74LVC161PW [NXP]
Presettable synchronous 4-bit binary counter; asynchronous reset; 可预置同步4位二进制计数器;异步复位
| 型号： | 74LVC161PW |
| 厂家： | 
NXP |
| 描述： | Presettable synchronous 4-bit binary counter; asynchronous reset |
| 文件： | 总14页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74LVC161
Presettable synchronous 4-bit binary
counter; asynchronous reset
Product specification
1998 May 20
Supersedes data of 1996 Aug 23
IC24 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter;
asynchronous reset
74LVC161
The 74LVC161 is a synchronous presettable binary counter which
features an internal look–head carry and can be used for
high–speed counting. Synchronous operation is provided by having
all flip–flops clocked simultaneously on the positive–going edge of
FEATURES
• Wide supply voltage range of 1.2 V to 3.6 V
• In accordance with JEDEC standard no. 8–1A
• Inputs accept voltages up to 5.5 V
• CMOS low power consumption
the clock (CP). The outputs (Q to Q ) of the counters may be
0
3
preset to a HIGH or LOW level. A LOW level at the parallel enable
input (PE) disables the counting action and causes the data at the
data inputs (D to D ) to be loaded into the counter on the
0
3
• Direct interface with TTL levels
positive–going edge of the clock (provided that the set–up and hold
time requirements for PE are met). Preset takes place regardless of
the levels at count enable inputs (CEP and CET). A low level at the
master reset input (MR) sets all four outputs of the flip–flops
• Asynchronous reset
• Synchronous counting and loading
• Two count enable inputs for n–bit cascading
• Positive edge–triggered clock
(Q to Q ) to LOW level regardless of the levels at CP, PE, CET
0
3
and CEP inputs (thus providing an asynchronous clear function).
The look–ahead carry simplifies serial cascading of the counters.
Both count enable inputs (CEP and CET) must be HIGH to count.
The CET input is fed forward to enable the terminal count output
(TC). The TC output thus enabled will produce a HIGH output pulse
• Output drive capability 50 W transmission lines @85_C
of a duration approximately equal to a HIGH level output of Q . This
0
DESCRIPTION
pulse can be used to enable the next cascaded stage. The
maximum clock frequency for the cascaded counters is determined
by the CP to TC propagation delay and CEP to CP set–up time,
according to the following formula:
The 74LVC161 is a high–performance, low–power, low–voltage,
Si–gate CMOS device and superior to most advanced CMOS
compatible TTL families.
1
_______________________________
f
=
max
tp
(max)
(CP to TC) + t (CEP to CP)
SU
QUICK REFERENCE DATA
GND = 0V; T
= 25°C; T = T ꢀ 2.5ns
amb
R F
SYMBOL
PARAMETER
Propagation delay
CONDITIONS
C = 50 pF
TYPICAL
UNIT
L
CP to Q
CP to TC
MR to Q
MR to TC
CET to TC
V
CC
= 3.3V
4.9
5.7
5.2
5.7
4.5
n
t
/t
ns
PHL PLH
n
f
maximum clock frequency
input capacitance
200
5.0
39
MHz
pF
MAX
C
I
C
power dissipation capacitance per gate
notes 1 and 2
pF
PD
NOTES:
1. C is used to determine the dynamic power dissipation (P in µW)
PD
D
2
2
P
= C x V
x f +Σ (C x V
x f where:
D
PD
CC
i
L
CC o )
f = input frequency in MHz; C = output load capacity in pF;
i
L
f = output frequency in MHz; V = supply voltage in V;
o
CC
2
Σ (C x V
x f = sum of the outputs
L
CC
o )
2. The condition is V = GND to V
1
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
74LVC161 D
DWG NUMBER
SOT109-1
16-Pin Plastic SO
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74LVC161 D
74LVC161 DB
74LVC161 PW
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
74LVC161 DB
SOT338-1
74LVC161PW DH
SOT403-1
2
1998 May 20
853-1864 19421
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter;
asynchronous reset
74LVC161
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
MR
CP
D0
D1
D2
1
2
3
4
5
16
V
CC
asynchronous master
reset (active LOW)
1
MR
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 CET
clock input (LOW-to-HIGH,
edge-triggered)
2
CP
3,4,5,6
D to D
0
data inputs
3
7
8
CEP
GND
count enable inputs
ground (0V)
D3
CEP
GND
6
7
8
9
PE
parallel enable input
(active LOW)
9
PE
SF00656
10
14,13,12,11
15
CET
count enable carry input
flip-flop outputs
Q to Q
0
3
TC
terminal count output
positive supply voltage
LOGIC SYMBOL
16
V
CC
15
LOGIC SYMBOL (IEEE/IEC)
CTR4
1
9
TC
R
3
4
Q
Q
0
D
D
14
13
0
1
M1
G3
G4
1
7
10
2
5
6
9
D
D
Q
Q
12
11
2
3
2
3
C2 /1,3,4+
PE
CEP
CP MR
CET
3
4
5
6
14
13
12
11
1,2 D
7
10
2
1
15
4 CT=15
V
= Pin 16
CC
GND = Pin 8
SY00065
SY00066
3
1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter;
asynchronous reset
74LVC161
FUNCTIONAL DIAGRAM
FUNCTION TABLE
INPUTS
MR CP CEP CET PE Dn
OUTPUTS
OPERATING
MODES
3
4
5
6
Qn
TC
Reset (clear)
Parallel load
Count
L
X
X
X
X
X
L
L
D
D
D
3
D
1
2
0
H
H
↑
↑
X
X
X
X
l
l
l
L
L
*
9
PE
h
H
PARALLEL LOAD
CIRCUITRY
H
↑
h
h
h
X
count
*
Hold
(do nothing)
NOTES:
H
H
X
X
l
X
l
h
h
X
X
q
q
*
n
CET
CEP
10
7
X
L
n
TC 15
*
=
The TC output is High when CET is High and the counter
is at Terminal Count (HHHH)
H
h
=
=
High voltage level
High voltage level one setup time prior to the Low-to-High
clock transition
BINARY
COUNTER
2
1
CP
L
l
=
=
Low voltage level
Low voltage level one setup time prior to the Low-to-High
clock transition
MR
q
=
Lower case letters indicate the state of the referenced
output one setup time prior to the Low-to-High clock
transition
Q
1
Q
3
Q
0
Q
2
X
↑
=
=
Don’t care
Low-to-High clock transition
14
13
12
11
TYPICAL TIMING SEQUENCE
SY00068
MR
PE
D0
D1
D2
D3
STATE DIAGRAM
0
1
2
3
4
5
6
7
8
CP
15
14
13
12
CEP
CET
Q0
Q1
Q2
Q3
11
10
9
TC
12
13
14
15
0
1
2
COUNT
INHIBIT
RESET PRESET
SF00664
SY00069
Typical timing sequence: reset outputs to zero; preset to binary
twelve; count to thirteen, fourteen, fifteen, zero, one, and two;
inhibit
4
1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter;
asynchronous reset
74LVC161
LOGIC DIAGRAM
D1
D0
D2
D3
CET
CEP
PE
FF0
FF1
FF2
FF3
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
CP
CP
CP
CP
CP
R
R
R
R
D
D
D
D
MR
Q2
Q3
TC
Q1
Q0
SY00070
5
1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter;
asynchronous reset
74LVC161
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN
2.7
1.2
0
MAX
DC supply voltage (for max. speed performance)
DC supply voltage (for low-voltage applications)
DC input voltage range
3.6
3.6
5.5
V
CC
V
V
I
V
V
V
O
DC output voltage range
0
V
CC
T
amb
Operating free-air temperature range
–40
+85
°C
V
CC
V
CC
= 1.2 to 2.7V
= 2.7 to 3.6V
0
0
20
10
t , t
r
Input rise and fall times
ns/V
f
1
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
UNIT
V
V
CC
I
IK
–0.5 to +6.5
–50
DC input diode current
DC input voltage
V t0
mA
V
I
V
I
Note 2
–0.5 to +5.5
"50
I
DC output diode current
DC output voltage
V
O
uV or V t 0
mA
V
OK
CC
O
V
O
Note 2
= 0 to V
CC
–0.5 to V +0.5
CC
I
O
DC output source or sink current
V
O
"50
"100
mA
mA
°C
I
, I
DC V or GND current
GND CC
CC
T
stg
Storage temperature range
–65 to +150
Power dissipation per package
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and
TSSOP)
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
500
500
P
TOT
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6
1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter;
asynchronous reset
74LVC161
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
1
MIN
TYP
MAX
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.2V
V
CC
V
HIGH level Input voltage
LOW level Input voltage
V
V
IH
= 2.7 to 3.6V
= 1.2V
2.0
GND
0.8
V
IL
= 2.7 to 3.6V
= 2.7V; V = V or V ; I = –12mA
V
V
V
V
*0.5
I
IH
IL
O
CC
CC
CC
CC
= 3.0V; V = V or V ; I = –100µA
*0.2
*0.6
*1.0
V
CC
I
IH
IL
O
V
OH
HIGH level output voltage
LOW level output voltage
V
= 3.0V; V = V or V I
= –12mA
I = –24mA
I
IH
IL; O
= 3.0V; V = V or V
IL; O
I
IH
= 2.7V; V = V or V ; I = 12mA
0.40
0.20
0.55
"5
10
I
IH
IL
O
= 3.0V; V = V or V ; I = 100µA
GND
V
OL
V
I
IH
IL
O
= 3.0V; V = V or V
I = 24mA
IL; O
I
IH
I
Input leakage current
= 3.6V; V = 5.5V or GND
"0.1
µA
µA
I
I
I
Quiescent supply current
= 3.6V; V = V or GND; I = 0
0.1
CC
I
CC
O
Additional quiescent supply current per
input pin
∆I
CC
V
CC
= 2.7V to 3.6V; V = V –0.6V; I = 0
5
500
µA
I
CC
O
NOTES:
1. All typical values are at V = 3.3V and T
= 25°C.
amb
CC
7
1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter;
asynchronous reset
74LVC161
AC CHARACTERISTICS
GND = 0 V; t = t v 2.5 ns; C = 50 pF; R = 500W; T
= –40_C to +85_C
r
f
L
L
amb
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V ±0.3V
V
CC
= 2.7V
V = 1.2V
CC
UNIT
1
MIN
TYP
MAX
MIN
MAX
TYP
t
t
Propagation delay
CP to Qn
PHL
PLH
1
1
–
–
4.9
8.0
9.5
7.8
9.0
10
–
–
9.0
11
8.8
10
11
–
24
28
22
28
20
–
ns
ns
t
t
Propagation delay
CP to TC
PHL
PLH
5.7
4.5
5.2
5.7
1.2
1.6
–0.3
1.0
1.2
2.1
–1.7
200
–
–
t
t
Propagation delay
CET to TC
PHL
PLH
2
–
ns
Propagation delay
MR to Qn
t
3
–
–
ns
PHL
PHL
Propagation delay
MR to TC
t
3
–
–
ns
Clock pulse width
HIGH or LOW
t
t
1
4.0
3.0
0
5.0
4.0
0
ns
W
Master reset
width LOW
3
–
–
–
ns
W
Removal time
MR to CP
t
3
–
–
–
ns
rem
Set-up time
D to CP
n
t
su
t
su
t
su
4
2.5
3.0
5.0
0
–
3.0
3.5
5.5
0
–
–
ns
Set-up time
PE to CP
4
–
–
–
ns
Set-up time
CEP, CET to CP
5
–
–
–
ns
Hold time
D , PE, CEP, CET to CP
n
t
h
4, 5
1
–
–
–
ns
Maximum clock
pulse frequency
f
125
–
110
–
–
MHz
max
NOTE:
1. These typical values are at V = 3.3V and T
= 25°C.
amb
CC
8
1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter;
asynchronous reset
74LVC161
AC WAVEFORMS
V
V
V
= 1.5 V at V w 2.7 V
M
CC
V
I
= 0.5 S V at V < 2.7 V
M
CC
CC
PE INPUT
GND
V
M
t
and V are the typical output voltage drop that occur with the
OL
OH
output load.
t
SU
SU
t
h
t
h
V
I
CP INPUT
GND
V
1/f
MAX
M
V
I
t
t
SU
SU
t
h
t
h
CP INPUT
GND
V
M
V
I
t
D
INPUT
GND
t
PLH
n
V
M
w
t
PHL
V
OH
V
M
Qn, TC OUTPUT
The shaded areas indicate when the input is permitted
to change for predictable output performance.
V
OL
SC00137
Waveform 4. Setup and hold times for the input (D ) and
parallel enable input (PE).
n
SY00071
Waveform 1. Clock (CP) to outputs (Q , TC) propagation
n
delays, the clock pulse width and the maximum clock
frequency.
V
I
CEP, CET
INPUT
V
t
M
GND
t
t
h
V
t
h
I
su
su
CET INPUT
GND
V
V
M
I
V
V
M
CP INPUT
GND
M
t
t
PLH
PHL
V
OH
V
TC OUTPUT
M
V
OL
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SC00138
SY00072
Waveform 5. CEP and CET setup and hold times.
Waveform 2. Input (CET) to output (TC) propagation delays.
TEST CIRCUIT
S
1
2 * V
V
CC
CC
V
I
Open
GND
MR INPUT
GND
V
M
500Ω
t
w
t
V
V
O
rem
I
V
I
PULSE
GENERATOR
D.U.T.
CP INPUT
GND
50pF
500Ω
R
T
C
L
t
PHL
V
OH
V
Qn, TC OUTPUT
M
SWITCH POSITION
V
OL
TEST
S
V
V
I
1
CC
SY00073
t
t
Open
< 2.7V
2.7–3.6V
V
CC
PLH/ PHL
Waveform 3. Master reset (MR) pulse width, the master reset
to output (Q , TC) propagation delays and the master reset to
2.7V
n
clock (CP) removal times.
SV00903
Waveform 6. Load circuitry for switching times.
9
1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter;
asynchronous reset
74LVC161
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
10
1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter;
asynchronous reset
74LVC161
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
11
1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter;
asynchronous reset
74LVC161
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
12
1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter;
asynchronous reset
74LVC161
NOTES
13
1998 May 20
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter;
asynchronous reset
74LVC161
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code
Date of release: 05-96
9397-750-04496
Document order number:
Philips
Semiconductors
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