74LVC16244AEV-T [NXP]
16-bit buffer/line driver; 5 V input/output tolerant; 3-state - Description: 3.3V 16-Bit Buffer/Line Driver; Non-Inverting (3-State) ; Logic switching levels: TTL ; Number of pins: 56 BGA ; Output drive capability: +/- 24 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 3.0@3.3V ns; Voltage: 1.2-3.6;
| 型号： | 74LVC16244AEV-T |
| 厂家： | 
NXP |
| 描述： | 16-bit buffer/line driver; 5 V input/output tolerant; 3-state - Description: 3.3V 16-Bit Buffer/Line Driver; Non-Inverting (3-State) ; Logic switching levels: TTL ; Number of pins: 56 BGA ; Output drive capability: +/- 24 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 3.0@3.3V ns; Voltage: 1.2-3.6 电池 驱动 逻辑集成电路 |
| 文件： | 总18页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
Rev. 08 — 17 November 2008
Product data sheet
1. General description
The 74LVC16244A; 74LVCH16244A are 16-bit non-inverting buffer/line drivers with
3-state bus compatible outputs. The device can be used as four 4-bit buffers, two 8-bit
buffers or one 16-bit buffer. It features four output enable inputs, (1OE to 4OE) each
controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a
high-impedance OFF-state.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices in mixed
3.3 V and 5 V applications.
The 74LVCH16244A bus hold on data inputs eliminates the need for external pull-up
resistors to hold unused inputs.
2. Features
I 5 V tolerant inputs/outputs for interfacing with 5 V logic
I Wide supply voltage range from 1.2 V to 3.6 V
I CMOS low power consumption
I MULTIBYTE flow-through standard pin-out architecture
I Low inductance multiple power and ground pins for minimum noise and ground
bounce
I Direct interface with TTL levels
I High-impedance when VCC = 0 V
I All data inputs have bus hold. (74LVCH16244A only)
I Complies with JEDEC standard JESD8-B / JESD36
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Temperature range Package
Name
Description
Version
74LVC16244ADL
74LVCH16244ADL
74LVC16244ADGG
74LVCH16244ADGG
74LVC16244AEV
74LVCH16244AEV
74LVC16244ABQ
74LVCH16244ABQ
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
SSOP48
plastic shrink small outline package; 48 leads;
body width 7.5 mm
SOT370-1
TSSOP48
VFBGA56
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
SOT362-1
plastic very thin fine-pitch ball grid array package; SOT702-1
56 balls; body 4.5 × 7 × 0.65 mm
HUQFN60U plastic thermal enhanced ultra thin quad flat
package; no leads; 60 terminals; UTLP based;
body 4 x 6 x 0.55 mm
SOT1025-1
4. Functional diagram
1
1A0
1A1
1A2
1A3
1OE
2A0
2A1
2A2
2A3
2OE
1Y0
1Y1
1Y2
1Y3
3A0
3A1
3A2
3A3
3OE
4A0
4A1
4A2
4A3
4OE
3Y0
1OE
2OE
3OE
4OE
EN1
EN2
EN3
EN4
47
46
44
43
1
2
3
5
6
36
35
33
32
25
30
29
27
26
24
13
14
16
17
48
25
24
3Y1
3Y2
3Y3
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2
3
1A0
1A1
1A2
1A3
2A0
2A1
2A2
2A3
3A0
3A1
3A2
3A3
4A0
4A1
4A2
4A3
1
1
1
1
1
2
3
4
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
3Y0
3Y1
3Y2
3Y3
4Y0
4Y1
4Y2
4Y3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
2Y0
2Y1
2Y2
2Y3
4Y0
4Y1
4Y2
4Y3
41
40
38
37
48
8
9
19
20
22
23
11
12
001aae506
001aae231
Pin numbers are shown for SSOP48 and TSSOP48
packages only.
Pin numbers are shown for SSOP48 and TSSOP48
packages only.
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74LVC_LVCH16244A_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 17 November 2008
2 of 18
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
V
CC
data input
to internal circuit
mna705
Fig 3. Bus hold circuit
5. Pinning information
5.1 Pinning
1
2
48
1OE
1Y0
1Y1
GND
1Y2
1Y3
2OE
1A0
1A1
GND
1A2
1A3
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
3
4
5
6
7
V
CC
V
CC
8
2Y0
2Y1
GND
2Y2
2Y3
3Y0
3Y1
GND
3Y2
3Y3
2A0
2A1
GND
2A2
2A3
3A0
3A1
GND
3A2
3A3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
74LVC16244A
74LVCH16244A
74LVC16244A
74LVCH16244A
ball A1
index area
1
2 3 4 5 6
A
B
C
D
E
F
G
H
J
V
CC
V
CC
4Y0
4Y1
4A0
4A1
GND
4A2
4A3
3OE
GND
4Y2
4Y3
K
4OE
001aaj053
Transparent top view
001aaj052
Fig 4. Pin configuration SOT370-1 (SSOP48) and
SOT362-1 (TSSOP48)
Fig 5. Pin configuration SOT702-1 (VFBGA56)
74LVC_LVCH16244A_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 17 November 2008
3 of 18
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
terminal 1
index area
D1
A32
D5
A31
A30
A29
A28
A27
D8
D4
B20
B19
B18
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
B1
B2
B3
B4
B5
B6
B7
B17
B16
B15
B14
B13
B12
B11
74LVC16244A
74LVCH16244A
(1)
GND
D6
B8
B9
B10
D7
D2
A11
A12
A13
A14
A15
A16
D3
001aaj054
Transparent top view
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig 6. Pin configuration SOT1025-1 (HUQFN60U)
74LVC_LVCH16244A_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 17 November 2008
4 of 18
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
5.2 Pin description
Table 2.
Symbol
Pin description
Pin
Description
SOT1025-1
SOT370-1 and
SOT362-1
SOT702-1
1OE, 2OE, 1, 48, 25, 24
3OE, 4OE
A1, A6, K6, K1
A30, A29, A14, A13
output enable input (active LOW)
1Y0 to 1Y3 2, 3, 5, 6
B2, B1, C2, C1
D2, D1, E2, E1
F1, F2, G1, G2
H1, H2, J1, J2
B20, A31, D5, D1
A2, B2, B3, A5
A6, B5, B6, A9
D2, D6, A12, B8
data output
data output
data output
data output
ground (0 V)
2Y0 to 2Y3 8, 9, 11, 12
3Y0 to 3Y3 13, 14, 16, 17
4Y0 to 4Y3 19, 20, 22, 23
GND
4, 10, 15, 21, 28,
34, 39, 45
B3, B4, D3, D4, G3, G4, A32, A3, A8, A11, A16,
J3, J4
A19, A24, A27
VCC
7, 18, 31, 42
C3, C4, H3, H4
B5, B6, C5, C6
D5, D6, E5, E6
F6, F5, G6, G5
H6, H5, J6, J5
A1, A10, A17, A26
B18, A28, D8, D4
A25, B16, B15, A22
A21, B13, B12, A18
D3, D7, A15, B10
supply voltage
data input
1A0 to 1A3 47, 46, 44, 43
2A0 to 2A3 41, 40, 38, 37
3A0 to 3A3 36, 35, 33, 32
4A0 to 4A3 30, 29, 27, 26
data input
data input
data input
n.c.
-
A2, A3, A4, A5, K2, K3, A4, A7, A20, A23, B1,
not connected
K4, K5
B4, B7, B9, B11, B14,
B17, B19
6. Functional description
Table 3.
Function table[1]
Control
Input
nAn
L
Output
nOE
L
nYn
L
L
H
H
H
X
Z
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
74LVC_LVCH16244A_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 17 November 2008
5 of 18
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
−0.5
−50
−0.5
-
Max
+6.5
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
VI
+6.5
±50
VCC + 0.5
+6.5
±50
100
-
IOK
output clamping current
output voltage
VO > VCC or VO < 0 V
output HIGH or LOW
output 3-state
mA
V
[2]
[2]
VO
−0.5
−0.5
-
V
IO
output current
VO = 0 V to VCC
mA
mA
mA
°C
ICC
IGND
Tstg
Ptot
supply current
-
ground current
−100
−65
storage temperature
total power dissipation
+150
Tamb = −40 °C to +125 °C;
(T)SSOP48 package
VFBGA56 package
[3]
[4]
[4]
-
-
-
500
mW
mW
mW
1000
1000
HUQFN60U package
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] Above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
[4] Above 70 °C the value of Ptot derates linearly with 1.8 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
maximum speed
performance
2.7
-
3.6
V
functional
1.2
0
-
-
-
-
-
-
-
3.6
5.5
VCC
5.5
+125
20
V
VI
input voltage
V
VO
output voltage
output HIGH or LOW
output 3-state
0
V
0
V
Tamb
ambient temperature
in free air
−40
0
°C
ns/V
ns/V
∆t/∆V
input transition rise and fall rate
VCC = 1.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
0
10
74LVC_LVCH16244A_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 17 November 2008
6 of 18
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions −40 °C to +85 °C
Min
Typ[1] Max
−40 °C to +125 °C Unit
Min
VCC
2.0
-
Max
VIH
HIGH-level input VCC = 1.2 V
voltage
VCC
-
-
-
-
-
-
-
-
V
V
V
V
VCC = 2.7 V to 3.6 V
2.0
VIL
LOW-level input
voltage
VCC = 1.2 V
VCC = 2.7 V to 3.6 V
-
-
0
0
0.8
-
0.8
VOH
HIGH-level output VI = VIH or VIL
voltage
IO = −100 µA;
VCC − 0.2 VCC
-
VCC − 0.3
-
V
V
CC = 2.7 V to 3.6 V
IO = −12 mA; VCC = 2.7 V
IO = −18 mA; VCC = 3.0 V
IO = −24 mA; VCC = 3.0 V
2.2
2.4
2.2
-
-
-
-
-
-
2.05
2.25
2.0
-
-
-
V
V
V
VOL
LOW-level output VI = VIH or VIL
voltage
IO = 100 µA;
CC = 2.7 V to 3.6 V
-
0
0.20
-
0.3
V
V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
-
-
-
-
-
0.40
0.55
±5
-
-
-
0.6
0.8
V
V
[2]
II
input leakage
current
VI = 5.5 V or GND; VCC = 3.6 V
±0.1
±20 µA
[2][3]
IOZ
OFF-state output VI = VIH or VIL;
current VO = 5.5 V or GND;
CC = 3.6 V
-
±0.1
±5
-
±20 µA
V
IOFF
ICC
power-off leakage VI or VO = 5.5 V; VCC = 0.0 V
current
-
-
±0.1
±10
-
-
±20 µA
supply current
VI = VCC or GND; IO = 0 A;
CC = 3.6 V
0.1
20
80
µA
V
∆ICC
CI
additional supply per input pin; VI = VCC − 0.6 V;
current IO = 0 A; VCC = 2.7 V to 3.6 V
-
5
5.0
-
500
-
5000 µA
input capacitance VCC = 0 V to 3.6 V;
VI = GND to VCC
-
-
-
-
-
-
-
-
-
-
pF
µA
µA
µA
[4][5]
[4][5]
[4][6]
IBHL
IBHH
IBHLO
bus hold current
LOW
VCC = 3.0 V; VI = 0.8 V
VCC = 3.0 V; VI = 2.0 V
VCC = 3.6 V
75
−75
500
60
−60
500
bus hold current
HIGH
-
bus hold
-
overdrive current
LOW
74LVC_LVCH16244A_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 17 November 2008
7 of 18
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions −40 °C to +85 °C
Min
Typ[1] Max
−500
−40 °C to +125 °C Unit
Min
Max
[4][6]
IBHHO
bus hold
V
CC = 3.6 V
-
-
−500
-
µA
overdrive current
HIGH
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.
[2] The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input terminal.
[3] For I/O ports the parameter IOZ includes the input leakage current.
[4] Valid for data inputs of bus hold parts only (74LVCH16244A). Note that control inputs do not have a bus hold circuit.
[5] The specified sustaining current at the data input holds the input below the specified VI level.
[6] The specified overdrive current at the data input forces the data input to the opposite input state.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ
Max
Min
Max
[1]
tpd
ten
tdis
propagation
delay
nAn to nYn; see Figure 7
VCC = 1.2 V
-
11.0
-
-
-
-
ns
ns
ns
VCC = 2.7 V
1.0
1.1
4.7
4.1
1.0
1.1
6.0
5.5
[2]
[1]
VCC = 3.0 V to 3.6 V
nOE to nYn; see Figure 8
VCC = 1.2 V
3.0
enable time
disable time
-
15.0
-
-
-
-
ns
ns
ns
VCC = 2.7 V
1.0
1.0
5.8
4.6
1.0
1.0
7.5
6.0
[2]
[1]
VCC = 3.0 V to 3.6 V
nOE to nYn; see Figure 8
VCC = 1.2 V
3.5
-
10.0
-
-
-
-
ns
ns
ns
VCC = 2.7 V
1.0
1.8
6.2
5.2
1.0
1.8
8.0
6.5
[2]
VCC = 3.0 V to 3.6 V
3.7
74LVC_LVCH16244A_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 17 November 2008
8 of 18
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ
Max
Min
Max
[3]
CPD
power
dissipation
capacitance
per buffer; VI = GND to VCC; VCC = 3.3 V
outputs enabled
-
-
12
-
-
-
-
-
-
pF
pF
outputs disabled
4.0
[1] tpd is the same as tPLH and tPHL
ten is the same as tPZL and tPZH
tdis is the same as tPLZ and tPHZ
.
.
.
[2] Typical values are measured at Tamb = 25 °C and VCC = 3.3 V.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
Σ(CL × VCC2 × fo) = sum of the outputs.
11. Waveforms
V
I
nAn input
GND
V
M
V
M
t
t
PLH
PHL
V
OH
V
V
M
nYn output
M
V
OL
mna171
Measurement points are given in Table 8.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. The input (nAn) to output (nYn) propagation delays
74LVC_LVCH16244A_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 17 November 2008
9 of 18
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
V
I
nOE input
GND
V
M
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna362
Measurement points are given in Table 8.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. 3-state enable and disable times.
Table 8.
Measurement points
Supply voltage
VCC
Input
VI
Output
VM
VM
VX
VY
1.2 V
VCC
0.5 × VCC
1.5 V
1.5 V
0.5 × VCC
1.5 V
VOL + 0.1 V
VOL + 0.3 V
VOL + 0.3 V
V
V
V
OH − 0.1 V
2.7 V
2.7 V
2.7 V
OH − 0.3 V
OH − 0.3 V
3.0 V to 3.6 V
1.5 V
74LVC_LVCH16244A_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 17 November 2008
10 of 18
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
t
W
V
I
90 %
negative
pulse
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
V
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 9. Load circuit for measuring switching times
Table 9.
Test data
Supply voltage
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPLZ, tPZL
2 × VCC
2 × VCC
2 × VCC
tPHZ, tPZH
GND
1.2 V
VCC
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
50 pF
50 pF
50 pF
500 Ω[1]
500 Ω
500 Ω
2.7 V
2.7 V
2.7 V
open
GND
3.0 V to 3.6 V
open
GND
[1] The circuit performs better when RL = 1 kΩ,
74LVC_LVCH16244A_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 17 November 2008
11 of 18
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
12. Package outline
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
D
E
A
X
c
y
H
v
M
A
E
Z
25
48
Q
A
2
A
A
(A )
3
1
θ
pin 1 index
L
p
L
24
1
detail X
w
M
b
p
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.
8o
0o
0.4
0.2
2.35
2.20
0.3
0.2
0.22 16.00
0.13 15.75
7.6
7.4
10.4
10.1
1.0
0.6
1.2
1.0
0.85
0.40
mm
2.8
0.25
0.635
1.4
0.25
0.18
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT370-1
MO-118
Fig 10. Package outline SOT370-1 (SSOP48)
74LVC_LVCH16244A_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 17 November 2008
12 of 18
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
H
v
M
A
y
E
Z
48
25
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
24
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.8
0.4
mm
1.2
0.5
1
0.25
0.25
0.08
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT362-1
MO-153
Fig 11. Package outline SOT362-1 (TSSOP48)
74LVC_LVCH16244A_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 17 November 2008
13 of 18
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm
SOT702-1
B
A
D
ball A1
index area
A
2
A
E
A
1
detail X
e
1
C
v M
w M
C
C
A B
b
e
y
y
C
1
1/2 e
K
J
H
G
F
e
e
2
E
D
C
B
A
1/2 e
X
ball A1
index area
1
2
3
4
5
6
DIMENSIONS (mm are the original dimensions)
A
A
A
b
e
y
UNIT
D
E
e
e
v
w
y
1
1
2
0
2.5
5 mm
1
2
max.
0.3
0.2
0.7
0.6
0.45
0.35
4.6
4.4
7.1
6.9
scale
mm
1
3.25 5.85
0.08
0.1
0.65
0.15 0.08
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
02-08-08
03-07-01
SOT702-1
MO-225
Fig 12. Package outline SOT702-1 (VFBGA56)
74LVC_LVCH16244A_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 17 November 2008
14 of 18
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
HUQFN60U: plastic thermal enhanced ultra thin quad flat package; no leads
60 terminals; UTLP based; body 4 x 6 x 0.55 mm
SOT1025-1
D
B
A
terminal 1
index area
E
A
A
1
detail X
e
2
M
M
v
C A
B
v
C A
C
B
e
1
b
M
M
w
C
w
C
1/2 e
e
y
y
C
1
L
1
D2
D6
D3
D7
A11
A16
B8
B10
L
eR
A10
B7
A17
e
B11
E
e
3
e
4
h
1/2 e
B1
A1
B17
A26
terminal 1
index area
D5
D1
D8
D4
B20
B18
A32
A27
D
h
X
k
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
b
D
D
h
E
E
e
e
1
e
2
e
3
e
4
eR
k
L
L
v
w
y
y
1
h
1
max
0.05 0.35 4.1
0.00 0.25
1.9
1.8
6.1
5.9
3.9
3.8
0.25 0.35 0.125
0.15 0.25 0.025
mm
0.6
0.5
1
2.5
3
4.5
0.5
0.07 0.05 0.08 0.1
3.9
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
- - -
JEDEC
JEITA
07-08-28
07-11-14
SOT1025-1
- - -
- - -
Fig 13. Package outline SOT1025-1 (HUQFN60U)
74LVC_LVCH16244A_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 17 November 2008
15 of 18
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
20081117
Data sheet status
Change notice
Supersedes
74LVC_LVCH16244A_8
Modifications:
Product data sheet
-
74LVC_LVCH16244A_7
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Added type number 74LVC16244ABQ and 74LVCH16244ABQ (HUQFN60U package)
74LVC_LVCH16244A_7
74LVC_LVCH16244A_6
74LVC_LVCH16244A_5
74LVC_H16244A_4
20031208
20030130
20021030
19971028
Product specification
Product specification
Product specification
Product specification
-
-
-
-
74LVC_LVCH16244A_6
74LVC_LVCH16244A_5
74LVC_H16244A_4
74LVC16244A_
74LVCH16244A_3
74LVC16244A_
19971028
Product specification
-
74LVC16244A_2
74LVCH16244A_3
74LVC16244A_2
74LVC16244A_1
19970630
-
Product specification
-
-
-
74LVC16244A_1
-
74LVC_LVCH16244A_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 17 November 2008
16 of 18
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC_LVCH16244A_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 17 November 2008
17 of 18
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
6
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 November 2008
Document identifier: 74LVC_LVCH16244A_8
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