74LVC169D,118 [NXP]
74LVC169 - Presettable synchronous 4-bit up/down binary counter SOP 16-Pin;
| 型号： | 74LVC169D,118 |
| 厂家： | 
NXP |
| 描述： | 74LVC169 - Presettable synchronous 4-bit up/down binary counter SOP 16-Pin 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总22页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC169
Presettable synchronous 4-bit up/down binary counter
Rev. 05 — 8 June 2009
Product data sheet
1. General description
The 74LVC169 is a synchronous presettable 4-bit binary counter which features an
internal look-ahead carry circuitry for cascading in high-speed counting applications.
Synchronous operation is provided by having all flip-flops clocked simultaneously so that
the outputs (pins Q0 to Q3) change simultaneously with each other when so instructed by
the count-enable (pins CEP and CET) inputs and internal gating. This mode of operation
eliminates the output counting spikes that are normally associated with asynchronous
(ripple clock) counters. A buffered clock (pin CP) input triggers the four flip-flops on the
LOW-to-HIGH transition of the clock.
The counter is fully programmable; that is, the outputs may be preset to any number
between 0 and its maximum count. Presetting is synchronous with the clock and takes
place regardless of the levels of the count enable inputs. A LOW level on the parallel
enable (pin PE) input disables the counter and causes the data at the Dn input to be
loaded into the counter on the next LOW-to-HIGH transition of the clock. The direction of
the counting is controlled by the up/down (pin U/D) input. When pin U/D is HIGH, the
counter counts up, when LOW, it counts down.
The look-ahead carry circuitry is provided for cascading counters for n-bit synchronous
applications without additional gating. Instrumental in accomplishing this function are two
count-enable (pins CEP and CET) inputs and a terminal count (pin TC) output. Both
count-enable (pins CEP and CET) inputs must be LOW to count. Input pin CET is fed
forward to enable the terminal count (pin TC) output. Pin TC thus enabled will produce a
LOW-level output pulse with a duration approximately equal to a HIGH level portion of
pin Q0 output. The LOW level pin TC pulse is used to enable successive cascaded
stages.
The 74LVC169 uses edge triggered J-K type flip-flops and has no constraints on changing
the control of data input signals in either state of the clock. The only requirement is that
the various inputs attain the desired state at least a set-up time before the next
LOW-to-HIGH transition of the clock and remain valid for the recommended hold time
thereafter.
The parallel load operation takes precedence over the other operations, as indicated in
the mode select table. When pin PE is LOW, the data on the input pins D0 to D3 enters
the flip-flops on the next LOW-to-HIGH transition of the clock.
74LVC169
NXP Semiconductors
Presettable synchronous 4-bit up/down binary counter
In order for counting to occur, both pins CEP and CET must be LOW and pin PE must be
HIGH. The pin U/D input determines the direction of the counting. The terminal count
output pin TC output is normally HIGH and goes LOW, provided that pin CET is LOW,
when a counter reaches 15 in the count up mode.The pin TC output state is not a function
of the count-enable parallel (pin CEP) input level. Since pin TC signal is derived by
decoding the flip-flop states, there exists the possibility of decoding spikes on pin TC. For
this reason the use of pin TC as a clock signal is not recommended; see the following
logic equations:
count enable = CEP • CET • PE
count up: TC = Q3 • Q2 • Q1 • Q0 • CET • U ⁄ D
count down: TC = Q3 • Q2 • Q1 • Q0 • CET • U ⁄ D
2. Features
I 5 V tolerant inputs for interfacing with 5 V logic
I Wide supply voltage range from 1.2 V to 3.6 V
I CMOS low power consumption
I Direct interface with TTL levels
I Up/down counting
I Two count enable inputs for n-bit cascading
I Built-in look-ahead carry capability
I Presettable for programmable operation
I Complies with JEDEC standard JESD8-B / JESD36
I ESD protection:
N HBM JESD22-A114D exceeds 2000 V
N CDM JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C.
3. Ordering information
Table 1.
Ordering information
Type number Temperature range Package
Name
Description
Version
74LVC169D
−40 °C to +125 °C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74LVC169DB −40 °C to +125 °C
74LVC169PW −40 °C to +125 °C
74LVC169BQ −40 °C to +125 °C
SSOP16
TSSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
SOT403-1
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
DHVQFN16 plastic dual in-line compatible thermal enhanced very thin SOT763-1
quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
74LVC169_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 8 June 2009
2 of 22
74LVC169
NXP Semiconductors
Presettable synchronous 4-bit up/down binary counter
4. Functional diagram
CTR4
M1 [LOAD]
9
M2 [COUNT]
M3 [UP]
3
4
5
6
1
M4 [DOWN]
D0
D1
D2
D3
15
10
7
3, 5 CT=15
4, 5 CT=0
G5
G6
9
1
PE
U/D
CP
2, 3, 5, 6+/C7
2, 3, 5, 6−
2
15
2
TC
7
CEP
CET
Q0
14
13
12
11
3
4
5
6
1,7D
[1]
[2]
[4]
[8]
10
Q1 Q2
Q3
11
14
13
12
001aaa645
001aaa646
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74LVC169_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 8 June 2009
3 of 22
74LVC169
NXP Semiconductors
Presettable synchronous 4-bit up/down binary counter
D
Q
Q
3
D0
14
13
12
11
Q0
Q1
Q2
Q3
CP
D
Q
Q
4
D1
CP
D
Q
Q
5
D2
CP
D
Q
Q
6
D3
CP
9
PE
7
10
CEP
CET
2
CP
1
U/D
15
TC
001aaa649
Fig 3. Logic diagram
74LVC169_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 8 June 2009
4 of 22
74LVC169
NXP Semiconductors
Presettable synchronous 4-bit up/down binary counter
5. Pinning information
5.1 Pinning
74LVC169
terminal 1
index area
74LVC169
2
3
4
5
6
7
15
14
13
12
11
10
CP
D0
TC
Q0
Q1
Q2
Q3
CET
U/D
CP
1
2
3
4
5
6
7
8
16 V
CC
D1
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 CET
D0
D2
D1
D3
(1)
GND
D2
CEP
D3
CEP
GND
001aaa682
9
PE
Transparent top view
001aaa644
(1) The die substrate is attached to this pad using
conductive die material. It can not be used as a supply
pin or input.
Fig 4. Pin configuration SO16 and
(T)SSOP16 package
Fig 5. Pin configuration DHVQFN16 package
5.2 Pin description
Table 2.
Symbol
U/D
Pin description
Pin
Description
1
up/down control input
CP
2
clock input (LOW-to-HIGH, edge-triggered)
data input
D0 to D3
CEP
3, 4, 5, 6
7
count enable input (active LOW)
ground (0 V)
GND
PE
8
9
parallel enable input (active LOW)
count enable carry input (active LOW)
flip-flop output
CET
10
Q0 to Q3
TC
14, 13, 12, 11
15
16
terminal count output (active LOW)
supply voltage
VCC
74LVC169_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 8 June 2009
5 of 22
74LVC169
NXP Semiconductors
Presettable synchronous 4-bit up/down binary counter
6. Functional description
Table 3.
Function table[1]
Operating modes
Input
Output
CP
↑
U/D
X
CEP
CET
PE
I
Dn
I
Qn
TC
*
Parallel load (Dn to Qn)
X
X
I
X
X
I
L
↑
X
l
h
H
*
Count up (increment)
Count down (decrement)
Hold (do nothing)
↑
h
h
h
h
h
X
X
X
X
count up
count down
qn
*
↑
I
I
I
*
↑
X
h
X
X
X
*
↑
X
qn
H
[1] H = HIGH voltage level steady state
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level steady state
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
qn = Lower case letters indicate state of referenced output prior to the LOW-to-HIGH clock transition
X = don’t care
↑ = LOW-to-HIGH clock transition
* = The TC is LOW when CET is LOW and the counter is at terminal count
Terminal count up is (HHHH) and terminal count down is (LLLL)
0
1
2
3
4
5
6
7
8
15
14
13
12
11
10
9
count down
count up
001aaa647
Fig 6. State diagram
74LVC169_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 8 June 2009
6 of 22
74LVC169
NXP Semiconductors
Presettable synchronous 4-bit up/down binary counter
PE
D0
D1
D2
D3
CP
U/D
CEP and CET
Q0
Q1
Q2
Q3
TC
13
14
15
0
1
2
2
2
1
0
15
14
13
load
count up
inhibit
count down
001aaa648
The following sequence is illustrated:
- Load (preset) to thirteen.
- Count up to fourteen, fifteen (maximum), zero, one and two.
- Inhibit.
- Countdown to one, zero (minimum), fifteen, fourteen and thirteen.
Fig 7. Typical timing sequence
74LVC169_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 8 June 2009
7 of 22
74LVC169
NXP Semiconductors
Presettable synchronous 4-bit up/down binary counter
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
−0.5
−50
−0.5
-
Max
+6.5
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
[1]
VI
+5.5
±50
VCC + 0.5
±50
100
-
IOK
output clamping current
output voltage
VO > VCC or VO < 0 V
mA
V
VO
−0.5
-
IO
output current
mA
mA
mA
°C
ICC
supply current
-
IGND
Tstg
Ptot
ground current
−100
−65
-
storage temperature
total power dissipation
+150
500
[2]
Tamb = −40 °C to +125 °C
mW
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO16 packages: above 70 °C, Ptot derates linearly with 8 mW/K.
For (T)SSOP16 packages: above 60 °C, Ptot derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 °C, Ptot derates linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
3.6
Unit
supply voltage
for maximum speed performance
for low-voltage applications
2.7
1.2
0
-
-
-
-
-
-
-
V
3.6
V
VI
input voltage
5.5
V
VO
output voltage
0
VCC
+125
20
V
Tamb
∆t/∆V
ambient temperature
in free air
−40
0
°C
ns/V
ns/V
input transition rise and fall rate VCC = 1.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
0
10
74LVC169_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 8 June 2009
8 of 22
74LVC169
NXP Semiconductors
Presettable synchronous 4-bit up/down binary counter
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
VCC
2.0
-
Typ[1]
Max
Min
VCC
2.0
-
Max
-
VIH
VIL
HIGH-level
input voltage
VCC = 1.2 V
-
-
-
-
-
-
V
V
V
V
VCC = 2.7 V to 3.6 V
VCC = 1.2 V
-
LOW-level
input voltage
GND
0.8
GND
0.8
VCC = 2.7 V to 3.6 V
VI = VIH or VIL
-
-
VOH
HIGH-level
output
voltage
IO = −100 µA; VCC = 2.7 V to 3.6 V VCC − 0.2 VCC
-
-
-
-
V
CC − 0.3
2.05
-
-
-
-
V
V
V
V
IO = −12 mA; VCC = 2.7 V
IO = −18 mA; VCC = 3.0 V
IO = −24 mA; VCC = 3.0 V
VI = VIH or VIL
2.2
2.4
2.2
-
-
-
2.25
2.0
VOL
LOW-level
output
voltage
IO = 100 µA; VCC = 2.7 V to 3.6 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
-
-
-
-
GND
0.2
0.4
0.55
±5
-
-
-
-
0.3
0.6
0.8
±20
V
-
-
V
V
II
input leakage VCC = 3.6 V; VI = 5.5 V or GND
current
±0.1
µA
ICC
∆ICC
supply
current
VCC = 3.6 V; VI = VCC or GND;
IO = 0 A
-
-
0.1
5
10
-
-
40
µA
additional
supply
per input pin; VCC = 1.65 V to 3.6 V;
VI = VCC − 0.6 V; IO = 0 A
500
5000 µA
current
CI
input
VCC = 0 V to 3.6 V; VI = GND to VCC
-
5.0
-
-
-
pF
capacitance
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.
74LVC169_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 8 June 2009
9 of 22
74LVC169
NXP Semiconductors
Presettable synchronous 4-bit up/down binary counter
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
[2]
[2]
[2]
[2]
tpd
propagation delay
CP to Qn; see Figure 8
VCC = 1.2 V
-
17
-
-
-
-
ns
ns
ns
VCC = 2.7 V
1.5
1.5
7.2
6.6
1.5
1.5
9.0
8.5
VCC = 3.0 V to 3.6 V
CP to TC; see Figure 8
VCC = 1.2 V
4.0
-
21
-
-
-
-
ns
ns
ns
VCC = 2.7 V
1.5
1.5
8.8
7.5
1.5
1.5
11.0
9.5
VCC = 3.0 V to 3.6 V
CET to TC; see Figure 9
VCC = 1.2 V
4.8
-
19
-
-
-
-
ns
ns
ns
VCC = 2.7 V
1.5
1.5
7.2
6.2
1.5
1.5
9.0
8.0
VCC = 3.0 V to 3.6 V
U/D to TC; see Figure 10
VCC = 1.2 V
4.1
-
21
-
-
-
-
ns
ns
ns
VCC = 2.7 V
1.5
1.5
8.2
6.9
1.5
1.5
10.5
9.0
VCC = 3.0 V to 3.6 V
CP HIGH or LOW; see Figure 8
VCC = 2.7 V
3.7
tW
pulse width
set-up time
5.0
4.0
-
-
-
5.0
4.0
-
-
ns
ns
VCC = 3.0 V to 3.6 V
Dn to CP; see Figure 11
VCC = 2.7 V
1.2
tsu
3.0
2.5
-
-
-
3.0
2.5
-
-
ns
ns
VCC = 3.0 V to 3.6 V
PE to CP; see Figure 11
VCC = 2.7 V
1.0
3.5
3.0
-
-
-
3.5
3.0
-
-
ns
ns
VCC = 3.0 V to 3.6 V
U/D to CP; see Figure 12
VCC = 2.7 V
1.2
6.5
5.5
-
-
-
6.5
5.5
-
-
ns
ns
VCC = 3.0 V to 3.6 V
CEP, CET to CP; see Figure 12
VCC = 2.7 V
2.8
5.5
4.5
-
-
-
5.5
4.5
-
-
ns
ns
VCC = 3.0 V to 3.6 V
2.1
th
hold time
Dn, PE, CEP, CET, U/D to CP;
see Figure 11 and 12
VCC = 2.7 V
0.0
0.5
-
-
-
0.0
0.5
-
-
ns
ns
VCC = 3.0 V to 3.6 V
0.0
74LVC169_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 8 June 2009
10 of 22
74LVC169
NXP Semiconductors
Presettable synchronous 4-bit up/down binary counter
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
fmax
maximum
frequency
see Figure 8
VCC = 2.7 V
150
150
-
-
200
-
-
-
150
150
-
-
-
MHz
MHz
ns
VCC = 3.0 V to 3.6 V
VCC = 3.0 V to 3.6 V
per input pin; VI = GND to VCC
VCC = 3.0 V to 3.6 V
[3]
[4]
tsk(0)
CPD
output skew time
1.0
1.5
power dissipation
capacitance
-
20
-
-
-
pF
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL
.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
N = number of inputs switching
∑(CL × VCC2 × fo) = sum of outputs
11. Waveforms
1/f
max
V
I
CP input
V
M
GND
t
W
t
t
PLH
PHL
V
OH
V
Qn, TC output
M
V
OL
001aaa651
Measurement points are given in Table 8.
Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 8. Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, and the maximum frequency
74LVC169_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 8 June 2009
11 of 22
74LVC169
NXP Semiconductors
Presettable synchronous 4-bit up/down binary counter
V
I
V
CET
M
GND
t
t
PLH
PHL
V
V
OH
I
V
TC
M
V
OL
001aaa652
Measurement points are given in Table 8.
Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 9. Input (CET) to output (TC) propagation delays
V
I
V
U/D
TC
M
GND
t
t
PLH
PHL
V
V
OH
I
V
M
V
OL
001aaa653
Measurement points are given in Table 8.
Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 10. The up/down control input (U/D) to output (TC) propagation delays
74LVC169_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 8 June 2009
12 of 22
74LVC169
NXP Semiconductors
Presettable synchronous 4-bit up/down binary counter
V
I
V
PE input
M
t
GND
t
su
su
t
t
h
h
V
I
V
CP input
M
GND
t
t
su
su
t
t
h
h
V
I
V
Dn input
M
GND
001aaa654
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8.
Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 11. Set-up and hold times for the input (Dn) and parallel enable input (PE)
V
I
V
M
CEP, CET, U/D input
GND
t
t
h
h
t
t
su
su
V
I
V
CP input
M
GND
001aaa655
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8.
Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 12. Set-up and hold times for count enable inputs (CEP and CET) and control input (U/D)
Table 8.
Measurement points
Supply voltage
VCC
Input
VM
Output
VM
1.2 V
0.5VCC
1.5 V
1.5 V
0.5VCC
1.5 V
1.5 V
2.7 V
3.0 V to 3.6 V
74LVC169_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 8 June 2009
13 of 22
74LVC169
NXP Semiconductors
Presettable synchronous 4-bit up/down binary counter
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 9.
Definitions for test circuit:
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 13. Test circuit for measuring switching times
Table 9.
Test data
Supply voltage
Input
VI
Load
CL
S1 position
tPLH: tPHL
open
tr, tf
RL
1.2 V
VCC
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
50 pF
50 pF
500 Ω[1]
500 Ω
500 Ω
2.7 V
2.7 V
2.7 V
open
3.0 V to 3.6 V
open
[1] The circuit preforms better when RL = 1000 kΩ.
74LVC169_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 8 June 2009
14 of 22
74LVC169
NXP Semiconductors
Presettable synchronous 4-bit up/down binary counter
12. Application information
CP
U/D
PE
D0 D1 D2 D3
D0 D1 D2 D3
PE
D0 D1 D2 D3
PE
D0 D1 D2 D3
PE
PE
U/D
CP
U/D
CP
U/D
CP
U/D
CP
TC
CEP
CET
TC
CEP
CET
TC
CEP
CET
TC
CEP
CET
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
least significant
4-bit counter
most significant
4-bit counter
001aaa650
Fig 14. Synchronous multistage counting scheme
74LVC169_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 8 June 2009
15 of 22
74LVC169
NXP Semiconductors
Presettable synchronous 4-bit up/down binary counter
13. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 15. Package outline SOT109-1 (SO16)
74LVC169_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 8 June 2009
16 of 22
74LVC169
NXP Semiconductors
Presettable synchronous 4-bit up/down binary counter
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
Fig 16. Package outline SOT338-1 (SSOP16)
74LVC169_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 8 June 2009
17 of 22
74LVC169
NXP Semiconductors
Presettable synchronous 4-bit up/down binary counter
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 17. Package outline SOT403-1 (TSSOP16)
74LVC169_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 8 June 2009
18 of 22
74LVC169
NXP Semiconductors
Presettable synchronous 4-bit up/down binary counter
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
Fig 18. Package outline SOT763-1 (DHVQFN16)
74LVC169_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 8 June 2009
19 of 22
74LVC169
NXP Semiconductors
Presettable synchronous 4-bit up/down binary counter
14. Abbreviations
Table 10. Abbreviations
Acronym
CDM
DUT
Description
Charged Device Model
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
TTL
Transistor-Transistor Logic
15. Revision history
Table 11. Revision history
Document ID
Release date
20090608
Data sheet status
Change notice
Supersedes
74LVC169_5
Product data sheet
-
74LVC169_4
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been updated and adapted to the new company name where appropriate.
• Table 7 “Dynamic characteristics” 3.0 V to 3.6 V max tPLH and tPHL values changed due to
ECN06_058.
74LVC169_4
74LVC169_3
74LVC169_2
74LVC169_1
20041014
20040512
19980520
19960823
Product specification
Product specification
Product specification
Product specification
-
-
-
-
74LVC169_3
74LVC169_2
74LVC169_1
-
74LVC169_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 8 June 2009
20 of 22
74LVC169
NXP Semiconductors
Presettable synchronous 4-bit up/down binary counter
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC169_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 8 June 2009
21 of 22
74LVC169
NXP Semiconductors
Presettable synchronous 4-bit up/down binary counter
18. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
6
Functional description . . . . . . . . . . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended operating conditions. . . . . . . . 8
Static characteristics. . . . . . . . . . . . . . . . . . . . . 9
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Application information. . . . . . . . . . . . . . . . . . 15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20
7
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 21
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 8 June 2009
Document identifier: 74LVC169_5
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