74LVC1G11GV [NXP]

Single 3-input AND gate; 单三输入与门
74LVC1G11GV
型号: 74LVC1G11GV
厂家: NXP    NXP
描述:

Single 3-input AND gate
单三输入与门

栅极 逻辑集成电路 光电二极管
文件: 总14页 (文件大小:70K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
74LVC1G11  
Single 3-input AND gate  
Rev. 01 — 30 November 2004  
Product data sheet  
1. General description  
The 74LVC1G11 is a high-performance, low-voltage, Si-gate CMOS device and superior  
to most advanced CMOS compatible TTL families.  
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of  
this device in a mixed 3.3 V and 5 V environment.  
This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry  
disables the output, preventing the damaging backflow current through the device when  
it is powered down.  
Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and  
fall times.  
The 74LVC1G11 provides a single 3-input AND gate.  
2. Features  
Wide supply voltage range from 1.65 V to 5.5 V  
5 V tolerant inputs for interfacing with 5 V logic  
High noise immunity  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8-B/JESD36 (2.7 V to 3.6 V).  
±24 mA output drive (VCC = 3.0 V)  
ESD protection:  
HBM EIA/JESD22-A114-B exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V.  
CMOS low power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Multiple package options  
Specified from 40 °C to +85 °C and 40 °C to +125 °C.  
74LVC1G11  
Philips Semiconductors  
Single 3-input AND gate  
3. Quick reference data  
Table 1:  
Quick reference data  
GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
tPHL, tPLH propagation delay A, CL = 50 pF; VCC = 3.3 V  
B and C to Y  
1.0  
2.6  
4.3  
ns  
CI  
input capacitance  
-
-
4
-
-
pF  
pF  
[1] [2]  
CPD  
power dissipation  
capacitance  
VCC = 3.3 V  
13  
[1] CPD is used to determine the dynamic power dissipation (PD in µW).  
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in V;  
N = number of inputs switching;  
Σ(CL × VCC2 × fo) = sum of the outputs.  
[2] The condition is VI = GND to VCC  
.
4. Ordering information  
Table 2:  
Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74LVC1G11GW  
74LVC1G11GV  
40 °C to +125 °C  
40 °C to +125 °C  
SC-88  
SC-74  
plastic surface mounted package; 6 leads  
plastic surface mounted package; 6 leads  
SOT363  
SOT457  
5. Marking  
Table 3:  
Marking  
Type number  
74LVC1G11GW  
74LVC1G11GV  
Marking code  
VU  
V11  
6. Functional diagram  
&
A
B
C
1
3
6
1
3
6
4
Y
4
001aac033  
001aac029  
Fig 1. Logic symbol  
Fig 2. IEC logic symbol  
9397 750 14209  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data sheet  
Rev. 01 — 30 November 2004  
2 of 14  
74LVC1G11  
Philips Semiconductors  
Single 3-input AND gate  
A
B
C
Y
001aac030  
Fig 3. Logic diagram  
7. Pinning information  
7.1 Pinning  
1
2
3
6
5
4
A
GND  
B
C
11  
V
CC  
Y
001aac032  
Fig 4. Pin configuration  
7.2 Pin description  
Table 4:  
Pin description  
Symbol  
Pin  
1
Description  
data input  
A
GND  
B
2
ground (0 V)  
data input  
3
Y
4
data output  
supply voltage  
data input  
VCC  
C
5
6
9397 750 14209  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data sheet  
Rev. 01 — 30 November 2004  
3 of 14  
74LVC1G11  
Philips Semiconductors  
Single 3-input AND gate  
8. Functional description  
8.1 Function table  
Table 5:  
Function table[1]  
Input  
Output  
A
H
L
B
H
X
L
C
H
X
X
L
Y
H
L
L
L
X
X
X
[1] H = HIGH voltage level;  
L = LOW voltage level;  
X = don’t care.  
9. Limiting values  
Table 6:  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to  
GND (ground = 0 V).  
Symbol Parameter  
Conditions  
Min  
0.5  
0.5  
0.5  
0.5  
-
Max  
+6.5  
+6.5  
Unit  
V
VCC  
VI  
supply voltage  
input voltage  
output voltage  
[1]  
[1] [2]  
[1] [2]  
V
VO  
active mode  
Power-down mode  
VI < 0 V  
VCC + 0.5 V  
+6.5  
50  
±50  
±50  
V
IIK  
IOK  
IO  
input diode current  
mA  
mA  
mA  
output diode current VO > VCC or VO < 0 V  
-
output source or sink VO = 0 V to VCC  
current  
-
ICC, IGND VCC or GND current  
-
±100  
+150  
250  
mA  
°C  
Tstg  
Ptot  
storage temperature  
power dissipation  
65  
Tamb = 40 °C to +125 °C  
-
mW  
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.  
9397 750 14209  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data sheet  
Rev. 01 — 30 November 2004  
4 of 14  
74LVC1G11  
Philips Semiconductors  
Single 3-input AND gate  
10. Recommended operating conditions  
Table 7:  
Recommended operating conditions  
Symbol Parameter  
Conditions  
Min  
1.65  
0
Typ  
Max Unit  
VCC  
VI  
supply voltage  
input voltage  
output voltage  
-
-
-
-
5.5  
5.5  
VCC  
5.5  
V
V
V
V
VO  
active mode  
0
Power-down mode;  
VCC = 0 V  
0
Tamb  
tr, tf  
ambient temperature  
40  
0
-
-
-
+125 °C  
input rise and fall times  
VCC = 1.65 V to 2.7 V  
VCC = 2.7 V to 5.5 V  
20  
10  
ns/V  
ns/V  
0
11. Static characteristics  
Table 8:  
Static characteristics  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Tamb = 40 °C to +85 °C[1]  
VIH  
HIGH-level input voltage VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
0.65 × VCC  
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7  
VCC = 2.7 V to 3.6 V  
2.0  
VCC = 4.5 V to 5.5 V  
0.7 × VCC  
VIL  
LOW-level input voltage VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
-
-
-
-
0.35 × VCC  
0.7  
VCC = 2.7 V to 3.6 V  
0.8  
VCC = 4.5 V to 5.5 V  
0.3 × VCC  
VOH  
HIGH-level output  
voltage  
VI = VIH or VIL  
IO = 100 µA; VCC = 1.65 V to 5.5 V  
IO = 4 mA; VCC = 1.65 V  
IO = 8 mA; VCC = 2.3 V  
IO = 12 mA; VCC = 2.7 V  
IO = 24 mA; VCC = 3.0 V  
IO = 32 mA; VCC = 4.5 V  
VI = VIH or VIL  
V
CC 0.1  
-
-
-
-
-
-
-
V
V
V
V
V
V
1.2  
1.9  
2.2  
2.3  
3.8  
1.54  
2.15  
2.50  
2.62  
4.11  
VOL  
LOW-level output  
voltage  
IO = 100 µA; VCC = 1.65 V to 5.5 V  
IO = 4 mA; VCC = 1.65 V  
IO = 8 mA; VCC = 2.3 V  
IO = 12 mA; VCC = 2.7 V  
IO = 24 mA; VCC = 3.0 V  
IO = 32 mA; VCC = 4.5 V  
VI = 5.5 V or GND; VCC = 5.5 V  
VI or VO = 5.5 V; VCC = 0 V  
-
-
-
-
-
-
-
-
-
0.10  
0.45  
0.30  
0.40  
0.55  
0.55  
±5  
V
0.07  
0.12  
0.17  
0.33  
0.39  
±0.1  
±0.1  
V
V
V
V
V
ILI  
input leakage current  
µA  
µA  
Ioff  
power-off leakage  
current  
±10  
9397 750 14209  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data sheet  
Rev. 01 — 30 November 2004  
5 of 14  
74LVC1G11  
Philips Semiconductors  
Single 3-input AND gate  
Table 8:  
Static characteristics …continued  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
quiescent supply current VI = VCC or GND; IO = 0 A;  
CC = 5.5 V  
VI = VCC 0.6 V; IO = 0 A;  
CC = 2.3 V to 5.5 V  
Min  
Typ  
Max  
Unit  
ICC  
ICC  
CI  
-
0.1  
10  
µA  
V
additional quiescent  
supply current per pin  
-
-
5
4
500  
-
µA  
V
input capacitance  
pF  
Tamb = 40 °C to +125 °C  
VIH  
HIGH-level input voltage VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
0.65 × VCC  
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7  
-
VCC = 2.7 V to 3.6 V  
2.0  
-
VCC = 4.5 V to 5.5 V  
0.7 × VCC  
-
VIL  
LOW-level input voltage VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
-
-
-
-
0.35 × VCC  
0.7  
VCC = 2.7 V to 3.6 V  
0.8  
VCC = 4.5 V to 5.5 V  
0.3 × VCC  
VOH  
HIGH-level output  
voltage  
VI = VIH or VIL  
IO = 100 µA; VCC = 1.65 V to 5.5 V  
IO = 4 mA; VCC = 1.65 V  
IO = 8 mA; VCC = 2.3 V  
IO = 12 mA; VCC = 2.7 V  
IO = 24 mA; VCC = 3.0 V  
IO = 32 mA; VCC = 4.5 V  
VI = VIH or VIL  
V
CC 0.1  
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
0.95  
1.7  
1.9  
2.0  
3.4  
VOL  
LOW-level output  
voltage  
IO = 100 µA; VCC = 1.65 V to 5.5 V  
IO = 4 mA; VCC = 1.65 V  
IO = 8 mA; VCC = 2.3 V  
IO = 12 mA; VCC = 2.7 V  
IO = 24 mA; VCC = 3.0 V  
IO = 32 mA; VCC = 4.5 V  
VI = 5.5 V or GND; VCC = 5.5 V  
VI or VO = 5.5 V; VCC = 0 V  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.10  
0.70  
0.45  
0.60  
0.80  
0.80  
±100  
±200  
V
V
V
V
V
V
ILI  
input leakage current  
µA  
µA  
Ioff  
power-off leakage  
current  
ICC  
quiescent supply current VI = VCC or GND; IO = 0 A;  
CC = 5.5 V  
-
-
-
-
200  
µA  
µA  
V
ICC  
additional quiescent  
supply current per pin  
VI = VCC 0.6 V; IO = 0 A;  
CC = 2.3 V to 5.5 V  
5000  
V
[1] All typical values are measured at Tamb = 25 °C.  
9397 750 14209  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data sheet  
Rev. 01 — 30 November 2004  
6 of 14  
74LVC1G11  
Philips Semiconductors  
Single 3-input AND gate  
12. Dynamic characteristics  
Table 9:  
Dynamic characteristics  
GND = 0 V; see Figure 6 for test circuit.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Tamb = 40 °C to +85 °C[1]  
tPHL, tPLH propagation delay  
A, B and C to Y  
see Figure 5  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V  
1.5  
1.0  
1.0  
1.0  
1.0  
-
4.7  
3.0  
3.0  
2.6  
1.9  
13  
17.2  
6.2  
6.0  
4.9  
3.5  
-
ns  
ns  
ns  
ns  
ns  
pF  
VCC = 3.0 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
VCC = 3.3 V  
[2] [3]  
CPD  
power dissipation  
capacitance  
Tamb = 40 °C to +125 °C  
tPHL, tPLH propagation delay  
A, B and C to Y  
see Figure 5  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V  
1.5  
1.0  
1.0  
1.0  
1.0  
-
-
-
-
-
21.5  
7.8  
7.5  
6.2  
4.4  
ns  
ns  
ns  
ns  
ns  
VCC = 3.0 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
[1] All typical values are measured at Tamb = 25 °C and nominal VCC  
.
[2] CPD is used to determine the dynamic power dissipation (PD in µW).  
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in V;  
N = number of inputs switching;  
Σ(CL × VCC2 × fo) = sum of the outputs.  
[3] The condition is VI = GND to VCC  
.
9397 750 14209  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data sheet  
Rev. 01 — 30 November 2004  
7 of 14  
74LVC1G11  
Philips Semiconductors  
Single 3-input AND gate  
13. Waveforms  
V
I
A, B, C  
input  
V
M
GND  
t
t
PLH  
PHL  
V
OH  
V
M
Y output  
V
OL  
t
THL  
001aac031  
Measurement points are given in Table 10.  
VOL and VOH are typical output voltage drop that occur with the output load.  
Fig 5. The input (A, B, C) to output (Y) propagation delays  
Table 10: Measurement points  
Supply voltage  
VCC  
Input  
Output  
VM  
VM  
1.65 V to 1.95 V  
2.3 V to 2.7 V  
2.7 V  
0.5 × VCC  
0.5 × VCC  
1.5 V  
0.5 × VCC  
0.5 × VCC  
1.5 V  
3.0 V to 3.6 V  
4.5 V to 5.5 V  
1.5 V  
1.5 V  
0.5 × VCC  
0.5 × VCC  
V
EXT  
V
CC  
R
L
V
I
V
O
PULSE  
GENERATOR  
D.U.T.  
C
L
R
L
R
T
mna616  
Test data is given in Table 11.  
Definitions for test circuit:  
RL = Load resistor.  
CL = Load capacitance including jig and probe capacitance  
RT = Termination resistance should be equal to the output impedance Zo of the pulse  
generator.  
Fig 6. Load circuitry for switching times  
9397 750 14209  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data sheet  
Rev. 01 — 30 November 2004  
8 of 14  
74LVC1G11  
Philips Semiconductors  
Single 3-input AND gate  
Table 11: Test data  
Supply voltage  
VCC  
Input  
VI  
Load  
CL  
VEXT  
tr = tf  
RL  
tPLH, tPHL  
1.65 V to 1.95 V  
2.3 V to 2.7 V  
2.7 V  
VCC  
VCC  
2.7 V  
2.7 V  
VCC  
2.0 ns  
2.0 ns  
2.5 ns  
2.5 ns  
2.5 ns  
30 pF  
30 pF  
50 pF  
50 pF  
50 pF  
1 kΩ  
open  
open  
open  
open  
open  
500 Ω  
500 Ω  
500 Ω  
500 Ω  
3.0 V to 3.6 V  
4.5 V to 5.5 V  
9397 750 14209  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data sheet  
Rev. 01 — 30 November 2004  
9 of 14  
74LVC1G11  
Philips Semiconductors  
Single 3-input AND gate  
14. Package outline  
Plastic surface mounted package; 6 leads  
SOT363  
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1  
index  
A
A
1
1
2
3
c
e
1
b
p
L
p
w
M B  
e
detail X  
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
1
UNIT  
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max  
0.30  
0.20  
1.1  
0.8  
0.25  
0.10  
2.2  
1.8  
1.35  
1.15  
2.2  
2.0  
0.45  
0.15  
0.25  
0.15  
mm  
0.1  
1.3  
0.65  
0.2  
0.2  
0.1  
REFERENCES  
JEDEC JEITA  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
97-02-28  
04-11-08  
SOT363  
SC-88  
Fig 7. Package outline SOT363 (SC-88)  
9397 750 14209  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data sheet  
Rev. 01 — 30 November 2004  
10 of 14  
74LVC1G11  
Philips Semiconductors  
Single 3-input AND gate  
Plastic surface mounted package; 6 leads  
SOT457  
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1  
index  
A
A
1
c
1
2
3
L
p
e
b
p
w
M B  
detail X  
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
UNIT  
A
A
b
c
D
E
e
H
L
Q
v
w
y
p
1
p
E
0.1  
0.013  
0.40  
0.25  
1.1  
0.9  
0.26  
0.10  
3.1  
2.7  
1.7  
1.3  
3.0  
2.5  
0.6  
0.2  
0.33  
0.23  
mm  
0.95  
0.2  
0.2  
0.1  
REFERENCES  
JEDEC JEITA  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
01-05-04  
04-11-08  
SOT457  
SC-74  
Fig 8. Package outline SOT457 (SC-74)  
9397 750 14209  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data sheet  
Rev. 01 — 30 November 2004  
11 of 14  
74LVC1G11  
Philips Semiconductors  
Single 3-input AND gate  
15. Revision history  
Table 12: Revision history  
Document ID  
Release date Data sheet status  
20041130 Product data sheet  
Change notice  
Doc. number  
9397 750 14209  
Supersedes  
74LVC1G11_1  
-
-
9397 750 14209  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data sheet  
Rev. 01 — 30 November 2004  
12 of 14  
74LVC1G11  
Philips Semiconductors  
Single 3-input AND gate  
16. Data sheet status  
Level Data sheet status[1] Product status[2] [3]  
Definition  
I
Objective data  
Development  
This data sheet contains data from the objective specification for product development. Philips  
Semiconductors reserves the right to change the specification in any manner without notice.  
II  
Preliminary data  
Qualification  
This data sheet contains data from the preliminary specification. Supplementary data will be published  
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in  
order to improve the design and supply the best possible product.  
III  
Product data  
Production  
This data sheet contains data from the product specification. Philips Semiconductors reserves the  
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant  
changes will be communicated via a Customer Product/Process Change Notification (CPCN).  
[1]  
[2]  
Please consult the most recently issued data sheet before initiating or completing a design.  
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at  
URL http://www.semiconductors.philips.com.  
[3]  
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.  
17. Definitions  
18. Disclaimers  
Short-form specification The data in a short-form specification is  
extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
Life support — These products are not designed for use in life support  
appliances, devices, or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors  
customers using or selling these products for use in such applications do so  
at their own risk and agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
Limiting values definition Limiting values given are in accordance with  
the Absolute Maximum Rating System (IEC 60134). Stress above one or  
more of the limiting values may cause permanent damage to the device.  
These are stress ratings only and operation of the device at these or at any  
other conditions above those given in the Characteristics sections of the  
specification is not implied. Exposure to limiting values for extended periods  
may affect device reliability.  
Right to make changes — Philips Semiconductors reserves the right to  
make changes in the products - including circuits, standard cells, and/or  
software - described or contained herein in order to improve design and/or  
performance. When the product is in full production (status ‘Production’),  
relevant changes will be communicated via a Customer Product/Process  
Change Notification (CPCN). Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no  
license or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products are  
free from patent, copyright, or mask work right infringement, unless otherwise  
specified.  
Application information Applications that are described herein for any  
of these products are for illustrative purposes only. Philips Semiconductors  
make no representation or warranty that such applications will be suitable for  
the specified use without further testing or modification.  
19. Contact information  
For additional information, please visit: http://www.semiconductors.philips.com  
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com  
9397 750 14209  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data sheet  
Rev. 01 — 30 November 2004  
13 of 14  
74LVC1G11  
Philips Semiconductors  
Single 3-input AND gate  
20. Contents  
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2  
7
7.1  
7.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3  
8
8.1  
9
Functional description . . . . . . . . . . . . . . . . . . . 4  
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Recommended operating conditions. . . . . . . . 5  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5  
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7  
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 13  
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Contact information . . . . . . . . . . . . . . . . . . . . 13  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
© Koninklijke Philips Electronics N.V. 2004  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior  
written consent of the copyright owner. The information presented in this document does  
not form part of any quotation or contract, is believed to be accurate and reliable and may  
be changed without notice. No liability will be accepted by the publisher for any  
consequence of its use. Publication thereof does not convey nor imply any license under  
patent- or other industrial or intellectual property rights.  
Date of release: 30 November 2004  
Document number: 9397 750 14209  
Published in The Netherlands  

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