74LVC1G53_08 [NXP]
2-channel analog multiplexer/demultiplexer; 2通道模拟多路复用器/多路分解器
| 型号： | 74LVC1G53_08 |
| 厂家： | 
NXP |
| 描述： | 2-channel analog multiplexer/demultiplexer |
| 文件： | 总23页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC1G53
2-channel analog multiplexer/demultiplexer
Rev. 05 — 11 June 2008
Product data sheet
1. General description
The 74LVC1G53 is a low-power, low-voltage, high-speed, Si-gate CMOS device.
The 74LVC1G53 provides one analog multiplexer/demultiplexer with a digital select
input (S), two independent inputs/outputs (Y0 and Y1), a common input/output (Z) and an
active LOW enable input (E). When pin E is HIGH, the switch is turned off.
Schmitt-trigger action at the select and enable inputs makes the circuit tolerant of slower
input rise and fall times across the entire VCC range from 1.65 V to 5.5 V.
2. Features
I Wide supply voltage range from 1.65 V to 5.5 V
I Very low ON resistance:
N 7.5 Ω (typical) at VCC = 2.7 V
N 6.5 Ω (typical) at VCC = 3.3 V
N 6 Ω (typical) at VCC = 5 V
I Switch current capability of 32 mA
I High noise immunity
I CMOS low-power consumption
I TTL interface compatibility at 3.3 V
I Latch-up performance meets requirements of JESD 78 Class I
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Control inputs accepts voltages up to 5 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
74LVC1G53
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC1G53DP −40 °C to +125 °C
74LVC1G53DC −40 °C to +125 °C
74LVC1G53GT −40 °C to +125 °C
74LVC1G53GD −40 °C to +125 °C
74LVC1G53GM −40 °C to +125 °C
TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
SOT765-1
SOT833-1
SOT996-2
SOT902-1
VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
XSON8
plastic extremely thin small outline package; no leads;
8 terminals; body 1 × 1.95 × 0.5 mm
XSON8U plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 × 2 × 0.5 mm
XQFN8U plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm
4. Marking
Table 2.
Marking codes
Type number
74LVC1G53DC
74LVC1G53DP
74LVC1G53GT
74LVC1G53GD
74LVC1G53GM
Marking code
V53
V53
V53
V53
V53
5. Functional diagram
Y1
Y0
S
Z
E
001aah795
Fig 1. Logic symbol
74LVC1G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 June 2008
2 of 23
74LVC1G53
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
Y0
S
Z
Y1
E
001aad387
Fig 2. Logic diagram
6. Pinning information
6.1 Pinning
74LVC1G53
Z
E
1
2
3
4
8
7
6
5
V
CC
Y0
Y1
S
74LVC1G53
GND
GND
1
2
3
4
8
7
6
5
Z
E
V
CC
Y0
Y1
S
GND
GND
001aad389
Transparent top view
001aad388
Fig 3. Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
Fig 4. Pin configuration SOT833-1 (XSON8)
74LVC1G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 June 2008
3 of 23
74LVC1G53
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
74LVC1G53
terminal 1
index area
Y0
1
7
6
5
Z
74LVC1G53
Z
E
1
2
3
4
8
7
6
5
V
CC
Y1
S
2
3
E
Y0
Y1
S
GND
GND
GND
001aag459
001aai249
Transparent top view
Transparent top view
Fig 5. Pin configuration SOT996-2 (XSON8U)
Fig 6. Pin configuration SOT902-1 (XQFN8U)
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SOT505-2, SOT765-1, SOT996-2 and SOT902-1
SOT833-1
Z
1
2
3
4
5
6
7
8
7
6
5
4
3
2
1
8
common output or input
enable input (active LOW)
ground (0 V)
E
GND
GND
S
ground (0 V)
select input
Y1
Y0
VCC
independent input or output
independent input or output
supply voltage
7. Functional description
Table 4.
Function table[1]
Input
Channel on
S
L
E
L
Y0 to Z or Z to Y0
Y1 to Z or Z to Y1
Z (switch off)
H
X
L
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
74LVC1G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 June 2008
4 of 23
74LVC1G53
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
−0.5
−0.5
−50
-
Max
+6.5
+6.5
-
Unit
V
supply voltage
[1]
[2]
input voltage
V
IIK
input clamping current
switch clamping current
switch voltage
VI < −0.5 V or VI > VCC + 0.5 V
VI < −0.5 V or VI > VCC + 0.5 V
enable and disable mode
mA
mA
V
ISK
±50
VCC + 0.5
±50
100
-
VSW
ISW
−0.5
-
switch current
VSW > −0.5 V or VSW < VCC + 0.5 V
mA
mA
mA
°C
ICC
supply current
-
IGND
Tstg
Ptot
ground current
−100
−65
-
storage temperature
total power dissipation
+150
250
[3]
Tamb = −40 °C to +125 °C
mW
[1] The minimum input voltage rating may be exceeded if the input current rating is observed.
[2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed.
[3] For TSSOP8 packages: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 packages: above 110 °C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
VCC
Operating conditions
Parameter
Conditions
Min
Max
5.5
Unit
supply voltage
1.65
V
VI
input voltage
0
5.5
V
[1]
VSW
switch voltage
enable and disable mode
0
VCC
+125
20
V
Tamb
ambient temperature
input transition rise and fall rate
−40
°C
ns/V
ns/V
[2]
[2]
∆t/∆V
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
-
-
10
[1] To avoid sinking GND current from terminal Z when switch current flows in terminal Yn, the voltage drop across the bidirectional switch
must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current will flow from terminal Yn. In this case, there is no limit
for the voltage drop across the switch.
[2] Applies to control signal levels.
74LVC1G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 June 2008
5 of 23
74LVC1G53
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter
Conditions
Tamb = −40 °C to +85 °C
Tamb = −40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
VIH
HIGH-level
input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
-
-
0.65 × VCC
-
V
V
V
V
V
V
V
V
µA
1.7
-
-
1.7
-
2.0
-
-
2.0
-
-
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.7 × VCC
-
-
0.35 × VCC
0.7
0.7 × VCC
VIL
LOW-level
input voltage
-
-
-
-
-
-
-
-
-
-
-
0.35 × VCC
0.7
-
-
-
0.8
0.8
VCC = 4.5 V to 5.5 V
0.3 × VCC
±2
0.3 × VCC
±10
[2]
[2]
[2]
[2]
II
input leakage pin S and pin E;
current
±0.1
VI = 5.5 V or GND;
CC = 0 V to 5.5 V
V
IS(OFF)
IS(ON)
ICC
OFF-state
leakage
current
VI = VIH or VIL;
CC = 5.5 V;
-
-
-
±0.1
±0.1
0.1
±5
±5
10
-
-
-
±20
±20
40
µA
µA
µA
V
see Figure 7
ON-state
leakage
current
VI = VIH or VIL;
VCC = 5.5 V;
see Figure 8
supply current VI = 5.5 V or GND;
SW = GND or VCC
IO = 0 A;
CC = 1.65 V to 5.5 V
V
;
V
[2]
∆ICC
additional
pin S and pin E;
-
5
500
-
5000
µA
supply current VI = VCC − 0.6 V;
IO = 0 A;
V
V
SW = GND or VCC
CC = 5.5 V
;
CI
input
capacitance
-
-
-
2.5
6.0
18
-
-
-
-
-
-
-
-
-
pF
pF
pF
CS(OFF) OFF-state
capacitance
CS(ON)
ON-state
capacitance
[1] Typical values are measured at Tamb = 25 °C.
[2] These typical values are measured at VCC = 3.3 V.
74LVC1G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 June 2008
6 of 23
74LVC1G53
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
10.1 Test circuits
V
CC
switch
S
E
1
2
V
V
IL
IH
IH
V
V
IH
S
Z
Y0
Y1
1
2
V
or V
V
IL
IH
switch
I
S
E
GND
IH
V
V
O
I
001aad390
VI = VCC or GND; VO = GND or VCC
.
Fig 7. Test circuit for measuring OFF-state leakage current
V
CC
switch
S
E
1
2
V
V
V
IL
IL
IL
V
IH
S
Z
Y0
Y1
1
2
V
or V
IH
IL
switch
I
S
E
GND
V
IL
V
V
O
I
001aad391
VI = VCC or GND and VO = open circuit.
Fig 8. Test circuit for measuring ON-state leakage current
10.2 ON resistance
Table 8.
ON resistance
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 10 to Figure 15.
Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ[1] Max
Min
Max
RON(peak) ON resistance (peak) VI = GND to VCC; see Figure 9
ISW = 4 mA;
-
34.0
130
-
195
Ω
V
CC = 1.65 V to 1.95 V
ISW = 8 mA; VCC = 2.3 V to 2.7 V
ISW = 12 mA; VCC = 2.7 V
-
-
-
-
12.0
10.4
7.8
30
25
20
15
-
-
-
-
45
38
30
23
Ω
Ω
Ω
Ω
ISW = 24 mA; VCC = 3 V to 3.6 V
ISW = 32 mA; VCC = 4.5 V to 5.5 V
6.2
74LVC1G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 June 2008
7 of 23
74LVC1G53
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
Table 8.
ON resistance …continued
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 10 to Figure 15.
Symbol Parameter
Conditions
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ[1] Max
Min
Max
RON(rail)
ON resistance (rail)
VI = GND; see Figure 9
ISW = 4 mA;
-
8.2
18
-
27
Ω
V
CC = 1.65 V to 1.95 V
ISW = 8 mA; VCC = 2.3 V to 2.7 V
ISW = 12 mA; VCC = 2.7 V
ISW = 24 mA; VCC = 3 V to 3.6 V
ISW = 32 mA; VCC = 4.5 V to 5.5 V
VI = VCC; see Figure 9
-
-
-
-
7.1
6.9
6.5
5.8
16
14
12
10
-
-
-
-
24
21
18
15
Ω
Ω
Ω
Ω
ISW = 4 mA;
-
10.4
30
-
45
Ω
V
CC = 1.65 V to 1.95 V
ISW = 8 mA; VCC = 2.3 V to 2.7 V
ISW = 12 mA; VCC = 2.7 V
ISW = 24 mA; VCC = 3 V to 3.6 V
ISW = 32 mA; VCC = 4.5 V to 5.5 V
VI = GND to VCC
-
-
-
-
7.6
7.0
6.1
4.9
20
18
15
10
-
-
-
-
30
27
23
15
Ω
Ω
Ω
Ω
[2]
RON(flat)
ON resistance
(flatness)
ISW = 4 mA;
-
26.0
-
-
-
Ω
V
CC = 1.65 V to 1.95 V
ISW = 8 mA; VCC = 2.3 V to 2.7 V
ISW = 12 mA; VCC = 2.7 V
-
-
-
-
5.0
3.5
2.0
1.5
-
-
-
-
-
-
-
-
-
-
-
-
Ω
Ω
Ω
Ω
ISW = 24 mA; VCC = 3 V to 3.6 V
ISW = 32 mA; VCC = 4.5 V to 5.5 V
[1] Typical values are measured at Tamb = 25 °C and nominal VCC
.
[2] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
10.3 ON resistance test circuit and graphs
V
SW
switch
S
E
V
CC
1
2
V
V
IL
IL
IL
V
IH
V
S
Z
Y0
Y1
1
2
V
or V
IH
IL
switch
E
GND
V
IL
I
V
SW
I
001aad392
RON = VSW / ISW
.
Fig 9. Test circuit for measuring ON resistance
74LVC1G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 June 2008
8 of 23
74LVC1G53
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
mna673
40
R
ON
(Ω)
30
(1)
20
10
0
(2)
(3)
(4)
(5)
0
1
2
3
4
5
V (V)
I
(1) VCC = 1.8 V.
(2) VCC = 2.5 V.
(3) VCC = 2.7 V.
(4) VCC = 3.3 V.
(5) VCC = 5.0 V.
Fig 10. Typical ON resistance as a function of input voltage; Tamb = 25 °C
001aaa712
001aaa708
55
15
R
ON
R
ON
(Ω)
(Ω)
45
13
35
25
15
5
11
9
(4)
(3)
(2)
(1)
(1)
(2)
(3)
(4)
7
5
0
0.4
0.8
1.2
1.6
2.0
0
0.5
1.0
1.5
2.0
2.5
V (V)
I
V (V)
I
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
Fig 11. ON resistance as a function of input voltage;
CC = 1.8 V
Fig 12. ON resistance as a function of input voltage;
VCC = 2.5 V
V
74LVC1G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 June 2008
9 of 23
74LVC1G53
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
001aaa709
001aaa710
13
10
R
(Ω)
ON
R
ON
(Ω)
11
8
6
4
(1)
(1)
(2)
9
7
5
(2)
(3)
(3)
(4)
(4)
0
0.5
1.0
1.5
2.0
2.5 3.0
V (V)
I
0
1
2
3
4
V (V)
I
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
Fig 13. ON resistance as a function of input voltage;
CC = 2.7 V
Fig 14. ON resistance as a function of input voltage;
VCC = 3.3 V
V
001aaa711
7
6
5
4
3
R
ON
(Ω)
(1)
(2)
(3)
(4)
0
1
2
3
4
5
V (V)
I
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
Fig 15. ON resistance as a function of input voltage; VCC = 5.0 V
74LVC1G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 June 2008
10 of 23
74LVC1G53
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
11. Dynamic characteristics
Table 9.
Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 18.
Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
[2][3]
tpd
propagation delay Z to Yn or Yn to Z; see Figure 16
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
-
-
-
-
-
-
-
-
-
-
2
-
-
-
-
-
2.5
1.5
ns
ns
ns
ns
ns
1.2
1.0
0.8
0.6
VCC = 2.7 V
1.25
1.0
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.8
[4]
ten
enable time
S to Z or Yn; see Figure 17
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.6
1.9
1.9
1.8
1.3
6.7
4.1
4.0
3.4
2.6
10.3
6.4
5.5
5.0
3.8
2.6
1.9
1.8
1.8
1.3
12.9
8.0
7.0
6.3
4.8
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
E to Z or Yn; see Figure 17
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[4]
1.9
1.4
1.1
1.2
1.0
4.0
2.5
2.6
2.2
1.7
7.3
4.4
3.9
3.8
2.6
1.9
1.4
1.1
1.2
1.0
9.2
5.5
4.9
4.8
3.3
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
S to Z or Yn; see Figure 17
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[5]
tdis
disable time
2.1
1.4
1.4
1.1
1.0
6.8
3.7
4.9
4.0
2.9
10.0
6.1
6.2
5.4
3.8
2.1
1.4
1.4
1.1
1.0
12.5
7.7
7.8
6.8
4.8
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
E to Z or Yn; see Figure 17
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[5]
2.3
1.2
1.4
2.0
1.3
5.6
3.2
4.0
3.7
2.9
8.6
4.8
5.2
5.0
3.8
2.3
1.2
1.4
2.0
1.3
11.0
6.0
6.5
6.3
4.8
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
[1] Typical values are measured at Tamb = 25 °C and nominal VCC
.
[2] tpd is the same as tPLH and tPHL
.
[3] Propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when
driven by an ideal voltage source (zero output impedance).
[4] ten is the same as tPZH and tPZL
.
[5] tdis is the same as tPLZ and tPHZ
.
74LVC1G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 June 2008
11 of 23
74LVC1G53
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
11.1 Waveforms and test circuits
V
I
Yn or Z
input
V
V
M
M
GND
t
t
PHL
PLH
V
OH
Z or Yn
output
V
V
M
M
V
OL
001aac361
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 16. Input (Yn or Z) to output (Z or Yn) propagation delays
V
I
S, E input
V
M
t
GND
t
PLZ
PZL
V
CC
output
Z, Yn LOW to OFF
V
M
OFF to LOW
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH to OFF
OFF to HIGH
Z, Yn
V
M
GND
switch
enabled
switch
disabled
switch
enabled
001aad393
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 17. Enable and disable times
Table 10. Measurement points
Supply voltage
VCC
Input
Output
VM
VM
VX
VY
1.65 V to 2.7 V
2.7 V to 5.5 V
0.5VCC
0.5VCC
0.5VCC
0.5VCC
VOL + 0.15 V
VOL + 0.3 V
V
OH − 0.15 V
VOH − 0.3 V
74LVC1G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 June 2008
12 of 23
74LVC1G53
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
mna616
Test data is given in Table 11.
Definitions test circuit:
RT = Termination resistance (should be equal to output impedance Zo of the pulse generator).
CL = Load capacitance (including jig and probe capacitance).
RL = Load resistance.
VEXT = External voltage for measuring switching times.
Fig 18. Load circuit for switching times
Table 11. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPZH, tPHZ
GND
tPZL, tPLZ
2VCC
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
VCC
VCC
VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
500 Ω
open
GND
2VCC
open
GND
2VCC
3 V to 3.6 V
4.5 V to 5.5 V
open
GND
2VCC
open
GND
2VCC
11.2 Additional dynamic characteristics
Table 12. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
THD
total harmonic distortion
fi = 600 Hz to 20 kHz; RL = 600 Ω;
CL = 50 pF; VI = 0.5 V (p-p); see Figure 19
VCC = 1.65 V
-
-
-
-
0.260
0.078
0.078
0.078
-
-
-
-
%
%
%
%
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
f(−3dB)
−3 dB frequency response RL = 50 Ω; CL = 5 pF; see Figure 20
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
-
-
-
-
200
300
300
300
-
-
-
-
MHz
MHz
MHz
MHz
74LVC1G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 June 2008
13 of 23
74LVC1G53
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
Table 12. Additional dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
αiso
isolation (OFF-state)
RL = 50 Ω; CL = 5 pF; fi = 10 MHz;
see Figure 21
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
-
-
-
-
−42
−42
−40
−40
-
-
-
-
dB
dB
dB
dB
Qinj
charge injection
CL = 0.1 nF; Vgen = 0 V; Rgen = 0 Ω;
fi = 1 MHz; RL = 1 MΩ; see Figure 22
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 5.5 V
-
-
-
-
-
3.3
4.1
5.0
6.4
7.5
-
-
-
-
-
pC
pC
pC
pC
pC
11.3 Test circuits
V
0.5V
CC
CC
switch
S
E
1
2
V
V
V
IL
IL
IL
R
L
V
IH
S
Z
Y0
Y1
1
2
10 µF
V
or V
IH
IL
switch
0.1 µF
E
V
IL
D
C
L
f
600 Ω
i
GND
001aad394
Fig 19. Test circuit for measuring total harmonic distortion
V
0.5V
CC
CC
switch
S
E
1
2
V
V
IL
IL
IL
R
L
V
V
IH
S
Z
Y0
Y1
1
2
V
or V
IH
IL
switch
0.1 µF
E
V
IL
dB
C
L
f
50 Ω
i
GND
001aad395
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads −3 dB.
Fig 20. Test circuit for measuring the frequency response when switch is in ON-state
74LVC1G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 June 2008
14 of 23
74LVC1G53
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
0.5V
0.5V
CC
CC
V
CC
switch
S
E
R
L
R
L
1
2
V
V
IH
IH
IH
V
V
IL
S
Z
Y0
Y1
1
2
V
or V
IH
IL
switch
0.1 µF
E
V
IH
dB
C
L
f
50 Ω
i
GND
001aad396
Adjust fi voltage to obtain 0 dBm level at input.
Fig 21. Test circuit for measuring isolation (OFF-state)
V
CC
S
Z
Y0
Y1
1
2
switch
E
R
gen
V
IL
G
V
V
R
L
C
L
I
O
V
gen
GND
001aad398
a. Test circuit
logic
input
(S) off
on
off
V
O
∆V
O
001aac478
b. Input and output pulse definitions
Qinj = ∆VO × CL.
∆VO = output voltage variation.
Rgen = generator resistance.
Vgen = generator voltage.
Fig 22. Test circuit for measuring charge injection
74LVC1G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 June 2008
15 of 23
74LVC1G53
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
12. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.65
0.25
0.5
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
Fig 23. Package outline SOT505-2 (TSSOP8)
74LVC1G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 June 2008
16 of 23
74LVC1G53
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
Fig 24. Package outline SOT765-1 (VSSOP8)
74LVC1G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 June 2008
17 of 23
74LVC1G53
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
b
1
2
3
4
4×
(2)
L
L
1
e
8
7
6
5
e
1
e
1
e
1
8×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
1
L
L
1
max max
0.25
0.17
2.0
1.9
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
- - -
07-11-14
07-12-07
SOT833-1
- - -
MO-252
Fig 25. Package outline SOT833-1 (XSON8)
74LVC1G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 June 2008
18 of 23
74LVC1G53
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
SOT996-2
D
B
A
E
A
A
1
detail X
terminal 1
index area
e
1
C
M
M
v
C A
C
B
b
e
L
1
y
y
w
C
1
1
4
L
2
L
8
5
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
b
D
E
e
e
1
L
L
L
v
w
y
y
1
1
2
max
0.05 0.35
0.00 0.15
2.1
1.9
3.1
2.9
0.5
0.3
0.15
0.05
0.6
0.4
mm
0.5
0.5
1.5
0.1
0.05 0.05
0.1
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
- - -
JEDEC
JEITA
07-12-18
07-12-21
SOT996-2
- - -
Fig 26. Package outline SOT996-2 (XSON8U)
74LVC1G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 June 2008
19 of 23
74LVC1G53
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
XQFN8U: plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm
SOT902-1
D
B
A
terminal 1
index area
E
A
A
1
detail X
e
L
1
e
C
y
C
1
y
L
M
M
v
C A
C
B
4
w
5
6
7
3
2
metal area
not for soldering
e
1
b
e
1
1
terminal 1
index area
8
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
b
D
E
e
e
1
L
L
v
w
y
y
1
1
max
0.05 0.25 1.65 1.65
0.00 0.15 1.55 1.55
0.35 0.15
0.25 0.05
mm
0.5
0.55
0.5
0.1
0.05 0.05 0.05
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
MO-255
JEITA
05-11-25
07-11-14
SOT902-1
- - -
- - -
Fig 27. Package outline SOT902-1 (XQFN8U)
74LVC1G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 June 2008
20 of 23
74LVC1G53
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
13. Abbreviations
Table 13. Abbreviations
Acronym
CMOS
TTL
Description
Complementary Metal-Oxide Semiconductor
Transistor-Transistor Logic
Human Body Model
HBM
ESD
ElectroStatic Discharge
Machine Model
MM
CDM
DUT
Charged Device Model
Device Under Test
14. Revision history
Table 14. Revision history
Document ID
74LVC1G53_5
Modifications:
74LVC1G53_4
74LVC1G53_3
74LVC1G53_2
74LVC1G53_1
Release date
20080611
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LVC1G53_4
• Added type number 74LVC1G53GD (XSON8U / SOT996-2 package)
20080303
20070829
20060410
20060110
Product data sheet
Product data sheet
Product data sheet
Product data sheet
-
-
-
-
74LVC1G53_3
74LVC1G53_2
74LVC1G53_1
-
74LVC1G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 June 2008
21 of 23
74LVC1G53
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC1G53_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 June 2008
22 of 23
74LVC1G53
NXP Semiconductors
2-channel analog multiplexer/demultiplexer
17. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
8
9
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
10
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 7
ON resistance test circuit and graphs. . . . . . . . 8
10.1
10.2
10.3
11
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
Waveforms and test circuits . . . . . . . . . . . . . . 12
Additional dynamic characteristics . . . . . . . . . 13
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
11.1
11.2
11.3
12
13
14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 22
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 22
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 June 2008
Document identifier: 74LVC1G53_5
相关型号：
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