74LVC1G57 [NXP]
Low-power configurable multiple function gate; 低功耗可配置多功能门
| 型号： | 74LVC1G57 |
| 厂家： | 
NXP |
| 描述： | Low-power configurable multiple function gate |
| 文件： | 总18页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC1G57
Low-power configurable multiple function gate
Rev. 01 — 6 September 2004
Product data sheet
1. General description
The 74LVC1G57 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry
disables the output, preventing the damaging backflow current through the device when it
is powered down.
The 74LVC1G57 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
NOR, XNOR, inverter and buffer. All inputs can be connected to VCC or GND.
All inputs (A, B and C) have Schmitt-trigger action. They are capable of transforming
slowly changing input signals into sharply defined, jitter-free output signals.
2. Features
■ Wide supply voltage range from 1.65 V to 5.5 V
■ 5 V tolerant input/output for interfacing with 5 V logic
■ High noise immunity
■ Complies with JEDEC standard:
◆ JESD8-7 (1.65 V to 1.95 V)
◆ JESD8-5 (2.3 V to 2.7 V)
◆ JESD8B/JESD36 (2.7 V to 3.6 V).
■ ±24 mA output drive (VCC = 3.0 V)
■ ESD protection:
◆ HBM EIA/JESD22-A114-B exceeds 2000 V
◆ MM EIA/JESD22-A115-A exceeds 200 V.
■ CMOS low power consumption
■ Latch-up performance exceeds 250 mA
■ Direct interface with TTL levels
■ Inputs accept voltages up to 5 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and −40 °C to +125 °C.
74LVC1G57
Philips Semiconductors
Low-power configurable multiple function gate
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
Symbol Parameter
Conditions
CL = 30 pF; RL = 1 kΩ;
CC = 1.8 V
CL = 30 pF; RL = 500 Ω;
CC = 2.5 V
CL = 50 pF; RL = 500 Ω;
CC = 2.7 V
CL = 50 pF; RL = 500 Ω;
CC = 3.3 V
CL = 50 pF; RL = 500 Ω;
CC = 5.0 V;
Min
Typ
Max Unit
tPHL, tPLH propagation delay
input A, B and
-
6.0
-
-
-
-
-
ns
ns
ns
ns
ns
V
C to output Y
-
-
-
-
3.5
4.2
3.8
3.0
V
V
V
V
CI
input capacitance
-
-
2.5
22
-
-
pF
pF
[1] [2]
CPD
power dissipation
VCC = 3.3 V
capacitance per buffer
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
[2] The condition is VI = GND to VCC
.
4. Ordering information
Table 2:
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LVC1G57GW
74LVC1G57GV
74LVC1G57GM
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
-
plastic surface mounted package; 6 leads
plastic surface mounted package; 6 leads
SOT363
SOT457
SOT886
-
XSON6
plastic extremely thin small outline package;
no leads; 6 terminals; body 1 × 1.45 × 0.5 mm
5. Marking
Table 3:
Marking
Type number
74LVC1G57GW
74LVC1G57GV
74LVC1G57GM
Marking code
YC
V57
YC
9397 750 13722
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 6 September 2004
2 of 18
74LVC1G57
Philips Semiconductors
Low-power configurable multiple function gate
6. Functional diagram
3
1
6
A
B
C
4
Y
001aab583
Fig 1. Logic symbol.
7. Pinning information
7.1 Pinning
B
GND
A
1
2
3
6
5
4
C
1
2
3
6
B
C
57
V
Y
CC
5
4
GND
A
57
V
CC
Y
001aab592
001aab591
Transparent top view
Fig 2. Pin configuration SOT363 and
SOT457.
Fig 3. Pin configuration SOT886.
7.2 Pin description
Table 4:
Pin description
Symbol
Pin
1
Description
data input B
ground (0 V)
data input A
data output Y
supply voltage
data input C
B
GND
A
2
3
Y
4
VCC
C
5
6
9397 750 13722
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 6 September 2004
3 of 18
74LVC1G57
Philips Semiconductors
Low-power configurable multiple function gate
8. Functional description
8.1 Function table
Table 5:
Function table[1]
Input
Output
C
L
B
L
A
L
Y
H
L
L
L
H
L
L
H
H
L
H
L
L
H
L
H
H
H
H
L
L
H
L
L
H
H
H
H
H
[1] H = HIGH voltage level;
L = LOW voltage level.
8.2 Logic configurations
Table 6:
Function selection table
Logic function
Figure
2-input AND
see Figure 4
see Figure 7
see Figure 5 and 6
see Figure 5 and 6
see Figure 7
see Figure 4
see Figure 8
see Figure 9
see Figure 10
2-input AND with both inputs inverted
2-input NAND with inverted input
2-input OR with inverted input
2-input NOR
2-input NOR with both inputs inverted
2-input XNOR
Inverter
Buffer
V
CC
V
CC
B
C
B
Y
C
Y
B
1
2
3
6
5
4
C
Y
B
1
2
3
6
5
4
C
Y
B
C
B
Y
C
Y
001aab585
001aab584
Fig 4. 2-input AND gate or 2-input NOR
gate with both inputs inverted.
Fig 5. 2-input NAND gate with input B
inverted or 2-input OR gate with
inverted C input.
9397 750 13722
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 6 September 2004
4 of 18
74LVC1G57
Philips Semiconductors
Low-power configurable multiple function gate
V
CC
V
CC
A
C
Y
Y
A
C
1
2
3
6
5
4
C
Y
Y
Y
1
2
3
6
5
4
C
Y
A
C
A
A
C
A
001aab587
001aab586
Fig 6. 2-input NAND gate with input C
inverted or 2-input OR gate with
inverted A input.
Fig 7. 2-input NOR gate or 2-input AND
gate with both inputs inverted.
V
CC
V
CC
B
1
2
3
6
5
4
C
Y
1
2
3
6
5
4
B
C
Y
A
Y
A
Y
001aab588
001aab589
Fig 8. 2-input XNOR gate.
Fig 9. Inverter.
V
CC
B
1
2
3
6
5
4
B
Y
Y
001aab590
Fig 10. Buffer.
9. Limiting values
Table 7:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min
−0.5 +6.5
−50
−0.5 +6.5
±50
Max
Unit
V
VCC
IIK
supply voltage
input diode current
input voltage
VI < 0 V
-
mA
V
[1]
VI
IOK
VO
output diode current
output voltage
VO > VCC or VO < 0 V
active mode
-
mA
V
[1] [2]
[1] [2]
−0.5 +6.5
−0.5 +6.5
Power-down mode
VO = 0 V to VCC
V
IO
output source or sink
current
-
±50
mA
9397 750 13722
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 6 September 2004
5 of 18
74LVC1G57
Philips Semiconductors
Low-power configurable multiple function gate
Table 7:
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
±100
+150
300
Unit
mA
°C
ICC, IGND VCC or GND current
-
Tstg
Ptot
storage temperature
power dissipation
−65
Tamb = −40 °C to +125 °C
-
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
10. Recommended operating conditions
Table 8:
Recommended operating conditions
Symbol Parameter
Conditions
Min
1.65
0
Typ Max Unit
VCC
VI
supply voltage
input voltage
output voltage
-
-
-
-
5.5
5.5
VCC
5.5
V
V
V
V
VO
active mode
0
VCC = 0 V; Power-down
mode
0
Tamb
operating ambient
temperature
−40
-
+125 °C
11. Static characteristics
Table 9:
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C[1]
VOL
LOW-level output voltage VI = VCC or GND
IO = 100 µA; VCC = 1.65 V to 5.5 V
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
V
V
V
V
V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
0.45
0.3
0.4
0.55
0.55
VOH
HIGH-level output voltage VI = VCC or GND
IO = −100 µA; VCC = 1.65 V to 5.5 V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
V
CC − 0.1 -
-
V
1.2
1.9
2.2
2.3
3.8
-
-
-
V
-
-
V
IO = −12 mA; VCC = 2.7 V
IO = −24 mA; VCC = 3.0 V
IO = −32 mA; VCC = 4.5 V
VI = 5.5 V or GND; VCC = 3.6 V
-
-
V
-
-
V
-
-
V
ILI
input leakage current
±0.1
±5
µA
9397 750 13722
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 6 September 2004
6 of 18
74LVC1G57
Philips Semiconductors
Low-power configurable multiple function gate
Table 9:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Ioff
power OFF leakage
current
VI or VO = 5.5 V; VCC = 0 V
-
±0.1
±10
µA
ICC
∆ICC
CI
quiescent supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
-
-
-
0.1
5
10
500
-
µA
µA
pF
V
additional quiescent
supply current per pin
VI = VCC − 0.6 V; IO = 0 A;
CC = 2.3 V to 5.5 V
V
input capacitance
2.5
Tamb = −40 °C to +125 °C
VOL LOW-level output voltage VI = VCC or GND
IO = 100 µA; VCC = 1.65 V to 5.5 V
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.7
0.45
0.6
0.8
0.8
V
V
V
V
V
V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VOH
HIGH-level output voltage VI = VCC or GND
IO = −100 µA; VCC = 1.65 V to 5.5 V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
V
CC − 0.1 -
-
V
0.95
1.7
1.9
2.0
3.4
-
-
-
-
-
-
-
-
-
V
-
V
IO = −12 mA; VCC = 2.7 V
IO = −24 mA; VCC = 3.0 V
IO = −32 mA; VCC = 4.5 V
VI = 5.5 V or GND; VCC = 3.6 V
VI or VO = 5.5 V; VCC = 0 V
-
V
-
V
-
V
ILI
input leakage current
±100
±200
µA
µA
Ioff
power OFF leakage
current
-
ICC
quiescent supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
-
-
-
-
200
µA
µA
V
∆ICC
additional quiescent
supply current per pin
VI = VCC − 0.6 V; IO = 0 A;
CC = 2.3 V to 5.5 V
5000
V
[1] Typical values are measured at maximum VCC and Tamb = 25 °C.
9397 750 13722
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 6 September 2004
7 of 18
74LVC1G57
Philips Semiconductors
Low-power configurable multiple function gate
12. Dynamic characteristics
Table 10: Dynamic characteristics
GND = 0 V.
Symbol
Tamb = −40 °C to +85 °C[1]
tPHL, tPLH propagation delay A, B, C to Y
Parameter
Conditions
Min
Typ
Max
Unit
see Figure 11 and 12
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.0
0.5
0.5
0.5
0.5
-
6.0
3.5
4.2
3.8
3.0
22
14.4
8.3
8.5
6.3
5.1
-
ns
ns
ns
ns
ns
pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 3.3 V
[2] [3]
CPD
power dissipation capacitance per
buffer
Tamb = −40 °C to +125 °C
tPHL, tPLH propagation delay A, B, C to Y
see Figure 11 and 12
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.0
0.5
0.5
0.5
0.5
-
-
-
-
-
18
ns
ns
ns
ns
ns
10.4
10.6
7.9
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
6.4
[1] Typical values are measured at nominal VCC and Tamb = 25 °C.
[2] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
[3] The condition is VI = GND to VCC
.
9397 750 13722
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 6 September 2004
8 of 18
74LVC1G57
Philips Semiconductors
Low-power configurable multiple function gate
13. Waveforms
V
I
A, B, C input
GND
V
M
t
t
t
PHL
PLH
V
OH
V
V
Y output
M
V
OL
t
PLH
PHL
V
OH
Y output
M
V
OL
001aab593
Measurement points are given in Table 11.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 11. Input A, B and C to output Y propagation delay times.
Table 11: Measurement points
Supply voltage
VCC
Input
Output
VM
VM
VI
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5 × VCC
0.5 × VCC
1.5 V
VCC
VCC
2.7 V
2.7 V
VCC
0.5 × VCC
0.5 × VCC
1.5 V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
1.5 V
0.5 × VCC
0.5 × VCC
9397 750 13722
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 6 September 2004
9 of 18
74LVC1G57
Philips Semiconductors
Low-power configurable multiple function gate
V
EXT
V
CC
R
L
V
I
V
O
PULSE
GENERATOR
D.U.T.
C
L
R
L
R
T
mna616
Measurement points are given in Table 12.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
VEXT = Test voltage for switching times.
Fig 12. Load circuitry for switching times.
Table 12: Measurement points
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr = tf
RL
tPLH, tPHL tPZH, tPHZ tPZL, tPLZ
1.65 V to 1.95 V
2.3 to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
open
open
open
open
open
GND
GND
GND
GND
GND
2 × VCC
2 × VCC
6 V
500 Ω
500 Ω
500 Ω
500 Ω
3.0 V to 3.6 V
4.5 V to 5.5 V
6 V
2 × VCC
14. Transfer characteristics
Table 13: Transfer characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Tamb = −40 °C to +85 °C[1]
VT+ positive-going threshold
Parameter
Conditions
Min
Typ
Max
Unit
see Figure 13, 14, 15 and 16
VCC = 1.8 V
voltage
0.70
1.11
1.50
2.16
2.61
1.02
1.42
1.79
2.52
2.99
1.20
1.60
2.00
2.74
3.33
V
V
V
V
V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
VT−
negative-going threshold
voltage
see Figure 13, 14, 15 and 16
VCC = 1.8 V
0.30
0.58
0.80
1.21
1.45
0.53
0.77
1.04
1.55
1.86
0.72
1.00
1.30
1.90
2.29
V
V
V
V
V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
9397 750 13722
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 6 September 2004
10 of 18
74LVC1G57
Philips Semiconductors
Low-power configurable multiple function gate
Table 13: Transfer characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VH
hysteresis voltage (VT+ − VT−) see Figure 13, 14, 15 and 16
VCC = 1.8 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
0.30
0.40
0.50
0.71
0.71
0.48
0.64
0.75
0.97
1.13
0.62
0.80
1.00
1.20
1.40
V
V
V
V
V
Tamb = −40 °C to +125 °C
VT+
VT−
VH
positive-going threshold
voltage
see Figure 13, 14, 15 and 16
VCC = 1.8 V
0.67
1.08
1.47
2.13
2.58
-
-
-
-
-
1.20
1.60
2.00
2.74
3.33
V
V
V
V
V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
negative-going threshold
voltage
see Figure 13, 14, 15 and 16
VCC = 1.8 V
0.30
0.58
0.80
1.21
1.45
-
-
-
-
-
0.75
1.03
1.33
1.93
2.32
V
V
V
V
V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
hysteresis voltage (VT+ − VT−) see Figure 13, 14, 15 and 16
VCC = 1.8 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
0.23
0.34
0.44
0.65
0.65
-
-
-
-
-
0.62
0.80
1.00
1.20
1.40
V
V
V
V
V
[1] Typical values are measured at Tamb = 25 °C.
15. Waveforms transfer characteristics
V
T+
V
O
V
V
H
I
V
T−
V
O
mna208
V
I
V
H
V
V
T+
T−
VT+ and VT− limits are at 70 % and
20 %.
mna207
Fig 13. Transfer characteristic.
Fig 14. Definition of VT+, VT− and VH.
9397 750 13722
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 6 September 2004
11 of 18
74LVC1G57
Philips Semiconductors
Low-power configurable multiple function gate
V
T+
V
O
V
I
V
H
V
T−
V
O
V
I
mnb155
V
H
V
V
T+
T−
VT+ and VT− limits are at 70 % and
20 %.
mnb154
Fig 15. Transfer characteristic.
Fig 16. Definition of VT+, VT− and VH.
001aab594
16
I
CC
(mA)
12
8
4
0
0
1
2
3
V (V)
I
Fig 17. Typical 74LVC1G57 transfer characteristic; VCC = 3.0 V.
9397 750 13722
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 6 September 2004
12 of 18
74LVC1G57
Philips Semiconductors
Low-power configurable multiple function gate
16. Package outline
Plastic surface mounted package; 6 leads
SOT363
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
1
2
3
c
e
1
b
p
L
p
w
M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
97-02-28
SOT363
SC-88
Fig 18. Package outline SOT363.
9397 750 13722
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 6 September 2004
13 of 18
74LVC1G57
Philips Semiconductors
Low-power configurable multiple function gate
Plastic surface mounted package; 6 leads
SOT457
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
c
1
2
3
L
p
e
b
p
w
M B
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A
b
c
D
E
e
H
L
Q
v
w
y
p
1
p
E
0.1
0.013
0.40
0.25
1.1
0.9
0.26
0.10
3.1
2.7
1.7
1.3
3.0
2.5
0.6
0.2
0.33
0.23
mm
0.95
0.2
0.2
0.1
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
SC-74
97-02-28
01-05-04
SOT457
Fig 19. Package outline SOT457.
9397 750 13722
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 6 September 2004
14 of 18
74LVC1G57
Philips Semiconductors
Low-power configurable multiple function gate
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L
1
e
6
5
4
e
1
e
1
6×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
1.5
1.4
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
04-07-15
04-07-22
SOT886
MO-252
Fig 20. Package outline SOT886 (XSON6).
9397 750 13722
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 6 September 2004
15 of 18
74LVC1G57
Philips Semiconductors
Low-power configurable multiple function gate
17. Revision history
Table 14: Revision history
Document ID
Release date Data sheet status
20040906 Product data sheet
Change notice Doc. number
9397 750 13722
Supersedes
74LVC1G57_1
-
-
9397 750 13722
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 6 September 2004
16 of 18
74LVC1G57
Philips Semiconductors
Low-power configurable multiple function gate
18. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
19. Definitions
20. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
21. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 13722
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 6 September 2004
17 of 18
74LVC1G57
Philips Semiconductors
Low-power configurable multiple function gate
22. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
8
8.1
8.2
Functional description . . . . . . . . . . . . . . . . . . . 4
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Logic configurations . . . . . . . . . . . . . . . . . . . . . 4
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Transfer characteristics. . . . . . . . . . . . . . . . . . 10
Waveforms transfer characteristics. . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Contact information . . . . . . . . . . . . . . . . . . . . 17
10
11
12
13
14
15
16
17
18
19
20
21
© Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 6 September 2004
Document number: 9397 750 13722
Published in The Netherlands
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