74LVC1G66GS/S500H [NXP]
Bus Driver, LVC/LCX/Z Series, 1-Func, 1-Bit, True Output, CMOS;
| 型号： | 74LVC1G66GS/S500H |
| 厂家： | 
NXP |
| 描述： | Bus Driver, LVC/LCX/Z Series, 1-Func, 1-Bit, True Output, CMOS 驱动 逻辑集成电路 |
| 文件： | 总25页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC1G66
Bilateral switch
Rev. 9 — 15 January 2015
Product data sheet
1. General description
The 74LVC1G66 provides one single pole, single-throw analog switch function. It has two
input/output terminals (Y and Z) and an active HIGH enable input pin (E). When E is LOW,
the analog switch is turned off.
Schmitt-trigger action at the enable input makes the circuit tolerant of slower input rise and
fall times across the entire VCC range from 1.65 V to 5.5 V.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
Very low ON resistance:
7.5 (typical) at VCC = 2.7 V
6.5 (typical) at VCC = 3.3 V
6 (typical) at VCC = 5 V
Switch current capability of 32 mA
High noise immunity
CMOS low power consumption
TTL interface compatibility at 3.3 V
Latch-up performance meets requirements of JESD78 Class I
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Enable input accepts voltages up to 5.5 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
Type number
Description
Version
74LVC1G66GW 40 C to +125 C
TSSOP5 plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
74LVC1G66GV
40 C to +125 C
SC-74A
XSON6
plastic surface-mounted package; 5 leads
SOT753
SOT886
74LVC1G66GM 40 C to +125 C
plastic extremely thin small outline package; no leads;
6 terminals; body 1 1.45 0.5 mm
74LVC1G66
NXP Semiconductors
Bilateral switch
Table 1.
Ordering information …continued
Type number
Package
Temperature range Name
Description
Version
74LVC1G66GF
40 C to +125 C
XSON6
XSON6
XSON6
plastic extremely thin small outline package; no leads;
6 terminals; body 1 1 0.5 mm
SOT891
SOT1115
SOT1202
74LVC1G66GN 40 C to +125 C
extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm
74LVC1G66GS
40 C to +125 C
extremely thin small outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74LVC1G66GW
74LVC1G66GV
74LVC1G66GM
74LVC1G66GF
74LVC1G66GN
74LVC1G66GS
VL
V66
VL
VL
VL
VL
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
ꢃ
(
ꢃ
ꢄ
ꢃ
ꢀꢁꢁꢁꢂ
=
<
;ꢃ
ꢀꢀꢁDDJꢂꢃꢄ
PQDꢀꢄꢅ
Fig 1. Logic symbol
Fig 2. IEC logic symbol
=
<
(
9
&&
ꢀꢀꢁDDPꢆꢇꢄ
Fig 3. Logic diagram
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
2 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
6. Pinning information
6.1 Pinning
ꢀꢁ/9&ꢂ*ꢃꢃ
ꢀꢁ/9&ꢂ*ꢃꢃ
<
=
ꢃ
ꢄ
ꢅ
ꢈ
ꢆ
ꢀ
9
&&
ꢀꢁ/9&ꢂ*ꢃꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
<
=
9
(
<
=
ꢃ
ꢄ
ꢅ
ꢈ
ꢆ
ꢀ
9
&&
&&
QꢇFꢇ
(
QꢇFꢇ
*1'
*1'
(
*1'
ꢀꢀꢁDDJꢂꢇꢃ
ꢀꢀꢁDDJꢂꢇꢇ
7UDQVSDUHQWꢁWRSꢁYLHZ
7UDQVSDUHQWꢁWRSꢁYLHZ
ꢀꢀꢁDDGꢅꢈꢂ
Fig 4. Pin configuration
SOT353-1 and SOT753
Fig 5. Pin configuration SOT886
Fig 6. Pin configuration SOT891
and SOT1115 and SOT1202
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SOT353-1, SOT753 SOT886, SOT891, SOT1115 and SOT1202
Y
1
2
3
4
-
1
2
3
4
5
6
independent input or output
independent output or input
ground (0 V)
Z
GND
E
enable input (active HIGH)
not connected
n.c.
VCC
5
supply voltage
7. Functional description
Table 4.
Function table[1]
Input E
Switch
L
OFF-state
ON-state
H
[1] H = HIGH voltage level; L = LOW voltage level
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
3 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
0.5
0.5
50
-
Max
+6.5
+6.5
-
Unit
V
supply voltage
[1]
[2]
input voltage
V
IIK
input clamping current
switch clamping current
switch voltage
VI < 0.5 V or VI > VCC + 0.5 V
VI < 0.5 V or VI > VCC + 0.5 V
enable and disable mode
mA
mA
V
ISK
50
VCC + 0.5
50
100
-
VSW
ISW
0.5
-
switch current
VSW > 0.5 V or VSW < VCC + 0.5 V
mA
mA
mA
C
ICC
supply current
-
IGND
Tstg
Ptot
ground current
100
65
-
storage temperature
total power dissipation
+150
250
[3]
Tamb = 40 C to +125 C
mW
[1] The minimum input voltage rating may be exceeded if the input current rating is observed.
[2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed.
[3] For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
5.5
Unit
V
supply voltage
input voltage
1.65
-
-
-
-
-
-
VI
0
5.5
V
[1]
VSW
switch voltage
ambient temperature
0
VCC
+125
20
V
Tamb
40
C
[2]
[2]
t/V
input transition rise and
fall rate
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
-
-
ns/V
ns/V
10
[1] To avoid sinking GND current from terminal Z when switch current flows in terminal Y, the voltage drop across the bidirectional switch
must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current will flow from terminal Y. In this case, there is no limit
for the voltage drop across the switch.
[2] Applies to control signal levels.
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
4 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
VIH
HIGH-level
input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.65VCC
-
-
0.65VCC
-
V
V
V
V
V
V
V
V
1.7
-
-
1.7
-
2.0
-
-
-
2.0
-
-
0.7VCC
-
0.7VCC
VIL
LOW-level
input voltage
-
-
-
-
-
-
0.35VCC
0.7
-
-
-
-
-
0.35VCC
0.7
-
-
-
0.8
0.8
0.3VCC
5
0.3VCC
[2]
[2]
II
input leakage pin E; VI = 5.5 V or GND;
current
0.1
100 A
VCC = 0 V to 5.5 V
IS(OFF)
OFF-state
leakage
current
VCC = 5.5 V; see Figure 7
-
-
-
-
0.1
0.1
0.1
5
5
5
-
-
-
-
200 A
[2]
[2]
[2]
IS(ON)
ON-state
leakage
current
VCC = 5.5 V; see Figure 8
200 A
ICC
supply
current
VI = 5.5 V or GND;
10
200
A
VSW = GND or VCC
;
VCC = 1.65 V to 5.5 V
ICC
additional
supply
pin E; VI = VCC 0.6 V;
VSW = GND or VCC; VCC = 5.5 V
500
5000 A
current
CI
input
capacitance
-
-
-
2.0
6.5
11
-
-
-
-
-
-
-
-
-
pF
pF
pF
CS(OFF) OFF-state
capacitance
CS(ON)
ON-state
capacitance
[1] All typical values are measured at Tamb = 25 C.
[2] These typical values are measured at VCC = 3.3 V.
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
5 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
10.1 Test circuits
9
9
&&
&&
(
=
(
=
9
9
,+
,/
<
<
,
,
6
6
*1'
*1'
9
,
9
2
9
,
9
2
ꢀꢀꢁDDPꢆꢃꢇ
ꢀꢀꢁDDPꢆꢇꢀ
VI = VCC or GND and VO = GND or VCC
.
VI = VCC or GND and VO = open circuit.
Fig 7. Test circuit for measuring OFF-state leakage
current
Fig 8. Test circuit for measuring ON-state leakage
current
10.2 ON resistance
Table 8.
ON resistance
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 10 to Figure 15.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
RON(peak) ON resistance (peak) VI = GND to VCC; see Figure 9
ISW = 4 mA;
-
34.0
130
-
195
VCC = 1.65 V to 1.95 V
I
SW = 8 mA; VCC = 2.3 V to 2.7 V
-
-
-
-
12.0
10.4
7.8
30
25
20
15
-
-
-
-
45
38
30
23
ISW = 12 mA; VCC = 2.7 V
ISW = 24 mA; VCC = 3.0 V to 3.6 V
ISW = 32 mA; VCC = 4.5 V to 5.5 V
VI = GND; see Figure 9
6.2
RON(rail) ON resistance (rail)
ISW = 4 mA;
-
8.2
18
-
27
VCC = 1.65 V to 1.95 V
ISW = 8 mA; VCC = 2.3 V to 2.7 V
ISW = 12 mA; VCC = 2.7 V
-
-
-
-
7.1
6.9
6.5
5.8
16
14
12
10
-
-
-
-
24
21
18
15
ISW = 24 mA; VCC = 3.0 V to 3.6 V
ISW = 32 mA; VCC = 4.5 V to 5.5 V
VI = VCC; see Figure 9
ISW = 4 mA;
-
10.4
30
-
45
VCC = 1.65 V to 1.95 V
ISW = 8 mA; VCC = 2.3 V to 2.7 V
ISW = 12 mA; VCC = 2.7 V
-
-
-
-
7.6
7.0
6.1
4.9
20
18
15
10
-
-
-
-
30
27
23
15
ISW = 24 mA; VCC = 3.0 V to 3.6 V
ISW = 32 mA; VCC = 4.5 V to 5.5 V
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
6 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
Table 8.
ON resistance …continued
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 10 to Figure 15.
Symbol Parameter
Conditions
40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
[2]
RON(flat) ON resistance
(flatness)
VI = GND to VCC
ISW = 4 mA;
-
26.0
-
-
-
VCC = 1.65 V to 1.95 V
ISW = 8 mA; VCC = 2.3 V to 2.7 V
ISW = 12 mA; VCC = 2.7 V
-
-
-
-
5.0
3.5
2.0
1.5
-
-
-
-
-
-
-
-
-
-
-
-
ISW = 24 mA; VCC = 3.0 V to 3.6 V
ISW = 32 mA; VCC = 4.5 V to 5.5 V
[1] Typical values are measured at Tamb = 25 C and nominal VCC
.
[2] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
10.3 ON resistance test circuit and graphs
PQDꢅꢄꢆ
ꢀꢋ
5
21ꢁ
ꢉȍꢊ
ꢅꢋ
9
6:
ꢉꢃꢊꢁ
ꢄꢋ
ꢃꢋ
ꢋ
9
&&
(
<
ꢉꢄꢊꢁ
ꢉꢅꢊꢁ
9
,+
=
ꢉꢀꢊꢁ
ꢉꢆꢊꢁ
ꢀ
*1'
9
,
,
6:
ꢋ
ꢃ
ꢄ
ꢅ
ꢆ
9 ꢁꢉ9ꢊ
,
ꢀꢀꢁDDPꢆꢇꢁ
RON = VSW/ISW
.
(1) VCC = 1.8 V.
(2) VCC = 2.5 V.
(3) VCC = 2.7 V.
(4)
VCC = 3.3 V.
(5) VCC = 5.0 V.
Fig 9. Test circuit for measuring ON resistance
Fig 10. Typical ON resistance as a function of input
voltage; Tamb = 25 C
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
7 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
ꢀꢀꢁDDDꢄꢁꢉ
ꢀꢀꢁDDDꢄꢀꢃ
ꢆꢆ
ꢃꢆ
5
5
21ꢁ
ꢉȍꢊ
21ꢁ
ꢉȍꢊ
ꢀꢆ
ꢃꢅ
ꢃꢃ
ꢍ
ꢅꢆ
ꢄꢆ
ꢃꢆ
ꢆ
ꢉꢀꢊꢁ
ꢉꢅꢊꢁ
ꢉꢄꢊꢁ
ꢉꢃꢊ
ꢉꢃꢊ
ꢉꢄꢊ
ꢉꢅꢊ
ꢉꢀꢊ
ꢎ
ꢆ
ꢋ
ꢋꢇꢀ
ꢋꢇꢌ
ꢃꢇꢄ
ꢃꢇꢈ
ꢄꢇꢋ
ꢋ
ꢋꢇꢆ
ꢃꢇꢋ
ꢃꢇꢆ
ꢄꢇꢋ
ꢄꢇꢆ
9 ꢁꢉ9ꢊ
,
9 ꢁꢉ9ꢊ
,
(1) Tamb = 125 C.
(2) amb = 85 C.
(1) Tamb = 125 C.
(2) amb = 85 C.
T
T
(3) Tamb = 25 C.
(4) Tamb = 40 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
Fig 11. ON resistance as a function of input voltage;
VCC = 1.8 V
Fig 12. ON resistance as a function of input voltage;
VCC = 2.5 V
ꢀꢀꢁDDDꢄꢀꢇ
ꢀꢀꢁDDDꢄꢁꢀ
ꢃꢅ
ꢃꢋ
5
21ꢁ
5
21ꢁ
ꢉȍꢊ
ꢉȍꢊ
ꢃꢃ
ꢌ
ꢉꢃꢊ
ꢉꢃꢊ
ꢉꢄꢊ
ꢍ
ꢎ
ꢆ
ꢉꢄꢊ
ꢉꢅꢊ
ꢈ
ꢀ
ꢉꢅꢊ
ꢉꢀꢊ
ꢉꢀꢊ
ꢋ
ꢋꢇꢆ
ꢃꢇꢋ
ꢃꢇꢆ
ꢄꢇꢋ
ꢄꢇꢆ
9 ꢁꢉ9ꢊ
ꢅꢇꢋ
ꢋ
ꢃ
ꢄ
ꢅ
ꢀ
9 ꢁꢉ9ꢊ
,
,
(1) Tamb = 125 C.
(2) Tamb = 85 C.
(1) Tamb = 125 C.
(2) Tamb = 85 C.
(3)
Tamb = 25 C.
(3)
Tamb = 25 C.
(4) Tamb = 40 C.
(4) Tamb = 40 C.
Fig 13. ON resistance as a function of input voltage;
VCC = 2.7 V
Fig 14. ON resistance as a function of input voltage;
VCC = 3.3 V
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
8 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
ꢀꢀꢁDDDꢄꢁꢁ
ꢎ
5
ꢁ
21
ꢉȍꢊ
ꢈ
ꢆ
ꢀ
ꢅ
ꢉꢃꢊ
ꢉꢄꢊ
ꢉꢅꢊ
ꢉꢀꢊ
ꢋ
ꢃ
ꢄ
ꢅ
ꢀ
ꢆ
9 ꢁꢉ9ꢊ
,
(1) Tamb = 125 C.
(2)
Tamb = 85 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
Fig 15. ON resistance as a function of input voltage; VCC = 5.0 V
11. Dynamic characteristics
Table 9.
Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 18.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
[2][3]
tpd
propagation delay Y to Z or Z to Y;
see Figure 16
VCC = 1.65 V to 1.95 V
-
-
-
-
-
0.8
0.4
0.4
0.3
0.2
2.0
1.2
1.0
0.8
0.6
-
-
-
-
-
3.0
2.0
1.5
1.5
1.0
ns
ns
ns
ns
ns
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
E to Y or Z; see Figure 17
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[4]
ten
enable time
1.0
1.0
1.0
1.0
1.0
5.3
3.0
2.6
2.5
1.9
12
6.5
6.0
5.0
4.2
1.0
1.0
1.0
1.0
1.0
15.5
8.5
8.0
6.5
5.5
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
9 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
Table 9.
Dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 18.
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
[5]
tdis
disable time
E to Y or Z; see Figure 17
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.0
1.0
1.0
1.0
1.0
4.2
2.4
3.6
3.4
2.5
10
6.9
7.5
6.5
5.0
1.0
1.0
1.0
1.0
1.0
13
9.0
9.5
8.5
6.5
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
[6]
CPD
power dissipation CL = 50 pF; fi = 10 MHz;
capacitance
VI = GND to VCC
VCC = 2.5 V
-
-
-
9.8
-
-
-
-
-
-
-
-
-
pF
pF
pF
VCC = 3.3 V
12.0
17.3
VCC = 5.0 V
[1] Typical values are measured at Tamb = 25 C and nominal VCC
.
[2] tpd is the same as tPLH and tPHL
[3] propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when
driven by an ideal voltage source (zero output impedance).
[4]
ten is the same as tPZH and tPZL
[5] tdis is the same as tPLZ and tPHZ
[6] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + {(CL + CS(ON)) VCC2 fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
CS(ON) = maximum ON-state switch capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
{(CL + CS(ON)) VCC2 fo} = sum of the outputs.
11.1 Waveforms and test circuit
9
,
9
<ꢁRUꢁ=ꢁLQSXW
=ꢁRUꢁ<ꢁRXWSXW
0
*1'
W
W
3/+
3+/
9
2+
9
0
9
2/
PQDꢅꢅꢄ
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 16. Input (Y or Z) to output (Z or Y) propagation delays
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
10 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
9
,
(
9
0
*1'
W
W
3=/
3/=
9
&&
RXWSXWꢁ
<ꢁRUꢁ=
<ꢁRUꢁ=
/2:ꢏWRꢏ2))ꢁ
2))ꢏWRꢏ/2:
9
0
9
;
9
2/
W
W
3=+
3+=
9
2+
9
RXWSXWꢁ
+,*+ꢏWRꢏ2))ꢁ
2))ꢏWRꢏ+,*+
<
9
0
*1'
VZLWFKꢁ
VZLWFKꢁ
VZLWFKꢁ
HQDEOHG
HQDEOHG
GLVDEOHG
PQDꢅꢅꢃ
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 17. Enable and disable times
Table 10. Measurement points
Supply voltage
VCC
Input
Output
VM
VM
VX
VY
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5VCC
0.5VCC
1.5 V
1.5 V
0.5VCC
0.5VCC
0.5VCC
1.5 V
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
VOL + 0.3 V
VOH 0.15 V
VOH 0.15 V
VOH 0.3 V
VOH 0.3 V
VOH 0.3 V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
0.5VCC
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
11 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
9
(;7
9
&&
5
/
9
9
2
,
*
'87
5
7
&
/
5
/
PQDꢅꢁꢅ
Test data is given in Table 11.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
VEXT = External voltage for measuring switching times.
Fig 18. Test circuit for measuring switching times
Table 11. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPZH, tPHZ
tPZL, tPLZ
2VCC
2VCC
6 V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
VCC
2.0 ns
2.0 ns
2.5 ns
2.5 ns
2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 k
GND
GND
GND
GND
GND
500
500
500
500
open
open
3.0 V to 3.6 V
4.5 V to 5.5 V
open
6 V
open
2VCC
11.2 Additional dynamic characteristics
Table 12. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
THD
total harmonic distortion
RL = 10 k; CL = 50 pF; fi = 1 kHz;
see Figure 19
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
-
-
-
-
0.032
0.008
0.006
0.001
-
-
-
-
%
%
%
%
RL = 10 k; CL = 50 pF; fi = 10 kHz;
see Figure 19
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
-
-
-
-
0.068
0.009
0.008
0.006
-
-
-
-
%
%
%
%
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
12 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
Table 12. Additional dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
f(3dB)
3 dB frequency response RL = 600 ; CL = 50 pF;
see Figure 20
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
-
-
-
-
135
145
150
155
-
-
-
-
MHz
MHz
MHz
MHz
RL = 50 ; CL = 5 pF; see Figure 20
VCC = 1.65 V
VCC = 2.3 V
-
-
-
-
500
500
500
500
-
-
-
-
MHz
MHz
MHz
MHz
VCC = 3.0 V
VCC = 4.5 V
RL = 50 ; CL = 10 pF; see Figure 20
VCC = 1.65 V
-
-
-
-
200
350
410
440
-
-
-
-
MHz
MHz
MHz
MHz
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
iso
isolation (OFF-state)
RL = 600 ; CL = 50 pF; fi = 1 MHz;
see Figure 21
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
-
-
-
-
46
46
46
46
-
-
-
-
dB
dB
dB
dB
RL = 50 ; CL = 5 pF; fi = 1 MHz;
see Figure 21
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
-
-
-
-
37
37
37
37
-
-
-
-
dB
dB
dB
dB
Vct
crosstalk voltage
between digital input and switch;
RL = 600 ; CL = 50 pF; fi = 1 MHz;
tr = tf = 2 ns; see Figure 22
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
-
-
-
-
69
87
-
-
-
-
mV
mV
mV
mV
156
302
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
13 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
Table 12. Additional dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Qinj
charge injection
CL = 0.1 nF; Vgen = 0 V; Rgen = 0 ;
fi = 1 MHz; RL = 1 M; see Figure 23
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 5.5 V
-
-
-
-
-
3.3
4.1
5.0
6.4
7.5
-
-
-
-
-
pC
pC
pC
pC
pC
11.3 Test circuits
9
ꢋꢇꢆ9
&&
&&
(
9
5
/
,+
ꢃꢋꢁ)
<ꢐ=
=ꢐ<
9
2
I
L
ꢈꢋꢋꢁȍ
&
/
'
ꢀꢀꢁDDPꢆꢇꢉ
Test conditions:
VCC = 1.65 V: Vi = 1.4 V (p-p).
VCC = 2.3 V: Vi = 2 V (p-p).
V
CC = 3 V: Vi = 2.5 V (p-p).
VCC = 4.5 V: Vi = 4 V (p-p).
Fig 19. Test circuit for measuring total harmonic distortion
9
ꢋꢇꢆ9
&&
&&
(
9
5
/
,+
ꢋꢇꢃꢁ)
ꢆꢋꢁȍ
<ꢐ=
=ꢐ<
9
2
I
L
&
/
G%
ꢀꢀꢁDDPꢆꢇꢆ
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3 dB.
Fig 20. Test circuit for measuring the frequency response when switch is in ON-state
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
14 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
ꢋꢇꢆ9
9
ꢋꢇꢆ9
&&
&&
&&
(
5
/
9
5
/
,/
ꢋꢇꢃꢁ)
<ꢐ=
=ꢐ<
9
2
I
L
ꢆꢋꢁȍ
&
/
G%
ꢀꢀꢁDDPꢆꢇꢂ
Adjust fi voltage to obtain 0 dBm level at input.
Fig 21. Test circuit for measuring isolation (OFF-state)
9
&&
(
<ꢐ=
=ꢐ<
9
2
ORJLFꢁ
LQSXW
*
5
/
&
/
ꢆꢋꢁȍ
ꢈꢋꢋꢁȍ
ꢋꢇꢆ9
ꢋꢇꢆ9
ꢀꢀꢁDDPꢆꢇꢈ
&&
&&
Fig 22. Test circuit for measuring crosstalk between digital input and switch
9
&&
(
5
JHQ
<ꢐ=
=ꢐ<
9
2
5
/ꢁ
ꢃꢁ0ȍꢁ
&
/ꢁ
ꢋꢇꢃꢁQ)
*
ORJLFꢁ
LQSXW
9
JHQ
ꢀꢀꢁDDPꢆꢇꢅ
ORJLFꢁ
LQSXWꢁꢉ(ꢊ
RII
RQ
RII
9
2
ǻ9
2
ꢀꢀꢁDDPꢆꢇꢃ
Qinj = VO CL.
VO = output voltage variation.
Rgen = generator resistance.
V
gen = generator voltage.
Fig 23. Test circuit for measuring charge injection
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
15 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
12. Package outline
76623ꢊꢋꢄSODVWLFꢄWKLQꢄVKULQNꢄVPDOOꢄRXWOLQHꢄSDFNDJHꢌꢄꢊꢄOHDGVꢌꢄERG\ꢄZLGWKꢄꢂꢅꢆꢊꢄPPꢄ
627ꢇꢊꢇꢍꢂꢄ
'ꢁ
(ꢁ
$ꢁ
;ꢁ
Fꢁ
\ꢁ
+
Yꢁ 0ꢁ
$ꢁ
(ꢁ
=ꢁ
ꢆꢁ
ꢃꢁ
ꢀꢁ
ꢅꢁ
$
ꢄꢁ
$ꢁ
ꢉ$ ꢊꢁ
ꢅ
$
ꢃꢁ
șꢁ
/
Sꢁ
/ꢁ
Hꢁ
Zꢁ 0ꢁ
E
Sꢁ
GHWDLOꢁ;ꢁ
H
ꢃꢁ
ꢋꢁ
ꢃꢇꢆꢁ
ꢅꢁPPꢁ
VFDOHꢁ
',0(16,216ꢄꢈPPꢄDUHꢄWKHꢄRULJLQDOꢄGLPHQVLRQVꢉꢄ
$ꢄ
ꢈꢂꢉꢄ
ꢈꢂꢉꢄ
ꢈꢂꢉꢄ
$
$
$
E
Fꢄ
'
(
Hꢄ
ꢋꢇꢈꢆꢁ
H
+
/ꢄ
/
81,7ꢄ
șꢁ
Yꢄ
Zꢄ
ꢋꢇꢃꢁ
\ꢄ
=
ꢂꢄ
ꢆꢄ
ꢇꢄ
Sꢄ
ꢂꢄ
(ꢄ
Sꢄ
PD[ꢅꢄ
ꢋꢇꢃꢁ
ꢋꢁ
ꢃꢇꢋꢁ
ꢋꢇꢌꢁ
ꢋꢇꢅꢋꢁ ꢋꢇꢄꢆꢁ ꢄꢇꢄꢆꢁ ꢃꢇꢅꢆꢁ
ꢋꢇꢃꢆꢁ ꢋꢇꢋꢌꢁ ꢃꢇꢌꢆꢁ ꢃꢇꢃꢆꢁ
ꢄꢇꢄꢆꢁ
ꢄꢇꢋꢁ
ꢋꢇꢀꢈꢁ
ꢋꢇꢄꢃꢁ
ꢋꢇꢈꢋꢁ
ꢋꢇꢃꢆꢁ
ꢎꢁ
ꢋꢁ
PPꢁ
ꢃꢇꢃꢁ
ꢃꢇꢅꢁ
ꢋꢇꢀꢄꢆꢁ
ꢋꢇꢅꢁ
ꢋꢇꢃꢁ
ꢋꢇꢃꢆꢁ
1RWHꢄ
ꢃꢇꢁ3ODVWLFꢁRUꢁPHWDOꢁSURWUXVLRQVꢁRIꢁꢋꢇꢃꢆꢁPPꢁPD[LPXPꢁSHUꢁVLGHꢁDUHꢁQRWꢁLQFOXGHGꢇꢁ
ꢄ5()(5(1&(6ꢄ
287/,1(ꢄ
9(56,21ꢄ
(8523($1ꢄ
352-(&7,21ꢄ
,668(ꢄ'$7(ꢄ
ꢄ,(&ꢄ
ꢄ-('(&ꢄ
02ꢏꢁꢄꢋꢅꢁ
ꢄ-(,7$ꢄ
ꢋꢋꢏꢋꢍꢏꢋꢃꢁ
ꢋꢅꢏꢋꢄꢏꢃꢍꢁ
ꢁ627ꢅꢆꢅꢏꢃꢁ
6&ꢏꢌꢌ$ꢁ
Fig 24. Package outline SOT353-1 (TSSOP5)
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
16 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
3ODVWLFꢄVXUIDFHꢍPRXQWHGꢄSDFNDJHꢌꢄꢊꢄOHDGV
627ꢀꢊꢇ
'
%
(
$
;
\
+
Y
0
$
(
ꢊ
ꢁ
4
$
$
ꢃ
F
/
S
ꢂ
ꢆ
ꢇ
GHWDLOꢁ;
E
H
Z
0 %
S
ꢋ
ꢃ
ꢄꢁPP
VFDOH
',0(16,216ꢄꢈPPꢄDUHꢄWKHꢄRULJLQDOꢄGLPHQVLRQVꢉ
81,7
$
$
ꢂ
E
F
'
H
+
/
4
Y
Z
\
(
S
S
(
ꢋꢇꢃꢋꢋꢁ
ꢋꢇꢋꢃꢅ
ꢋꢇꢀꢋꢁ
ꢋꢇꢄꢆ
ꢃꢇꢃꢁ
ꢋꢇꢍ
ꢋꢇꢄꢈꢁ
ꢋꢇꢃꢋ
ꢅꢇꢃꢁ
ꢄꢇꢎ
ꢃꢇꢎꢁ
ꢃꢇꢅ
ꢅꢇꢋꢁ
ꢄꢇꢆ
ꢋꢇꢈꢁ
ꢋꢇꢄ
ꢋꢇꢅꢅꢁ
ꢋꢇꢄꢅ
PP
ꢋꢇꢍꢆ
ꢋꢇꢄ
ꢋꢇꢄ
ꢋꢇꢃ
ꢄ5()(5(1&(6
ꢄ-('(& ꢄ-(,7$
6&ꢏꢎꢀ$
(8523($1ꢄ
352-(&7,21
287/,1(ꢄ
9(56,21
,668(ꢄ'$7(
ꢄ,(&
ꢋꢄꢏꢋꢀꢏꢃꢈꢁ
ꢋꢈꢏꢋꢅꢏꢃꢈ
ꢁ627ꢎꢆꢅ
ꢁ
Fig 25. Package outline SOT753 (SC-74A)
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
17 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
;621ꢈꢑꢁSODVWLFꢁH[WUHPHO\ꢁWKLQꢁVPDOOꢁRXWOLQHꢁSDFNDJHꢒꢁQRꢁOHDGVꢒꢁꢈꢁWHUPLQDOVꢒꢁERG\ꢁꢃꢁ[ꢁꢃꢇꢀꢆꢁ[ꢁꢋꢇꢆꢁPP
E
627ꢌꢌꢈ
ꢃ
ꢄ
ꢅ
ꢀ[
ꢉꢄꢊ
/
/
ꢃ
H
ꢈ
ꢆ
ꢀ
H
H
ꢃ
ꢃ
ꢈ[
ꢉꢄꢊ
$
$
ꢃ
'
(
WHUPLQDOꢁꢃ
LQGH[ꢁDUHD
ꢋ
ꢃ
ꢄꢁPP
VFDOH
'LPHQVLRQVꢁꢉPPꢁDUHꢁWKHꢁRULJLQDOꢁGLPHQVLRQVꢊ
ꢉꢃꢊ
8QLW
$
$
E
'
(
H
H
/
/
ꢃ
ꢃ
ꢃ
PD[ ꢋꢇꢆ ꢋꢇꢋꢀ ꢋꢇꢄꢆ ꢃꢇꢆꢋ ꢃꢇꢋꢆ
ꢋꢇꢅꢆ ꢋꢇꢀꢋ
ꢋꢇꢅꢋ ꢋꢇꢅꢆ
ꢋꢇꢄꢎ ꢋꢇꢅꢄ
QRP
PLQ
ꢋꢇꢄꢋ ꢃꢇꢀꢆ ꢃꢇꢋꢋ ꢋꢇꢈ
ꢋꢇꢃꢎ ꢃꢇꢀꢋ ꢋꢇꢍꢆ
PP
ꢋꢇꢆ
1RWHV
ꢃꢇꢁ,QFOXGLQJꢁSODWLQJꢁWKLFNQHVVꢇ
ꢄꢇꢁ&DQꢁEHꢁYLVLEOHꢁLQꢁVRPHꢁPDQXIDFWXULQJꢁSURFHVVHVꢇ
VRWꢃꢃꢅBSR
5HIHUHQFHV
2XWOLQH
(XURSHDQ
SURMHFWLRQ
,VVXHꢁGDWH
YHUVLRQ
,(&
-('(&
02ꢏꢄꢆꢄ
-(,7$
ꢋꢀꢏꢋꢎꢏꢄꢄ
ꢃꢄꢏꢋꢃꢏꢋꢆ
627ꢌꢌꢈ
Fig 26. Package outline SOT886 (XSON6)
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
18 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
;621ꢃꢋꢄSODVWLFꢄH[WUHPHO\ꢄWKLQꢄVPDOOꢄRXWOLQHꢄSDFNDJHꢌꢄQRꢄOHDGVꢌꢄꢃꢄWHUPLQDOVꢌꢄERG\ꢄꢂꢄ[ꢄꢂꢄ[ꢄꢐꢅꢊꢄPP
627ꢎꢏꢂ
E
ꢇ
ꢂ
ꢆ
ꢀîꢁ
ꢉꢃꢊ
/
/
ꢃ
H
ꢃ
ꢊ
ꢁ
H
ꢃ
H
ꢃ
ꢈîꢁ
ꢉꢃꢊ
$
$
ꢃ
'
(
WHUPLQDOꢁꢃꢁ
LQGH[ꢁDUHD
ꢋ
ꢃ
ꢄꢁPP
VFDOH
',0(16,216ꢄꢈPPꢄDUHꢄWKHꢄRULJLQDOꢄGLPHQVLRQVꢉ
ꢄ
$
$
ꢂꢄ
81,7
E
'
(
H
H
/
/
ꢂ
ꢂ
PD[ PD[
ꢋꢇꢄꢋꢁ ꢃꢇꢋꢆꢁ ꢃꢇꢋꢆꢁ
ꢋꢇꢃꢄ ꢋꢇꢍꢆ ꢋꢇꢍꢆ
ꢋꢇꢅꢆꢁ ꢋꢇꢀꢋꢁ
ꢋꢇꢄꢎ ꢋꢇꢅꢄ
PP
ꢋꢇꢆ ꢋꢇꢋꢀ
ꢋꢇꢆꢆ
ꢋꢇꢅꢆ
1RWHꢄ
ꢃꢇꢁ&DQꢁEHꢁYLVLEOHꢁLQꢁVRPHꢁPDQXIDFWXULQJꢁSURFHVVHVꢇ
5()(5(1&(6
-('(& -(,7$
287/,1(ꢄ
9(56,21
(8523($1ꢄ
352-(&7,21
,668(ꢄ'$7(
,(&
ꢋꢆꢏꢋꢀꢏꢋꢈꢁ
ꢋꢎꢏꢋꢆꢏꢃꢆ
627ꢌꢍꢃ
ꢁ
ꢁ
Fig 27. Package outline SOT891 (XSON6)
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
19 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
;621ꢃꢋꢄH[WUHPHO\ꢄWKLQꢄVPDOOꢄRXWOLQHꢄSDFNDJHꢌꢄQRꢄOHDGVꢌꢄ
ꢃꢄWHUPLQDOVꢌꢄERG\ꢄꢐꢅꢏꢄ[ꢄꢂꢅꢐꢄ[ꢄꢐꢅꢇꢊꢄPP
627ꢂꢂꢂꢊ
E
ꢅ
ꢉꢄꢊ
ꢉꢀîꢊ
ꢃ
ꢄ
/
/
ꢃ
H
ꢈ
ꢆ
ꢀ
H
H
ꢃ
ꢃ
ꢉꢄꢊ
ꢉꢈîꢊ
$
ꢃ
$
'
(
WHUPLQDOꢁꢃꢁ
LQGH[ꢁDUHD
ꢋ
/
ꢋꢇꢆ
VFDOH
ꢃꢁPP
'LPHQVLRQV
8QLW
ꢉꢃꢊ
$
$
E
'
(
H
H
ꢃ
/
ꢃ
ꢃ
PD[ꢁ ꢋꢇꢅꢆ ꢋꢇꢋꢀ ꢋꢇꢄꢋꢁ ꢋꢇꢍꢆꢁ ꢃꢇꢋꢆꢁ
ꢋꢇꢅꢆꢁ ꢋꢇꢀꢋꢁ
ꢋꢇꢃꢆꢁ ꢋꢇꢍꢋꢁ ꢃꢇꢋꢋꢁ ꢋꢇꢆꢆ ꢋꢇꢅ ꢋꢇꢅꢋꢁ ꢋꢇꢅꢆꢁ
ꢋꢇꢃꢄ ꢋꢇꢌꢆ ꢋꢇꢍꢆ ꢋꢇꢄꢎ ꢋꢇꢅꢄ
PP QRPꢁ
PLQ
1RWHꢁ
ꢃꢇꢁ,QFOXGLQJꢁSODWLQJꢁWKLFNQHVVꢇꢁ
ꢄꢇꢁ9LVLEOHꢁGHSHQGLQJꢁXSRQꢁXVHGꢁPDQXIDFWXULQJꢁWHFKQRORJ\ꢇ
VRWꢁꢁꢁꢈBSR
5HIHUHQFHV
2XWOLQHꢁ
YHUVLRQ
(XURSHDQꢁ
SURMHFWLRQ
,VVXHꢁGDWH
,(&
ꢁ
-('(&
ꢁ
-(,7$
ꢃꢋꢏꢋꢀꢏꢋꢄꢁ
ꢃꢋꢏꢋꢀꢏꢋꢎ
627ꢃꢃꢃꢆ
ꢁ
Fig 28. Package outline SOT1115 (XSON6)
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
20 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
;621ꢃꢋꢄH[WUHPHO\ꢄWKLQꢄVPDOOꢄRXWOLQHꢄSDFNDJHꢌꢄQRꢄOHDGVꢌꢄ
ꢃꢄWHUPLQDOVꢌꢄERG\ꢄꢂꢅꢐꢄ[ꢄꢂꢅꢐꢄ[ꢄꢐꢅꢇꢊꢄPP
627ꢂꢆꢐꢆ
E
ꢅ
ꢉꢄꢊ
ꢃ
ꢄ
ꢉꢀîꢊ
/
/
ꢃ
H
ꢈ
ꢆ
ꢀ
H
H
ꢃ
ꢃ
ꢉꢄꢊ
ꢉꢈîꢊ
$
ꢃ
$
'
(
WHUPLQDOꢁꢃꢁ
LQGH[ꢁDUHD
ꢋ
/
ꢋꢇꢆ
ꢃꢁPP
VFDOH
'LPHQVLRQV
8QLW
ꢉꢃꢊ
$
$
E
'
(
H
H
ꢃ
/
ꢃ
ꢃ
PD[ꢁ ꢋꢇꢅꢆ ꢋꢇꢋꢀ ꢋꢇꢄꢋꢁ ꢃꢇꢋꢆꢁ ꢃꢇꢋꢆꢁ
ꢋꢇꢅꢆꢁ ꢋꢇꢀꢋꢁ
ꢋꢇꢃꢆꢁ ꢃꢇꢋꢋꢁ ꢃꢇꢋꢋꢁ ꢋꢇꢆꢆ ꢋꢇꢅꢆ ꢋꢇꢅꢋꢁ ꢋꢇꢅꢆꢁ
ꢋꢇꢃꢄ ꢋꢇꢍꢆ ꢋꢇꢍꢆ ꢋꢇꢄꢎ ꢋꢇꢅꢄ
PP QRPꢁ
PLQ
1RWHꢁ
ꢃꢇꢁ,QFOXGLQJꢁSODWLQJꢁWKLFNQHVVꢇꢁ
ꢄꢇꢁ9LVLEOHꢁGHSHQGLQJꢁXSRQꢁXVHGꢁPDQXIDFWXULQJꢁWHFKQRORJ\ꢇ
VRWꢁꢉꢀꢉBSR
5HIHUHQFHV
2XWOLQHꢁ
YHUVLRQ
(XURSHDQꢁ
SURMHFWLRQ
,VVXHꢁGDWH
,(&
ꢁ
-('(&
ꢁ
-(,7$
ꢃꢋꢏꢋꢀꢏꢋꢄꢁ
ꢃꢋꢏꢋꢀꢏꢋꢈ
627ꢃꢄꢋꢄ
ꢁ
Fig 29. Package outline SOT1202 (XSON6)
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
21 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
13. Abbreviations
Table 13. Abbreviations
Acronym
CMOS
TTL
Description
Complementary Metal Oxide Semiconductor
Transistor-Transistor Logic
Human Body Model
HBM
ESD
ElectroStatic Discharge
Machine Model
MM
DUT
Device Under Test
14. Revision history
Table 14. Revision history
Document ID
74LVC1G66 v.9
Modifications:
Release date
20150115
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LVC1G66 v.8
• SOT886 (XSON6) package outline drawing modified.
74LVC1G66 v.8
Modifications:
20111202
Product data sheet
-
74LVC1G66 v.7
• Legal pages updated.
74LVC1G66 v.7
74LVC1G66 v.6
74LVC1G66 v.5
74LVC1G66 v.4
74LVC1G66 v.3
74LVC1G66 v.2
74LVC1G66 v.1
20100730
20070827
20070807
20040413
20021115
20020529
20011030
Product data sheet
-
-
-
-
-
-
-
74LVC1G66 v.6
74LVC1G66 v.5
74LVC1G66 v.4
74LVC1G66 v.3
74LVC1G66 v.2
74LVC1G66 v.1
-
Product data sheet
Product data sheet
Product specification
Product specification
Product specification
Product specification
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
22 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
15.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
23 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC1G66
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 15 January 2015
24 of 25
74LVC1G66
NXP Semiconductors
Bilateral switch
17. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
8
9
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
10
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance test circuit and graphs. . . . . . . . 7
10.1
10.2
10.3
11
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms and test circuit . . . . . . . . . . . . . . . 10
Additional dynamic characteristics . . . . . . . . . 12
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
11.1
11.2
11.3
12
13
14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 23
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 24
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 January 2015
Document identifier: 74LVC1G66
相关型号：
©2020 ICPDF网 联系我们和版权申明