74LVC1G74GT [NXP]
Single D-type flip-flop with set and reset; positive edge trigger; 单一的D- FL型IP- FL运算与置位和复位;上升沿触发
| 型号： | 74LVC1G74GT |
| 厂家： | 
NXP |
| 描述： | Single D-type flip-flop with set and reset; positive edge trigger |
| 文件： | 总19页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVC1G74
Single D-type flip-flop with set and
reset; positive edge trigger
Product specification
2005 Feb 01
Supersedes data of 2004 Sep 09
Philips Semiconductors
Product specification
Single D-type flip-flop with set and
reset; positive edge trigger
74LVC1G74
FEATURES
DESCRIPTION
• Wide supply voltage range from 1.65 V to 5.5 V
• 5 V tolerant inputs for interfacing with 5 V logic
• High noise immunity
The 74LVC1G74 is a high-performance, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
The 74LVC1G74 is a single positive edge triggered D-type
flip-flop with individual data (D) inputs, clock (CP) inputs,
set (SD) and (RD) inputs, and complementary Q and Q
outputs.
• Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V).
• ±24 mA output drive (VCC = 3.0 V)
• ESD protection:
This device is fully specified for partial power down
applications using Ioff. The Ioff circuitry disables the output,
preventing damaging backflow current through the device
when it is powered down.
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
• CMOS low power consumption
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
clock transition, for predictable operation.
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• Inputs accept voltages up to 5 V
• Multiple package options
Schmitt-trigger action at all inputs makes the circuit highly
tolerant to slower input rise and fall times.
• Specified from −40 °C to +85 °C and −40 °C to +125 °C.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
PARAMETER
propagation delay
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
CP to Q, Q
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
3.5
ns
ns
ns
SD to Q, Q
3.0
3.0
280
4.0
15
RD to Q, Q
fmax
CI
maximum clock frequency
input capacitance
power dissipation capacitance
MHz
pF
CPD
VCC = 3.3 V; notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC
.
2005 Feb 01
2
Philips Semiconductors
Product specification
Single D-type flip-flop with set and
reset; positive edge trigger
74LVC1G74
FUNCTION TABLES
Table 1 Asynchronous operation. See note 1.
INPUT
OUTPUT
SD
RD
CP
D
Q
Q
L
H
L
H
L
L
X
X
X
X
X
X
H
L
L
H
H
H
Table 2 Synchronous operation. See note 1.
INPUT
OUTPUT
SD
H
RD
H
CP
↑
D
L
Qn+1
L
Qn+1
H
H
H
↑
H
H
L
Note to Tables 1 and 2
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑ = LOW-to-HIGH CP transition;
Qn+1 = state after the next LOW-to-HIGH CP transition.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE
PINS
PACKAGE
MATERIAL
CODE
MARKING
RANGE
74LVC1G74DP
74LVC1G74DC
74LVC1G74GT
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
8
8
8
TSSOP8
VSSOP8
XSON8
plastic
plastic
plastic
SOT505-2
SOT765-1
SOT833-1
V74
V74
V74
PINNING
SYMBOL
PIN
DESCRIPTION
CP
D
1
2
3
4
5
6
7
8
clock input (LOW-to-HIGH, edge-triggered)
data input
Q
complement flip-flop output
ground (0 V)
GND
Q
true flip-flop output
RD
SD
VCC
asynchronous reset-direct input (active LOW)
asynchronous set-direct input (active LOW)
supply voltage
2005 Feb 01
3
Philips Semiconductors
Product specification
Single D-type flip-flop with set and
reset; positive edge trigger
74LVC1G74
74
CP
D
1
2
3
4
8
7
6
5
V
CC
1
2
3
4
8
7
6
5
CP
D
V
CC
SD
RD
Q
SD
RD
Q
74
Q
Q
GND
001aab659
GND
001aab658
Transparent top view
Fig.1 Pin configuration TSSOP8 and VSSOP8.
Fig.2 Pin configuration XSON8.
7
handbook, halfpage
SD
7
SD
handbook, halfpage
S
Q
Q
5
3
5
2
1
D
D
Q
Q
1
C1
CP
2
CP
1D
R
3
6
FF
MNB140
RD
RD
6
MNB139
Fig.3 Logic symbol.
Fig.4 IEC logic symbol.
2005 Feb 01
4
Philips Semiconductors
Product specification
Single D-type flip-flop with set and
reset; positive edge trigger
74LVC1G74
Q
C
C
C
C
C
C
C
D
Q
C
RD
SD
MNA421
CP
C
C
Fig.5 Logic diagram.
2005 Feb 01
5
Philips Semiconductors
Product specification
Single D-type flip-flop with set and
reset; positive edge trigger
74LVC1G74
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
PARAMETER
supply voltage
CONDITIONS
MIN.
1.65
MAX.
5.5
UNIT
V
VI
input voltage
0
5.5
VCC
5.5
+125
20
V
VO
output voltage
active mode
0
V
VCC = 0 V; Power-down mode
0
V
Tamb
tr, tf
ambient temperature
−40
0
°C
input rise and fall times
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
ns/V
ns/V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +6.5
V
IIK
input diode current
input voltage
VI < 0 V
note 1
−
−50
mA
V
VI
−0.5
−
+6.5
±50
IOK
VO
output diode current
output voltage
VO > VCC or VO < 0 V
mA
V
active mode; notes 1 and 2
−0.5
VCC + 0.5
+6.5
±50
Power-down mode; notes 1 and 2 −0.5
V
IO
output source or sink current
VCC or GND current
storage temperature
power dissipation
VO = 0 V to VCC
−
mA
mA
°C
mW
ICC, IGND
Tstg
−
±100
+150
250
−65
−
Ptot
Tamb = −40 °C to +125 °C
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
2005 Feb 01
6
Philips Semiconductors
Product specification
Single D-type flip-flop with set and
reset; positive edge trigger
74LVC1G74
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 °C to +85 °C; note 1
VIH
HIGH-level input
voltage
1.65 to 1.95 0.65 × VCC
−
−
−
−
−
−
−
−
−
−
−
−
V
V
V
V
V
V
V
V
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.7
2.0
0.7 × VCC
VIL
LOW-level input voltage
−
−
−
−
0.35 × VCC
0.7
0.8
0.3 × VCC
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −100 µA
IO = −4 mA
IO = −8 mA
IO = −12 mA
IO = −24 mA
IO = −32 mA
VI = VIH or VIL
IO = 100 µA
IO = 4 mA
1.65 to 5.5
1.65
2.3
V
CC − 0.1
−
−
−
−
−
−
−
V
V
V
V
V
V
1.2
1.9
2.2
2.3
3.8
1.54
2.15
2.50
2.62
4.11
2.7
3.0
4.5
VOL
LOW-level output
voltage
1.65 to 5.5
1.65
2.3
−
−
−
−
−
−
−
−
-
0.10
0.45
0.30
0.40
0.55
0.55
±5
V
0.07
0.12
0.17
0.33
0.39
±0.1
±0.1
V
IO = 8 mA
V
IO = 12 mA
IO = 24 mA
IO = 32 mA
2.7
V
3.0
V
4.5
V
ILI
input leakage current
VI = 5.5 V or GND 5.5
µA
µA
Ioff
power OFF leakage
current
VI or VO = 5.5 V
0
±10
ICC
quiescent supply
current
VI = VCC or GND;
IO = 0 A
5.5
−
−
0.1
5
10
µA
µA
∆ICC
additional quiescent
supply current per pin
VI = VCC − 0.6 V;
IO = 0 A
2.3 to 5.5
500
2005 Feb 01
7
Philips Semiconductors
Product specification
Single D-type flip-flop with set and
reset; positive edge trigger
74LVC1G74
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 °C to +125 °C
VIH
HIGH-level input
voltage
1.65 to 1.95 0.65 × VCC
−
−
−
−
−
−
−
−
−
−
−
−
V
V
V
V
V
V
V
V
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.7
2.0
0.7 × VCC
VIL
LOW-level input voltage
−
−
−
−
0.35 × VCC
0.7
0.8
0.3 × VCC
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −100 µA
IO = −4 mA
IO = −8 mA
IO = −12 mA
IO = −24 mA
IO = −32 mA
VI = VIH or VIL
IO = 100 µA
IO = 4 mA
1.65 to 5.5
1.65
2.3
V
CC − 0.1
−
−
−
−
−
−
−
−
−
−
−
−
V
V
V
V
V
V
0.95
1.7
1.9
2.0
3.4
2.7
3.0
4.5
VOL
LOW-level output
voltage
1.65 to 5.5
1.65
2.3
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0.10
0.70
0.45
0.60
0.80
0.80
±20
V
V
IO = 8 mA
V
IO = 12 mA
IO = 24 mA
IO = 32 mA
2.7
V
3.0
V
4.5
V
ILI
input leakage current
VI = 5.5 V or GND 5.5
µA
µA
Ioff
power OFF leakage
current
VI or VO = 5.5 V
0
±20
ICC
quiescent supply
current
VI = VCC or GND;
IO = 0
5.5
−
−
−
−
40
µA
µA
∆ICC
additional quiescent
supply current per pin
VI = VCC − 0.6 V;
IO = 0
2.3 to 5.5
5000
Note
1. All typical values are measured at Tamb = 25 °C.
2005 Feb 01
8
Philips Semiconductors
Product specification
Single D-type flip-flop with set and
reset; positive edge trigger
74LVC1G74
AC CHARACTERISTICS
GND = 0 V.
TEST CONDITIONS
WAVEFORMS VCC (V)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Tamb = −40 °C to +85 °C; note 1
tPHL/tPLH propagation delay CP to Q, Q
see Figs 6 and 8 1.65 to 1.95
1.5
6.0
13.4
7.1
7.1
5.9
4.1
12.9
7.0
7.0
5.9
4.1
12.9
7.0
7.0
5.9
4.1
−
ns
2.3 to 2.7
1.0
1.0
1.0
1.0
1.5
1.0
1.0
1.0
1.0
1.5
1.0
1.0
1.0
1.0
6.2
2.7
2.7
2.7
2.0
6.2
2.7
2.7
2.7
2.0
1.9
1.4
1.3
1.2
1.0
2.9
1.7
1.7
1.3
1.1
3.5
3.5
3.5(2)
2.5
6.0
3.5
3.5
3.0(2)
2.5
5.0
3.5
3.5
3.0(2)
2.5
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.7
3.0 to 3.6
4.5 to 5.5
propagation delay SD to Q, Q
propagation delay RD to Q, Q
see Figs 7 and 8 1.65 to 1.95
2.3 to 2.7
2.7
3.0 to 3.6
4.5 to 5.5
see Figs 7 and 8 1.65 to 1.95
2.3 to 2.7
2.7
3.0 to 3.6
4.5 to 5.5
tW
clock pulse width HIGH or LOW see Figs 6 and 8 1.65 to 1.95
2.3 to 2.7
2.7
−
−
−
−
3.0 to 3.6
4.5 to 5.5
1.3(2)
−
−
−
set or reset pulse width LOW
removal time set or reset
set-up time D to CP
see Figs 7 and 8 1.65 to 1.95
−
−
2.3 to 2.7
−
−
2.7
−
−
3.0 to 3.6
1.6(2)
−
4.5 to 5.5
−
−
trem
see Figs 7 and 8 1.65 to 1.95
−
−
2.3 to 2.7
−
−
2.7
3.0 to 3.6
−
−
−3.0(2)
−
4.5 to 5.5
−
−
tsu
see Figs 6 and 8 1.65 to 1.95
2.3 to 2.7
−
−
−
−
2.7
−
−
3.0 to 3.6
0.5(2)
−
4.5 to 5.5
−
−
2005 Feb 01
9
Philips Semiconductors
Product specification
Single D-type flip-flop with set and
reset; positive edge trigger
74LVC1G74
TEST CONDITIONS
WAVEFORMS VCC (V)
SYMBOL
th
PARAMETER
hold time D to CP
MIN.
0.0
TYP.
MAX.
UNIT
ns
see Figs 6 and 8 1.65 to 1.95
−
−
−
−
2.3 to 2.7
2.7
0.3
0.5
1.2
0.5
80
−
−
−
−
−
−
−
−
−
ns
ns
3.0 to 3.6
4.5 to 5.5
0.6(2)
ns
−
ns
fmax
maximum clock pulse frequency see Figs 6 and 8 1.65 to 1.95
−
MHz
MHz
MHz
MHz
MHz
2.3 to 2.7
2.7
175
175
175
200
−
−
3.0 to 3.6
4.5 to 5.5
280(2)
−
Tamb = −40 °C to +125 °C
tPHL/tPLH
propagation delay CP to Q, Q
see Figs 6 and 8 1.65 to 1.95
1.5
1.0
1.0
1.0
1.0
1.5
1.0
1.0
1.0
1.0
1.5
1.0
1.0
1.0
1.0
6.2
2.7
2.7
2.7
2.0
6.2
2.7
2.7
2.7
2.0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
13.4
7.1
7.1
5.9
4.1
12.9
7.0
7.0
5.9
4.1
12.9
7.0
7.0
5.9
4.1
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.3 to 2.7
2.7
3.0 to 3.6
4.5 to 5.5
propagation delay SD to Q, Q
propagation delay RD to Q, Q
see Figs 7 and 8 1.65 to 1.95
2.3 to 2.7
2.7
3.0 to 3.6
4.5 to 5.5
see Figs 7 and 8 1.65 to 1.95
2.3 to 2.7
2.7
3.0 to 3.6
4.5 to 5.5
tW
clock pulse width HIGH or LOW see Figs 6 and 8 1.65 to 1.95
2.3 to 2.7
2.7
−
−
3.0 to 3.6
4.5 to 5.5
−
−
set or reset pulse width LOW
see Figs 7 and 8 1.65 to 1.95
−
2.3 to 2.7
2.7
−
−
3.0 to 3.6
4.5 to 5.5
−
−
2005 Feb 01
10
Philips Semiconductors
Product specification
Single D-type flip-flop with set and
reset; positive edge trigger
74LVC1G74
TEST CONDITIONS
WAVEFORMS VCC (V)
SYMBOL
trem
PARAMETER
MIN.
1.9
TYP.
MAX.
UNIT
ns
removal time set or reset
see Figs 7 and 8 1.65 to 1.95
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
2.3 to 2.7
1.4
1.3
1.2
1.0
2.9
1.7
1.7
1.3
1.1
0.0
0.3
0.5
1.2
0.5
80
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ns
2.7
ns
3.0 to 3.6
ns
4.5 to 5.5
ns
tsu
set-up time D to CP
hold time D to CP
see Figs 6 and 8 1.65 to 1.95
ns
2.3 to 2.7
ns
2.7
3.0 to 3.6
ns
ns
4.5 to 5.5
ns
th
see Figs 6 and 8 1.65 to 1.95
2.3 to 2.7
ns
ns
2.7
ns
3.0 to 3.6
ns
4.5 to 5.5
ns
fmax
maximum clock pulse frequency see Figs 6 and 8 1.65 to 1.95
MHz
MHz
MHz
MHz
MHz
2.3 to 2.7
2.7
175
175
175
200
3.0 to 3.6
4.5 to 5.5
Notes
1. All typical values are measured at Tamb = 25 °C.
2. These typical values are measured at VCC = 3.3 V.
2005 Feb 01
11
Philips Semiconductors
Product specification
Single D-type flip-flop with set and
reset; positive edge trigger
74LVC1G74
AC WAVEFORMS
V
I
V
D input
M
GND
t
t
h
h
t
t
su
su
1/f
max
V
I
V
CP input
M
GND
t
W
t
t
PLH
PHL
V
OH
V
Q output
Q output
M
V
OL
V
OH
V
M
V
OL
t
t
PHL
PLH
MNB141
The shaded areas indicate when the input is permitted to change for predictable output performance.
INPUT
VCC
VM
VI
tr = tf
1.65 V to 1.95 V 0.5 × VCC
VCC
VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
2.3 V to 2.7 V
2.7 V
0.5 × VCC
1.5 V
2.7 V
2.7 V
VCC
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
0.5 × VCC
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.6 The clock input (CP) to output (Q, Q) propagation delays, the clock pulse width, the D to CP set-up, the
CP to D hold times and the maximum clock pulse frequency.
2005 Feb 01
12
Philips Semiconductors
Product specification
Single D-type flip-flop with set and
reset; positive edge trigger
74LVC1G74
V
I
V
CP input
M
GND
t
rem
V
I
V
SD input
RD input
M
GND
t
t
W
W
V
I
V
M
GND
t
t
PHL
PLH
V
OH
Q output
Q output
V
V
M
V
OL
V
OH
M
t
V
OL
t
PHL
PLH
MNB142
INPUT
VCC
VM
VI
tr = tf
1.65 V to 1.95 V 0.5 × VCC
VCC
VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
2.3 V to 2.7 V
2.7 V
0.5 × VCC
1.5 V
2.7 V
2.7 V
VCC
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
0.5 × VCC
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.7 The set (SD) and reset (RD) input to output (Q, Q) propagation delays, the set and reset pulse widths and
the RD to CP removal time.
2005 Feb 01
13
Philips Semiconductors
Product specification
Single D-type flip-flop with set and
reset; positive edge trigger
74LVC1G74
V
EXT
V
CC
R
L
V
I
V
O
PULSE
GENERATOR
D.U.T.
C
L
R
L
R
T
mna616
VEXT
VCC
VI
CL
RL
tPLH/tPHL
tPZH/tPHZ
tPZL/tPLZ
1.65 V to 1.95 V VCC
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
open
open
open
open
open
GND
GND
GND
GND
GND
2 × VCC
2 × VCC
6 V
2.3 V to 2.7 V
2.7 V
VCC
500 Ω
500 Ω
500 Ω
500 Ω
2.7 V
2.7 V
VCC
3.0 V to 3.6 V
4.5 V to 5.5 V
6 V
2 × VCC
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.8 Load circuitry for switching times.
2005 Feb 01
14
Philips Semiconductors
Product specification
Single D-type flip-flop with set and
reset; positive edge trigger
74LVC1G74
PACKAGE OUTLINES
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.65
0.25
0.5
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
2005 Feb 01
15
Philips Semiconductors
Product specification
Single D-type flip-flop with set and
reset; positive edge trigger
74LVC1G74
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
2005 Feb 01
16
Philips Semiconductors
Product specification
Single D-type flip-flop with set and
reset; positive edge trigger
74LVC1G74
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
b
1
2
3
4
4×
(2)
L
L
1
e
8
7
6
5
e
1
e
1
e
1
8×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
2.0
1.9
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
- - -
04-07-22
04-11-09
SOT833-1
- - -
MO-252
2005 Feb 01
17
Philips Semiconductors
Product specification
Single D-type flip-flop with set and
reset; positive edge trigger
74LVC1G74
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2005 Feb 01
18
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2005
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R20/03/pp19
Date of release: 2005 Feb 01
Document order number: 9397 750 14529
相关型号：
74LVC1G74GT,115
74LVC1G74 - Single D-type flip-flop with set and reset; positive edge trigger SON 8-Pin
NXP
74LVC1G74GT-G
IC LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8, 1 X 1.95 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT-833-1, SON-8, FF/Latch
NXP
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