74LVC1G86GW-G [NXP]

暂无描述;
74LVC1G86GW-G
型号: 74LVC1G86GW-G
厂家: NXP    NXP
描述:

暂无描述

文件: 总12页 (文件大小:71K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
INTEGRATED CIRCUITS  
DATA SHEET  
74LVC1G86  
2-input EXCLUSIVE-OR gate  
Preliminary specification  
2001 Apr 06  
Supersedes data of 2000 Dec 22  
File under Integrated Circuits, IC24  
Philips Semiconductors  
Preliminary specification  
2-input EXCLUSIVE-OR gate  
74LVC1G86  
FEATURES  
DESCRIPTION  
Wide supply voltage range from 1.65 to 5.5 V  
High noise immunity  
The 74LVC1G86 is a high-performance, low-power,  
low-voltage, Si-gate CMOS device, superior to most  
advanced CMOS compatible TTL families.  
Complies with JEDEC standard:  
– JESD8-7 (1.65 to 1.95 V)  
Inputs can be driven from either 3.3 or 5 V devices. These  
features allow the use of these devices in a mixed  
3.3 and 5 V environment.  
– JESD8-5 (2.3 to 2.7 V)  
– JESD8B/JESD36 (2.7 to 3.6 V).  
• ±24 mA output drive (VCC = 3.0 V)  
CMOS low power consumption  
Latch-up performance 250 mA  
Direct interface with TTL levels  
SOT353 package.  
This device is fully specified for partial power-down  
applications using Ioff. The Ioff circuitry disables the output,  
preventing the damaging backflow current through the  
device when it is powered down.  
The 74LVC1G86 provides the 2-input EXCLUSIVE-OR  
function.  
QUICK REFERENCE DATA  
GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns.  
SYMBOL  
tPHL/tPLH  
PARAMETER  
CONDITIONS  
TYPICAL  
UNIT  
ns  
propagation delay A and B to Y  
VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ  
3.7  
2.5  
2.3  
1.9  
5
V
V
V
CC = 2.5 V; CL = 30 pF; RL = 500 Ω  
CC = 3.3 V; CL = 50 pF; RL = 500 Ω  
CC = 5.0 V; CL = 50 pF; RL = 500 Ω  
ns  
ns  
ns  
pF  
pF  
CI  
input capacitance  
CPD  
power dissipation capacitance per notes 1 and 2  
buffer  
25  
Notes  
1. CPD is used to determine the dynamic power dissipation (PD in µW).  
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in Volts.  
2. The condition is VI = GND to VCC  
.
2001 Apr 06  
2
Philips Semiconductors  
Preliminary specification  
2-input EXCLUSIVE-OR gate  
74LVC1G86  
FUNCTION TABLE  
See note 1.  
INPUTS  
OUTPUT  
Y
A
B
L
L
L
H
L
L
H
H
L
H
H
H
Note  
1. H = HIGH voltage level;  
L = LOW voltage level.  
ORDERING INFORMATION  
PACKAGE  
TYPE NUMBER  
TEMPERATURE  
PINS  
PACKAGE MATERIAL  
CODE  
MARKING  
RANGE  
74LVC1G86GW  
40 to +85 °C  
5
SC-88A  
plastic  
SOT353  
VH  
PINNING  
PIN  
SYMBOL  
DESCRIPTION  
1
2
3
4
5
B
A
data input B  
data input A  
ground (0 V)  
data output Y  
supply voltage  
GND  
Y
VCC  
handbook, halfpage  
B
A
1
2
3
5
4
V
Y
CC  
handbook, halfpage  
B
1
Y
4
A
86  
2
GND  
MNA038  
MNA037  
Fig.2 Logic symbol.  
Fig.1 Pin configuration.  
2001 Apr 06  
3
Philips Semiconductors  
Preliminary specification  
2-input EXCLUSIVE-OR gate  
74LVC1G86  
handbook, halfpage  
B
handbook, halfpage  
1
2
= 1  
4
Y
MNA039  
A
MNA040  
Fig.3 IEE/IEC logic symbol.  
Fig.4 Logic diagram.  
RECOMMENDED OPERATING CONDITIONS  
SYMBOL  
VCC  
PARAMETER  
supply voltage  
CONDITIONS  
MIN.  
1.65  
MAX.  
UNIT  
5.5  
5.5  
V
V
V
V
VI  
input voltage  
0
VO  
output voltage  
active mode  
0
VCC  
5.5  
+85  
20  
Power-down mode; VCC = 0 V  
0
Tamb  
tr, tf  
operating ambient temperature  
input rise and fall times  
40  
0
°C  
VCC = 1.65 to 2.7 V  
ns/V  
ns/V  
V
CC = 2.7 to 5.5 V  
0
10  
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).  
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT  
VCC supply voltage 0.5 +6.5  
V
IIK  
input diode current  
input voltage  
VI < 0  
note 1  
50  
mA  
V
VI  
0.5  
+6.5  
±50  
IOK  
VO  
output diode current  
output voltage  
VO > VCC or VO < 0  
mA  
V
active mode; notes 1 and 2  
0.5  
VCC + 0.5  
+6.5  
±50  
Power-down mode; notes 1 and 2 0.5  
V
IO  
output source or sink current  
VCC or GND current  
VO = 0 to VCC  
mA  
mA  
°C  
mW  
ICC, IGND  
±100  
+150  
200  
Tstg  
PD  
storage temperature  
65  
power dissipation per package  
for temperature range from  
40 to +85 °C; note 3  
Notes  
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.  
3. Above 55 °C the value of PD derates linearly with 2.5 mW/K.  
2001 Apr 06  
4
Philips Semiconductors  
Preliminary specification  
2-input EXCLUSIVE-OR gate  
74LVC1G86  
DC CHARACTERISTICS  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
TEST CONDITIONS  
Tamb (°C)  
SYMBOL  
PARAMETER  
40 to +85  
TYP.(1)  
UNIT  
OTHER  
VCC (V)  
MIN.  
MAX.  
VIH  
HIGH-level input  
voltage  
1.65 to 1.95 0.65 × VCC  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA  
2.3 to 2.7  
2.7 to 3.6  
4.5 to 5.5  
1.65 to 1.95  
2.3 to 2.7  
2.7 to 3.6  
4.5 to 5.5  
1.7  
2
0.7 × VCC  
VIL  
LOW-level input  
voltage  
0.35 × VCC  
0.7  
0.8  
0.3 × VCC  
VOL  
LOW-level output  
voltage  
VI = VIH or VIL; IO = 100 µA 1.65 to 5.5  
0.1  
0.45  
0.3  
0.4  
0.55  
0.55  
VI = VIH or VIL; IO = 4 mA  
VI = VIH or VIL; IO = 8 mA  
VI = VIH or VIL; IO = 12 mA  
VI = VIH or VIL; IO = 24 mA  
VI = VIH or VIL; IO = 32 mA  
1.65  
2.3  
2.7  
3.0  
4.5  
VOH  
HIGH-level output  
voltage  
VI = VIH or VIL; IO = 100 µA 1.65 to 5.5  
VCC 0.1  
VI = VIH or VIL; IO = 4 mA  
VI = VIH or VIL; IO = 8 mA  
1.65  
2.3  
1.2  
1.9  
2.2  
2.3  
3.8  
VI = VIH or VIL; IO = 12 mA 2.7  
VI = VIH or VIL; IO = 24 mA 3.0  
VI = VIH or VIL; IO = 32 mA 4.5  
ILI  
input leakage  
current  
VI = 5.5 V or GND  
3.6  
±0.1  
±5  
Ioff  
ICC  
power OFF leakage VI or VO = 5.5 V  
current  
0
±0.1  
±10  
µA  
µA  
quiescent supply  
current  
VI = VCC or GND; IO = 0  
5.5  
0.1  
10  
Note  
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.  
2001 Apr 06  
5
Philips Semiconductors  
Preliminary specification  
2-input EXCLUSIVE-OR gate  
74LVC1G86  
AC CHARACTERISTICS  
GND = 0 V; tr = tf 2.0 ns.  
TEST CONDITIONS  
WAVEFORMS VCC (V)  
Tamb (°C)  
SYMBOL  
PARAMETER  
40 to +85  
UNIT  
MIN.  
TYP.(1)  
MAX.  
9.9  
t
PHL/tPLH propagation delay A and B to Y see Figs 5 and 6 1.65 to 1.95 1.0  
3.7  
2.5  
2.8  
2.3  
1.9  
ns  
2.3 to 2.7  
2.7  
0.5  
0.5  
0.5  
0.5  
5.5  
5.8  
5.0  
4.0  
ns  
ns  
ns  
ns  
3.0 to 3.6  
4.5 to 5.5  
Note  
1. All typical values are measured at Tamb = 25 °C.  
AC WAVEFORMS  
handbook, halfpage  
A, B input  
V
M
t
t
PHL  
PLH  
V
Y output  
M
MNA041  
INPUT  
VCC  
VM  
VI  
tr = tf  
1.65 to 1.95 V  
2.3 to 2.7 V  
2.7 V  
0.5 × VCC VCC  
0.5 × VCC VCC  
2.0 ns  
2.0 ns  
2.5 ns  
2.5 ns  
2.5 ns  
1.5 V  
1.5 V  
2.7 V  
2.7 V  
3.0 to 3.6 V  
4.5 to 5.5 V  
0.5 × VCC VCC  
VOL and VOH are typical output voltage drop that occur with the output load.  
Fig.5 The inputs A and B to output Y propagation delay times.  
2001 Apr 06  
6
Philips Semiconductors  
Preliminary specification  
2-input EXCLUSIVE-OR gate  
74LVC1G86  
V
EXT  
V
CC  
R
L
V
V
O
I
PULSE  
GENERATOR  
D.U.T.  
C
R
R
L
L
T
MNA616  
VEXT  
tPLH/tPHL tPZH/tPHZ tPZL/tPLZ  
VCC  
VI  
VCC  
CL  
RL  
1.65 to 1.95 V  
2.3 to 2.7 V  
2.7 V  
30 pF  
30 pF  
50 pF  
50 pF  
50 pF  
1 kΩ  
open  
GND  
GND  
GND  
GND  
GND  
2 × VCC  
2 × VCC  
6 V  
VCC  
500 Ω  
500 Ω  
500 Ω  
500 Ω  
open  
open  
open  
open  
2.7 V  
2.7 V  
VCC  
3.0 to 3.6 V  
4.5 to 5.5 V  
6 V  
2 × VCC  
Definitions for test circuit:  
RL = Load resistor.  
CL = Load capacitance including jig and probe capacitance.  
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.  
Fig.6 Load circuitry for switching times.  
2001 Apr 06  
7
Philips Semiconductors  
Preliminary specification  
2-input EXCLUSIVE-OR gate  
74LVC1G86  
PACKAGE OUTLINE  
Plastic surface mounted package; 5 leads  
SOT353  
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
1
2
3
c
e
1
b
p
L
p
w
M B  
e
detail X  
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
1
(2)  
UNIT  
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max  
0.30  
0.20  
1.1  
0.8  
0.25  
0.10  
2.2  
1.8  
1.35  
1.15  
2.2  
2.0  
0.45  
0.15  
0.25  
0.15  
mm  
0.1  
1.3  
0.65  
0.2  
0.2  
0.1  
REFERENCES  
JEDEC  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
EIAJ  
SC-88A  
97-02-28  
SOT353  
2001 Apr 06  
8
Philips Semiconductors  
Preliminary specification  
2-input EXCLUSIVE-OR gate  
74LVC1G86  
SOLDERING  
If wave soldering is used the following conditions must be  
observed for optimal results:  
Introduction to soldering surface mount packages  
Use a double-wave soldering method comprising a  
turbulent wave with high upward pressure followed by a  
smooth laminar wave.  
This text gives a very brief insight to a complex technology.  
A more in-depth account of soldering ICs can be found in  
our “Data Handbook IC26; Integrated Circuit Packages”  
(document order number 9398 652 90011).  
For packages with leads on two sides and a pitch (e):  
– larger than or equal to 1.27 mm, the footprint  
longitudinal axis is preferred to be parallel to the  
transport direction of the printed-circuit board;  
There is no soldering method that is ideal for all surface  
mount IC packages. Wave soldering can still be used for  
certain surface mount ICs, but it is not suitable for fine pitch  
SMDs. In these situations reflow soldering is  
recommended.  
– smaller than 1.27 mm, the footprint longitudinal axis  
must be parallel to the transport direction of the  
printed-circuit board.  
Reflow soldering  
The footprint must incorporate solder thieves at the  
downstream end.  
Reflow soldering requires solder paste (a suspension of  
fine solder particles, flux and binding agent) to be applied  
to the printed-circuit board by screen printing, stencilling or  
pressure-syringe dispensing before package placement.  
For packages with leads on four sides, the footprint must  
be placed at a 45° angle to the transport direction of the  
printed-circuit board. The footprint must incorporate  
solder thieves downstream and at the side corners.  
Several methods exist for reflowing; for example,  
convection or convection/infrared heating in a conveyor  
type oven. Throughput times (preheating, soldering and  
cooling) vary between 100 and 200 seconds depending  
on heating method.  
During placement and before soldering, the package must  
be fixed with a droplet of adhesive. The adhesive can be  
applied by screen printing, pin transfer or syringe  
dispensing. The package can be soldered after the  
adhesive is cured.  
Typical reflow peak temperatures range from  
215 to 250 °C. The top-surface temperature of the  
packages should preferable be kept below 220 °C for  
thick/large packages, and below 235 °C for small/thin  
packages.  
Typical dwell time is 4 seconds at 250 °C.  
A mildly-activated flux will eliminate the need for removal  
of corrosive residues in most applications.  
Manual soldering  
Wave soldering  
Fix the component by first soldering two  
diagonally-opposite end leads. Use a low voltage (24 V or  
less) soldering iron applied to the flat part of the lead.  
Contact time must be limited to 10 seconds at up to  
300 °C.  
Conventional single wave soldering is not recommended  
for surface mount devices (SMDs) or printed-circuit boards  
with a high component density, as solder bridging and  
non-wetting can present major problems.  
When using a dedicated tool, all other leads can be  
soldered in one operation within 2 to 5 seconds between  
270 and 320 °C.  
To overcome these problems the double-wave soldering  
method was specifically developed.  
2001 Apr 06  
9
Philips Semiconductors  
Preliminary specification  
2-input EXCLUSIVE-OR gate  
74LVC1G86  
Suitability of surface mount IC packages for wave and reflow soldering methods  
SOLDERING METHOD  
PACKAGE  
BGA, LFBGA, SQFP, TFBGA  
WAVE  
not suitable  
REFLOW(1)  
suitable  
suitable  
suitable  
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS  
PLCC(3), SO, SOJ  
not suitable(2)  
suitable  
LQFP, QFP, TQFP  
not recommended(3)(4) suitable  
not recommended(5)  
suitable  
SSOP, TSSOP, VSO  
Notes  
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum  
temperature (with respect to time) and body size of the package, there is a risk that internal or external package  
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the  
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.  
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink  
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).  
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.  
The package footprint must incorporate solder thieves downstream and at the side corners.  
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;  
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.  
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is  
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.  
2001 Apr 06  
10  
Philips Semiconductors  
Preliminary specification  
2-input EXCLUSIVE-OR gate  
74LVC1G86  
DATA SHEET STATUS  
PRODUCT  
DATA SHEET STATUS(1)  
STATUS(2)  
DEFINITIONS  
Objective data  
Development This data sheet contains data from the objective specification for product  
development. Philips Semiconductors reserves the right to change the  
specification in any manner without notice.  
Preliminary data  
Qualification  
This data sheet contains data from the preliminary specification.  
Supplementary data will be published at a later date. Philips  
Semiconductors reserves the right to change the specification without  
notice, in order to improve the design and supply the best possible  
product.  
Product data  
Production  
This data sheet contains data from the product specification. Philips  
Semiconductors reserves the right to make changes at any time in order  
to improve the design, manufacturing and supply. Changes will be  
communicated according to the Customer Product/Process Change  
Notification (CPCN) procedure SNW-SQ-650A.  
Notes  
1. Please consult the most recently issued data sheet before initiating or completing a design.  
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was  
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.  
DEFINITIONS  
DISCLAIMERS  
Short-form specification  
The data in a short-form  
Life support applications  
These products are not  
specification is extracted from a full data sheet with the  
same type number and title. For detailed information see  
the relevant data sheet or data handbook.  
designed for use in life support appliances, devices, or  
systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips  
Semiconductors customers using or selling these products  
for use in such applications do so at their own risk and  
agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
Limiting values definition Limiting values given are in  
accordance with the Absolute Maximum Rating System  
(IEC 60134). Stress above one or more of the limiting  
values may cause permanent damage to the device.  
These are stress ratings only and operation of the device  
at these or at any other conditions above those given in the  
Characteristics sections of the specification is not implied.  
Exposure to limiting values for extended periods may  
affect device reliability.  
Right to make changes  
Philips Semiconductors  
reserves the right to make changes, without notice, in the  
products, including circuits, standard cells, and/or  
software, described or contained herein in order to  
improve design and/or performance. Philips  
Semiconductors assumes no responsibility or liability for  
the use of any of these products, conveys no licence or title  
under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that  
these products are free from patent, copyright, or mask  
work right infringement, unless otherwise specified.  
Application information  
Applications that are  
described herein for any of these products are for  
illustrative purposes only. Philips Semiconductors make  
no representation or warranty that such applications will be  
suitable for the specified use without further testing or  
modification.  
2001 Apr 06  
11  
Philips Semiconductors – a worldwide company  
Argentina: see South America  
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,  
Tel. +31 40 27 82785, Fax. +31 40 27 88399  
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,  
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139  
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,  
Tel. +64 9 849 4160, Fax. +64 9 849 7811  
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,  
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210  
Norway: Box 1, Manglerud 0612, OSLO,  
Tel. +47 22 74 8000, Fax. +47 22 74 8341  
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,  
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773  
Pakistan: see Singapore  
Belgium: see The Netherlands  
Brazil: see South America  
Philippines: Philips Semiconductors Philippines Inc.,  
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,  
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474  
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,  
51 James Bourchier Blvd., 1407 SOFIA,  
Tel. +359 2 68 9211, Fax. +359 2 68 9102  
Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,  
Tel. +48 22 5710 000, Fax. +48 22 5710 001  
Portugal: see Spain  
Romania: see Italy  
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,  
Tel. +1 800 234 7381, Fax. +1 800 943 0087  
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,  
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,  
Tel. +852 2319 7888, Fax. +852 2319 7700  
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,  
Tel. +7 095 755 6918, Fax. +7 095 755 6919  
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,  
Colombia: see South America  
Czech Republic: see Austria  
Tel. +65 350 2538, Fax. +65 251 6500  
Slovakia: see Austria  
Slovenia: see Italy  
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,  
Tel. +45 33 29 3333, Fax. +45 33 29 3905  
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,  
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,  
Tel. +27 11 471 5401, Fax. +27 11 471 5398  
Finland: Sinikalliontie 3, FIN-02630 ESPOO,  
Tel. +358 9 615 800, Fax. +358 9 6158 0920  
France: 7 - 9 Rue du Mont Valérien, BP317, 92156 SURESNES Cedex,  
Tel. +33 1 4728 6600, Fax. +33 1 4728 6638  
South America: Al. Vicente Pinzon, 173, 6th floor,  
04547-130 SÃO PAULO, SP, Brazil,  
Tel. +55 11 821 2333, Fax. +55 11 821 2382  
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,  
Tel. +49 40 2353 60, Fax. +49 40 2353 6300  
Spain: Balmes 22, 08007 BARCELONA,  
Tel. +34 93 301 6312, Fax. +34 93 301 4107  
Hungary: Philips Hungary Ltd., H-1119 Budapest, Fehervari ut 84/A,  
Tel: +36 1 382 1700, Fax: +36 1 382 1800  
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,  
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745  
India: Philips INDIA Ltd, Band Box Building, 2nd floor,  
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,  
Tel. +91 22 493 8541, Fax. +91 22 493 0966  
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,  
Tel. +41 1 488 2741 Fax. +41 1 488 3263  
Indonesia: PT Philips Development Corporation, Semiconductors Division,  
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,  
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080  
Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,  
TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874  
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,  
60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,  
Tel. +66 2 361 7910, Fax. +66 2 398 3447  
Ireland: Newstead, Clonskeagh, DUBLIN 14,  
Tel. +353 1 7640 000, Fax. +353 1 7640 200  
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,  
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,  
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007  
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813  
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),  
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,  
Tel. +39 039 203 6838, Fax +39 039 203 6800  
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461  
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,  
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,  
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057  
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421  
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,  
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,  
Tel. +82 2 709 1412, Fax. +82 2 709 1415  
Tel. +1 800 234 7381, Fax. +1 800 943 0087  
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,  
Tel. +60 3 750 5214, Fax. +60 3 757 4880  
Uruguay: see South America  
Vietnam: see Singapore  
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,  
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087  
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,  
Tel. +381 11 3341 299, Fax.+381 11 3342 553  
Middle East: see Italy  
For all other countries apply to: Philips Semiconductors,  
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,  
The Netherlands, Fax. +31 40 27 24825  
Internet: http://www.semiconductors.philips.com  
72  
SCA  
© Philips Electronics N.V. 2001  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
613508/02/pp12  
Date of release: 2001 Apr 06  
Document order number: 9397 750 07989  

相关型号:

74LVC1G86GW-Q100

2-input EXCLUSIVE-OR gate
NEXPERIA

74LVC1G86GW-Q100H

74LVC1G86-Q100 - 2-input EXCLUSIVE-OR gate TSSOP 5-Pin
NXP

74LVC1G86GX

2-input EXCLUSIVE-OR gateProduction
NEXPERIA

74LVC1G86SE

SINGLE 2 INPUT EXCLUSIVE OR GATE
DIODES

74LVC1G86SE-7

SINGLE 2 INPUT EXCLUSIVE OR GATE
DIODES

74LVC1G86W5

SINGLE 2 INPUT EXCLUSIVE OR GATE
DIODES

74LVC1G86W5-7

SINGLE 2 INPUT EXCLUSIVE OR GATE
DIODES

74LVC1G86Z-7

SINGLE 2 INPUT EXCLUSIVE OR GATE
DIODES

74LVC1G86_12

SINGLE 2 INPUT EXCLUSIVE OR GATE
DIODES

74LVC1G97

CONFIGURABLE MULTIPLE-FUNCTION GATE
DIODES

74LVC1G97DW

CONFIGURABLE MULTIPLE-FUNCTION GATE
DIODES

74LVC1G97DW-7

CONFIGURABLE MULTIPLE-FUNCTION GATE
DIODES