74LVC2G02DP [NXP]

Dual 2-input NOR gate; 双路2输入或非门


型号：	74LVC2G02DP
厂家：	NXP
描述：	Dual 2-input NOR gate 双路2输入或非门逻辑集成电路光电二极管
文件：	总15页 (文件大小：88K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74LVC2G02

Dual 2-input NOR gate

Rev. 05 — 4 September 2007

Product data sheet

1. General description

The 74LVC2G02 provides a 2-input NOR gate function.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in a mixed 3.3 V and 5 V environment.

This device is fully speciﬁed for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing the damaging backﬂow current through the device

when it is powered down.

2. Features

■ Wide supply voltage range from 1.65 V to 5.5 V

■ 5 V tolerant outputs for interfacing with 5 V logic

■ High noise immunity

■ ±24 mA output drive (V_CC= 3.0 V)

■ CMOS low power consumption

■ Complies with JEDEC standard:

◆ JESD8-7 (1.65 V to 1.95 V)

◆ JESD8-5 (2.3 V to 2.7 V)

◆ JESD8-B/JESD36 (2.7 V to 3.6 V)

■ Latch-up performance exceeds 250 mA

■ Direct interface with TTL levels

■ Inputs accept voltages up to 5 V

■ ESD protection:

◆ HBM EIA/JESD22-A114E exceeds 2000 V

◆ MM EIA/JESD22-A115-A exceeds 200 V

■ Multiple package options

■ Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C

74LVC2G02

NXP Semiconductors

Dual 2-input NOR gate

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVC2G02DP

−40 °C to +125 °C

TSSOP8

plastic thin shrink small outline package; 8 leads;

body width 3 mm; lead length 0.5 mm

SOT505-2

74LVC2G02DC −40 °C to +125 °C

74LVC2G02GT −40 °C to +125 °C

VSSOP8

XSON8

XQFN8

plastic very thin shrink small outline package; 8 leads; SOT765-1

body width 2.3 mm

plastic extremely thin small outline package; no leads; SOT833-1

8 terminals; body 1 × 1.95 × 0.5 mm

74LVC2G02GM −40 °C to +125 °C

plastic extremely thin quad ﬂat package; no leads;

SOT902-1

8 terminals; body 1.6 × 1.6 × 0.5 mm

4. Marking

Table 2.

Marking

Type number

74LVC2G02DP

74LVC2G02DC

74LVC2G02GT

74LVC2G02GM

Marking code

V02

5. Functional diagram

≥ 1

mna716

mna717

Fig 1. Logic symbol

Fig 2. IEC logic symbol

mna105

Fig 3. Logic diagram (one gate)

74LVC2G02_5

Product data sheet

Rev. 05 — 4 September 2007

2 of 15

74LVC2G02

NXP Semiconductors

Dual 2-input NOR gate

6. Pinning information

6.1 Pinning

74LVC2G02

GND

001aab642

Fig 4. Pin conﬁguration TSSOP8 and VSSOP8

74LVC2G02

terminal 1

index area

74LVC2G02

GND

001aae971

001aab643

Transparent top view

Fig 5. Pin conﬁguration XSON8

Fig 6. Pin conﬁguration XQFN8

6.2 Pin description

Table 3.

Symbol

Pin description

Description

TSSOP8, VSSOP8

XSON8

XQFN8

data input

data output

ground (0 V)

data input

GND

data input

data output

supply voltage

V_CC

74LVC2G02_5

Product data sheet

Rev. 05 — 4 September 2007

3 of 15

74LVC2G02

NXP Semiconductors

Dual 2-input NOR gate

7. Functional description

Table 4.

Function table^[1]

Input

Output

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care

8. Limiting values

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

V_I

Parameter

Conditions

Min

−0.5

−50

Max

+6.5

V_CC+ 0.5

+6.5

Unit

supply voltage

input voltage

output voltage

[1]

V_O

Active mode

[1][2]

Power-down mode

V_I< 0 V

I_IK

input clamping current

output clamping current

output current

°C

I_OK

I_O

V_O< 0 V or V_O> V_CC

V_O= 0 V to V_CC

±50

100

I_CC

I_GND

T_stg

P_tot

supply current

ground current

−100

−65

storage temperature

total power dissipation

+150

300

[3]

T_amb= −40 °C to +125 °C

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] When V_CC= 0 V (Power-down mode), the output voltage can be 5.5 V in normal condition.

[3] For TSSOP8 package: above 55 °C the value of P_totderates linearly with 2.5 mW/K.

For VSSOP8 package: above 110 °C the value of P_totderates linearly with 8 mW/K.

For XSON8 and XQFN packages: above 45 °C the value of P_totderates linearly with 2.4 mW/K.

9. Recommended operating conditions

Table 6.

Symbol

V_CC

Recommended operating conditions

Parameter

Conditions

Min

Typ

Max

5.5

Unit

supply voltage

input voltage

output voltage

1.65

V_I

5.5

V_O

Active mode

V_CC

5.5

Power-down mode

T_amb

ambient temperature

−40

+125

°C

ns/V

∆t/∆V

input transition rise and fall

rate

V_CC= 1.65 V to 2.7 V

V_CC= 2.7 V to 5.5 V

74LVC2G02_5

Product data sheet

Rev. 05 — 4 September 2007

4 of 15

74LVC2G02

NXP Semiconductors

Dual 2-input NOR gate

10. Static characteristics

Table 7.

Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Typ

Max

Unit

T_amb= −40 °C to +85 °C^[1]

V_IH

HIGH-level input voltage V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

0.65 × V_CC

1.7

V_CC= 2.7 V to 3.6 V

2.0

V_CC= 4.5 V to 5.5 V

0.7 × V_CC

V_IL

LOW-level input voltage

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_CC= 4.5 V to 5.5 V

0.35 × V_CC

0.7

0.8

0.3 × V_CC

V_OH

HIGH-level output voltage V_I= V_IHor V_IL

I_O= −100 µA; V_CC= 1.65 V to 5.5 V

_CC− 0.1

I_O= −4 mA; V_CC= 1.65 V

I_O= −8 mA; V_CC= 2.3 V

I_O= −12 mA; V_CC= 2.7 V

I_O= −24 mA; V_CC= 3.0 V

I_O= −32 mA; V_CC= 4.5 V

1.2

1.9

2.2

2.3

3.8

1.53

2.13

2.50

2.60

4.10

V_OL

LOW-level output voltage V_I= V_IHor V_IL

I_O= 100 µA; V_CC= 1.65 V to 5.5 V

I_O= 4 mA; V_CC= 1.65 V

0.1

0.08 0.45

0.14 0.3

0.19 0.4

0.37 0.55

0.43 0.55

±0.1 ±5

I_O= 8 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

I_O= 32 mA; V_CC= 4.5 V

I_I

input leakage current

V_I= 5.5 V or GND; V_CC= 0 V to 5.5 V

µA

I_OFF

I_CC

power-off leakage current V_Ior V_O= 5.5 V; V_CC= 0 V

supply current V_I= 5.5 V or GND;

_CC= 1.65 V to 5.5 V; I_O= 0 A

additional supply current per pin; V_I= V_CC− 0.6 V; I_O= 0 A;

_CC= 2.3 V to 5.5 V

±0.1 ±10

0.1

500

∆I_CC

µA

C_I

input capacitance

2.5

T_amb= −40 °C to +125 °C

V_IH

HIGH-level input voltage V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

0.65 × V_CC

1.7

V_CC= 2.7 V to 3.6 V

2.0

V_CC= 4.5 V to 5.5 V

0.7 × V_CC

V_IL

LOW-level input voltage

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_CC= 4.5 V to 5.5 V

0.35 × V_CC

0.7

0.8

0.3 × V_CC

74LVC2G02_5

Product data sheet

Rev. 05 — 4 September 2007

5 of 15

74LVC2G02

NXP Semiconductors

Dual 2-input NOR gate

Table 7.

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

V_OHHIGH-level output voltage V_I= V_IHor V_IL

I_O= −100 µA; V_CC= 1.65 V to 5.5 V

Conditions

Min

Typ

Max

Unit

V_CC− 0.1

I_O= −4 mA; V_CC= 1.65 V

I_O= −8 mA; V_CC= 2.3 V

I_O= −12 mA; V_CC= 2.7 V

I_O= −24 mA; V_CC= 3.0 V

I_O= −32 mA; V_CC= 4.5 V

0.95

1.7

1.9

2.0

3.4

V_OL

LOW-level output voltage V_I= V_IHor V_IL

I_O= 100 µA; V_CC= 1.65 V to 5.5 V

I_O= 4 mA; V_CC= 1.65 V

0.1

0.70

0.45

0.60

0.80

±20

I_O= 8 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

I_O= 32 mA; V_CC= 4.5 V

I_I

input leakage current

V_I= 5.5 V or GND; V_CC= 0 V to 5.5 V

µA

I_OFF

I_CC

power-off leakage current V_Ior V_O= 5.5 V; V_CC= 0 V

supply current V_I= 5.5 V or GND;

_CC= 1.65 V to 5.5 V; I_O= 0 A

additional supply current per pin; V_I= V_CC− 0.6 V; I_O= 0 A;

_CC= 2.3 V to 5.5 V

∆I_CC

5000

µA

[1] All typical values are measured at T_amb= 25 °C.

74LVC2G02_5

Product data sheet

Rev. 05 — 4 September 2007

6 of 15

74LVC2G02

NXP Semiconductors

Dual 2-input NOR gate

11. Dynamic characteristics

Table 8.

Dynamic characteristics

Voltages are referenced to GND (ground 0 V); for test circuit see Figure 8.

Symbol Parameter Conditions −40 °C to +85 °C

−40 °C to +125 °C Unit

Min

Typ^[1]

Max

Min

Max

[2]

t_pd

propagation delay nA, nB to nY; see Figure 7

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

1.2

0.8

0.6

3.8

2.4

3.2

2.4

1.8

8.9

5.4

6.0

4.9

4.3

1.2

0.8

0.6

11.2

6.8

7.5

6.2

5.5

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

[3]

C_PD

power dissipation per gate; V_I= GND to V_CC

capacitance

[1] Typical values are measured at nominal V_CCand at T_amb= 25 °C.

[2] t_pdis the same as t_PLHand t_PHL

[3] C_PDis used to determine the dynamic power dissipation (P_Din µW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

Σ(C_L× V_CC²× f_o) = sum of outputs.

12. Waveforms

nA, nB input

GND

PLH

PHL

nY output

001aae972

Measurement points are given in Table 9.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 7. Input (nA, nB) to output (nY) propagation delays

74LVC2G02_5

Product data sheet

Rev. 05 — 4 September 2007

7 of 15

74LVC2G02

NXP Semiconductors

Dual 2-input NOR gate

Table 9.

Measurement points

Supply voltage

V_CC

Input

V_M

Output

V_M

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

0.5V_CC

1.5 V

0.5V_CC

1.5 V

3.0 V to 3.6 V

4.5 V to 5.5 V

1.5 V

0.5V_CC

90 %

negative

pulse

10 %

0 V

90 %

positive

pulse

10 %

0 V

EXT

PULSE

GENERATOR

DUT

001aae235

Test data is given in Table 10.

Deﬁnitions for test circuit:

R_L= Load resistor

C_L= Load capacitance including jig and probe capacitance

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator

V_EXT= Test voltage for switching times

Fig 8. Load circuitry for switching times

Table 10. Test data

Supply voltage

V_CC

Input

V_I

Load

C_L

V_EXT

t_r, t_f

R_L

t_PLH, t_PHL

open

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

V_CC

2.7 V

V_CC

≤ 2.0 ns

≤ 2.5 ns

30 pF

50 pF

1 kΩ

500 Ω

open

3.0 V to 3.6 V

4.5 V to 5.5 V

open

74LVC2G02_5

Product data sheet

Rev. 05 — 4 September 2007

8 of 15

74LVC2G02

NXP Semiconductors

Dual 2-input NOR gate

13. Package outline

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm

SOT505-2

(A )

pin 1 index

detail X

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

UNIT

max.

0.15

0.00

0.95

0.75

0.38

0.22

0.18

0.08

3.1

2.9

3.1

2.9

4.1

3.9

0.47

0.33

0.70

0.35

8°

0°

1.1

0.65

0.25

0.5

0.2

0.13

0.1

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-01-16

SOT505-2

- - -

Fig 9. Package outline SOT505-2 (TSSOP8)

74LVC2G02_5

Product data sheet

Rev. 05 — 4 September 2007

9 of 15

74LVC2G02

NXP Semiconductors

Dual 2-input NOR gate

VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm

SOT765-1

(A )

pin 1 index

detail X

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

(2)

(1)

UNIT

max.

0.15

0.00

0.85

0.60

0.27

0.17

0.23

0.08

2.1

1.9

2.4

2.2

3.2

3.0

0.40

0.15

0.21

0.19

0.4

0.1

8°

0°

0.5

0.12

0.4

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-06-07

SOT765-1

MO-187

Fig 10. Package outline SOT765-1 (VSSOP8)

74LVC2G02_5

Product data sheet

Rev. 05 — 4 September 2007

10 of 15

74LVC2G02

NXP Semiconductors

Dual 2-input NOR gate

XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm

SOT833-1

4×

(2)

8×

(2)

terminal 1

index area

2 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

UNIT

max max

0.25

0.17

2.0

1.9

1.05

0.95

0.35 0.40

0.27 0.32

0.5 0.04

0.6

0.5

Notes

1. Including plating thickness.

2. Can be visible in some manufacturing processes.

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

- - -

04-07-22

04-11-09

SOT833-1

- - -

MO-252

Fig 11. Package outline SOT833-1 (XSON8)

74LVC2G02_5

Product data sheet

Rev. 05 — 4 September 2007

11 of 15

74LVC2G02

NXP Semiconductors

Dual 2-input NOR gate

XQFN8: plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm

SOT902-1

terminal 1

index area

detail X

metal area

not for soldering

terminal 1

index area

2 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT

max

0.05 0.25 1.65 1.65

0.00 0.15 1.55 1.55

0.35 0.15

0.25 0.05

0.5

0.55

0.5

0.1

0.05 0.05 0.05

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

MO-255

JEITA

05-11-16

05-11-25

SOT902-1

- - -

Fig 12. Package outline SOT902-1 (XQFN8)

74LVC2G02_5

Product data sheet

Rev. 05 — 4 September 2007

12 of 15

74LVC2G02

NXP Semiconductors

Dual 2-input NOR gate

14. Abbreviations

Table 11. Abbreviations

Acronym

CMOS

DUT

Description

Complementary Metal Oxide Semiconductor

Device Under Test

ESD

ElectroStatic Discharge

Human Body Model

HBM

Machine Model

TTL

Transistor-Transistor Logic

15. Revision history

Table 12. Revision history

Document ID

74LVC2G02_5

Modiﬁcations:

Release date

20070904

Data sheet status

Change notice

Supersedes

Product data sheet

74LVC2G02_4

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• In Section 10 “Static characteristics”, changed conditions for input leakage and supply

current.

74LVC2G02_4

74LVC2G02_3

74LVC2G02_2

74LVC2G02_1

20060515

20050201

20040915

20031015

Product data sheet

Product speciﬁcation

74LVC2G02_3

74LVC2G02_2

74LVC2G02_1

74LVC2G02_5

Product data sheet

Rev. 05 — 4 September 2007

13 of 15

74LVC2G02

NXP Semiconductors

Dual 2-input NOR gate

16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of a NXP Semiconductors product can reasonably be expected to

16.2 Deﬁnitions

result in personal injury, death or severe property or environmental damage.

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

17. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

74LVC2G02_5

Product data sheet

Rev. 05 — 4 September 2007

14 of 15

74LVC2G02

NXP Semiconductors

Dual 2-input NOR gate

18. Contents

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

Functional description . . . . . . . . . . . . . . . . . . . 4

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

Recommended operating conditions. . . . . . . . 4

Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13

Legal information. . . . . . . . . . . . . . . . . . . . . . . 14

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

16.1

16.2

16.3

16.4

Contact information. . . . . . . . . . . . . . . . . . . . . 14

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 4 September 2007

Document identifier: 74LVC2G02_5

74LVC2G02DP [NXP]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E