74LVC2G66_08 [NXP]
Bilateral switch; 双向开关
| 型号： | 74LVC2G66_08 |
| 厂家： | 
NXP |
| 描述： | Bilateral switch |
| 文件： | 总24页 (文件大小：140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC2G66
Bilateral switch
Rev. 04 — 1 July 2008
Product data sheet
1. General description
The 74LVC2G66 is a low-power, low-voltage, high-speed Si-gate CMOS device.
The 74LVC2G66 provides two single pole, single-throw analog switch functions. Each
switch has two input/output terminals (nY and nZ) and an active HIGH enable input (nE).
When nE is LOW, the analog switch is turned off.
Schmitt-trigger action at the enable inputs makes the circuit tolerant of slower input rise
and fall times across the entire VCC range from 1.65 V to 5.5 V.
2. Features
I Wide supply voltage range from 1.65 V to 5.5 V
I Very low ON resistance:
N 7.5 Ω (typical) at VCC = 2.7 V
N 6.5 Ω (typical) at VCC = 3.3 V
N 6 Ω (typical) at VCC = 5 V
I Switch current capability of 32 mA
I High noise immunity
I CMOS low power consumption
I TTL interface compatibility at 3.3 V
I Latch-up performance meets requirements of JESD78 Class I
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Enable input accepts voltages up to 5.5 V
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
74LVC2G66
NXP Semiconductors
Bilateral switch
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC2G66DP
74LVC2G66DC
74LVC2G66GT
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
SOT765-1
SOT833-1
SOT996-2
SOT902-1
VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
XSON8
plastic extremely thin small outline package; no leads;
8 terminals; body 1 × 1.95 × 0.5 mm
74LVC2G66GD −40 °C to +125 °C
74LVC2G66GM −40 °C to +125 °C
XSON8U plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 × 2 × 0.5 mm
XQFN8U plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm
4. Marking
Table 2.
Marking codes
Type number
74LVC2G66DP
74LVC2G66DC
74LVC2G66GT
74LVC2G66GD
74LVC2G66GM
Marking code
V66
V66
V66
V66
V66
5. Functional diagram
1
1
#
X1
1
1
#
X1
001aah807
001aah808
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74LVC2G66_4
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Product data sheet
Rev. 04 — 1 July 2008
2 of 24
74LVC2G66
NXP Semiconductors
Bilateral switch
Z
Y
E
V
CC
mna658
Fig 3. Logic diagram (one switch)
6. Pinning information
6.1 Pinning
74LVC2G66
1Y
1Z
1
2
3
4
8
7
6
5
V
CC
1E
2Z
2Y
74LVC2G66
2E
V
1Y
1Z
1
2
3
4
8
7
6
5
CC
1E
2Z
2Y
GND
2E
GND
001aaf567
Transparent top view
001aaa529
Fig 4. Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
Fig 5. Pin configuration SOT833-1 (XSON8)
74LVC2G66
terminal 1
index area
1E
1
7
6
5
1Y
1Z
2E
74LVC2G66
1Y
1Z
1
2
3
4
8
7
6
5
V
CC
2Z
2Y
2
3
1E
2Z
2Y
2E
GND
001aaf568
001aai248
Transparent top view
Transparent top view
Fig 6. Pin configuration SOT996-2 (XSON8U)
Fig 7. Pin configuration SOT902-1 (XQFN8U)
74LVC2G66_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 1 July 2008
3 of 24
74LVC2G66
NXP Semiconductors
Bilateral switch
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SOT505-2, SOT765-1,
SOT902-1
SOT833-1 and SOT996-2
1Y
1
2
3
4
5
6
7
8
7
6
5
4
3
2
1
8
independent input or output
independent input or output
enable input (active HIGH)
ground (0 V)
1Z
2E
GND
2Y
independent input or output
independent input or output
enable input (active HIGH)
supply voltage
2Z
1E
VCC
7. Functional description
Table 4.
Function table[1]
Input nE
Switch
L
OFF-state
ON-state
H
[1] H = HIGH voltage level; L = LOW voltage level.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
−0.5
−0.5
−50
-
Max
+6.5
+6.5
-
Unit
V
supply voltage
[1]
[2]
input voltage
V
IIK
input clamping current
switch clamping current
switch voltage
VI < −0.5 V or VI > VCC + 0.5 V
VI < −0.5 V or VI > VCC + 0.5 V
enable and disable mode
VSW > −0.5 V or
mA
mA
V
ISK
±50
VSW
ISW
−0.5
-
VCC + 0.5
±50
switch current
mA
VSW < VCC + 0.5 V
ICC
supply current
-
100
-
mA
mA
°C
IGND
Tstg
Ptot
ground current
−100
−65
-
storage temperature
total power dissipation
+150
250
[3]
Tamb = −40 °C to +125 °C
mW
[1] The minimum input voltage rating may be exceeded if the input current rating is observed.
[2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed.
[3] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
74LVC2G66_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 1 July 2008
4 of 24
74LVC2G66
NXP Semiconductors
Bilateral switch
9. Recommended operating conditions
Table 6.
Symbol
VCC
Operating conditions
Parameter
Conditions
Min
Max
5.5
Unit
V
supply voltage
1.65
VI
input voltage
0
5.5
V
[1][2]
VSW
switch voltage
0
VCC
+125
20
V
Tamb
ambient temperature
input transition rise and fall rate
−40
°C
[3]
[3]
∆t/∆V
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
-
-
ns/V
ns/V
10
[1] To avoid sinking GND current from terminal nZ when switch current flows in terminal nY, the voltage drop across the bidirectional switch
must not exceed 0.4 V. If the switch current flows into terminal nZ, no GND current will flow from terminal nY. In this case, there is no
limit for the voltage drop across the switch.
[2] For overvoltage tolerant switch voltage capability, refer to 74LVCV2G66.
[3] Applies to control signal levels.
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
VIH
HIGH-level
input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
pin nE; VI = 5.5 V or GND;
0.65 × VCC
-
-
0.65 × VCC
-
V
V
V
V
V
V
V
V
µA
1.7
-
-
1.7
-
2.0
-
-
2.0
-
-
0.7 × VCC
-
-
0.35 × VCC
0.7
0.7 × VCC
VIL
LOW-level
input voltage
-
-
-
-
-
-
-
-
-
-
-
0.35 × VCC
0.7
-
-
-
0.8
0.8
0.3 × VCC
±5
0.3 × VCC
±100
[2]
[2]
II
input leakage
current
±0.1
V
CC = 0 V to 5.5 V
VI = VIH or VIL;
CC = 5.5 V; see Figure 8
IS(OFF)
OFF-state
leakage
current
-
-
-
±0.1
±0.1
0.1
±5
±5
10
-
-
-
±200
±200
200
µA
µA
µA
V
[2]
[2]
IS(ON)
ON-state
leakage
current
VI = VIH or VIL;
CC = 5.5 V; see Figure 9
V
ICC
supply current VI = 5.5 V or GND;
SW = GND or VCC
IO = 0 A;
CC = 1.65 V to 5.5 V
V
;
V
[2]
∆ICC
additional
supply current
pin nE; VI = VCC − 0.6 V;
SW = GND or VCC
IO = 0 A; VCC = 5.5 V
-
5
500
-
5000
µA
V
;
74LVC2G66_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 1 July 2008
5 of 24
74LVC2G66
NXP Semiconductors
Bilateral switch
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
CI
input
capacitance
-
-
-
2.0
-
-
-
-
-
pF
pF
pF
CS(OFF) OFF-state
capacitance
5.0
9.5
-
-
-
-
CS(ON)
ON-state
capacitance
[1] All typical values are measured at Tamb = 25 °C.
[2] These typical values are measured at VCC = 3.3 V.
10.1 Test circuits
V
V
CC
CC
E
Z
E
Z
V
V
IH
IL
Y
Y
I
I
I
S
S
S
GND
GND
V
V
V
V
O
I
O
I
001aag488
001aag489
VI = VCC or GND and VO = GND or VCC
.
VI = VCC or GND and VO = open circuit.
Fig 8. Test circuit for measuring OFF-state leakage
current
Fig 9. Test circuit for measuring ON-state leakage
current
74LVC2G66_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 1 July 2008
6 of 24
74LVC2G66
NXP Semiconductors
Bilateral switch
10.2 ON resistance
Table 8.
ON resistance
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 11 to Figure 16.
Symbol Parameter
Conditions
−40 °C to +85 °C
Min
Typ[1] Max
−40 °C to +125 °C Unit
Min
Max
RON(peak) ON resistance
(peak)
VI = GND to VCC; see Figure 10
ISW = 4 mA;
-
34.0
130
-
195
Ω
V
CC = 1.65 V to 1.95 V
ISW = 8 mA; VCC = 2.3 V to 2.7 V
ISW = 12 mA; VCC = 2.7 V
ISW = 24 mA; VCC = 3.0 V to 3.6 V
ISW = 32 mA; VCC = 4.5 V to 5.5 V
VI = GND; see Figure 10
-
-
-
-
12.0
10.4
7.8
30
25
20
15
-
-
-
-
45
38
30
23
Ω
Ω
Ω
Ω
6.2
RON(rail) ON resistance
(rail)
ISW = 4 mA;
-
8.2
18
-
27
Ω
V
CC = 1.65 V to 1.95 V
ISW = 8 mA; VCC = 2.3 V to 2.7 V
ISW = 12 mA; VCC = 2.7 V
ISW = 24 mA; VCC = 3.0 V to 3.6 V
ISW = 32 mA; VCC = 4.5 V to 5.5 V
VI = VCC; see Figure 10
-
-
-
-
7.1
6.9
6.5
5.8
16
14
12
10
-
-
-
-
24
21
18
15
Ω
Ω
Ω
Ω
ISW = 4 mA;
-
10.4
30
-
45
Ω
V
CC = 1.65 V to 1.95 V
ISW = 8 mA; VCC = 2.3 V to 2.7 V
ISW = 12 mA; VCC = 2.7 V
ISW = 24 mA; VCC = 3.0 V to 3.6 V
ISW = 32 mA; VCC = 4.5 V to 5.5 V
VI = GND to VCC
-
-
-
-
7.6
7.0
6.1
4.9
20
18
15
10
-
-
-
-
30
27
23
15
Ω
Ω
Ω
Ω
[2]
RON(flat) ON resistance
(flatness)
ISW = 4 mA;
-
26.0
-
-
-
Ω
V
CC = 1.65 V to 1.95 V
ISW = 8 mA; VCC = 2.3 V to 2.7 V
ISW = 12 mA; VCC = 2.7 V
-
-
-
-
5.0
3.5
2.0
1.5
-
-
-
-
-
-
-
-
-
-
-
-
Ω
Ω
Ω
Ω
ISW = 24 mA; VCC = 3.0 V to 3.6 V
ISW = 32 mA; VCC = 4.5 V to 5.5 V
[1] Typical values are measured at Tamb = 25 °C and nominal VCC
.
[2] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
74LVC2G66_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 1 July 2008
7 of 24
74LVC2G66
NXP Semiconductors
Bilateral switch
10.3 ON resistance test circuit and graphs
mna673
40
R
ON
(Ω)
30
V
SW
(1)
20
10
0
V
CC
E
Y
(2)
(3)
V
IH
Z
(4)
(5)
GND
V
I
I
SW
0
1
2
3
4
5
V (V)
I
001aag490
RON = VSW/ISW
.
(1) VCC = 1.8 V.
(2) VCC = 2.5 V.
(3) VCC = 2.7 V.
(4) VCC = 3.3 V.
(5) VCC = 5.0 V.
Fig 10. Test circuit for measuring ON resistance
Fig 11. Typical ON resistance as a function of input
voltage; Tamb = 25 °C
001aaa712
001aaa708
55
15
R
ON
R
ON
(Ω)
(Ω)
45
13
35
25
15
5
11
9
(4)
(3)
(2)
(1)
(1)
(2)
(3)
(4)
7
5
0
0.4
0.8
1.2
1.6
2.0
0
0.5
1.0
1.5
2.0
2.5
V (V)
I
V (V)
I
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
Fig 12. ON resistance as a function of input voltage;
CC = 1.8 V
Fig 13. ON resistance as a function of input voltage;
VCC = 2.5 V
V
74LVC2G66_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 1 July 2008
8 of 24
74LVC2G66
NXP Semiconductors
Bilateral switch
001aaa709
001aaa710
13
10
R
(Ω)
ON
R
ON
(Ω)
11
8
6
4
(1)
(1)
(2)
9
7
5
(2)
(3)
(3)
(4)
(4)
0
0.5
1.0
1.5
2.0
2.5 3.0
V (V)
I
0
1
2
3
4
V (V)
I
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
Fig 14. ON resistance as a function of input voltage;
CC = 2.7 V
Fig 15. ON resistance as a function of input voltage;
VCC = 3.3 V
V
001aaa711
7
6
5
4
3
R
ON
(Ω)
(1)
(2)
(3)
(4)
0
1
2
3
4
5
V (V)
I
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
Fig 16. ON resistance as a function of input voltage; VCC = 5.0 V
74LVC2G66_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 1 July 2008
9 of 24
74LVC2G66
NXP Semiconductors
Bilateral switch
11. Dynamic characteristics
Table 9.
Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 19.
Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit
Min
Typ[1] Max
Min
Max
[2][3]
tpd
propagation delay nY to nZ or nZ to nY;
see Figure 17
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
-
-
-
-
-
0.8
0.4
0.4
0.3
0.2
2.0
1.2
1.0
0.8
0.6
-
-
-
-
-
3.0
2.0
1.5
1.5
1.0
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
[4]
ten
enable time
nE to nY or nZ;
see Figure 18
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.0
1.0
1.0
1.0
1.0
4.6
2.7
2.7
2.4
1.8
10
1.0
1.0
1.0
1.0
1.0
13.0
7.5
6.5
6.0
5.0
ns
ns
ns
ns
ns
5.6
5.0
4.4
3.9
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
E to Y or Z; see Figure 18
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[5]
tdis
disable time
1.0
1.0
1.0
1.0
1.0
3.8
2.1
3.5
3.0
2.2
9.0
5.5
6.5
6.0
5.0
1.0
1.0
1.0
1.0
1.0
11.5
7.0
8.5
8.0
6.5
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
[6]
CPD
power dissipation CL = 50 pF; fi = 10 MHz;
capacitance
VI = GND to VCC
VCC = 2.5 V
-
-
-
9.0
-
-
-
-
-
-
-
-
-
pF
pF
pF
VCC = 3.3 V
11.0
15.7
VCC = 5.0 V
[1] Typical values are measured at Tamb = 25 °C and nominal VCC
.
[2] tpd is the same as tPLH and tPHL
.
[3] Propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when
driven by an ideal voltage source (zero output impedance).
[4] ten is the same as tPZH and tPZL
.
[5] tdis is the same as tPLZ and tPHZ
.
[6] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ{(CL + CS(ON)) × VCC2 × fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
CS(ON) = maximum ON-state switch capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ{(CL + CS(ON)) × VCC2 × fo} = sum of the outputs.
74LVC2G66_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 1 July 2008
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74LVC2G66
NXP Semiconductors
Bilateral switch
11.1 Waveforms and test circuit
V
I
nY or nZ
input
V
V
M
M
GND
t
t
PLH
PHL
V
OH
nZ or nY
output
V
M
V
M
V
OL
001aaa541
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 17. Input (nY or nZ) to output (nZ or nY) propagation delays
V
I
nE input
V
M
GND
t
t
PZL
PLZ
V
CC
output
nY or nZ
nY or nZ
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
switch
enabled
switch
enabled
switch
disabled
001aaa542
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 18. Enable and disable times
Table 10. Measurement points
Supply voltage
VCC
Input
Output
VM
VM
VX
VY
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5 × VCC
0.5 × VCC
1.5 V
0.5 × VCC
0.5 × VCC
1.5 V
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
VOL + 0.3 V
V
V
V
V
V
OH − 0.15 V
OH − 0.15 V
OH − 0.3 V
OH − 0.3 V
OH − 0.3 V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
1.5 V
0.5 × VCC
0.5 × VCC
74LVC2G66_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 1 July 2008
11 of 24
74LVC2G66
NXP Semiconductors
Bilateral switch
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
mna616
Test data is given in Table 11.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
VEXT = External voltage for measuring switching times.
Fig 19. Test circuit for measuring switching times
Table 11. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPZH, tPHZ
tPZL, tPLZ
2 × VCC
2 × VCC
6 V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
GND
GND
GND
GND
GND
500 Ω
500 Ω
500 Ω
500 Ω
open
open
3.0 V to 3.6 V
4.5 V to 5.5 V
open
6 V
open
2 × VCC
11.2 Additional dynamic characteristics
Table 12. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C.
Symbol Parameter
Conditions
Min Typ
Max Unit
THD
total harmonic distortion
RL = 10 kΩ; CL = 50 pF; fi = 1 kHz; see Figure 20
VCC = 1.65 V
-
-
-
-
0.032
-
-
-
-
%
%
%
%
VCC = 2.3 V
0.008
0.006
0.005
VCC = 3.0 V
VCC = 4.5 V
RL = 10 kΩ; CL = 50 pF; fi = 10 kHz; see Figure 20
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
-
-
-
-
0.068
0.009
0.008
0.006
-
-
-
-
%
%
%
%
74LVC2G66_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 1 July 2008
12 of 24
74LVC2G66
NXP Semiconductors
Bilateral switch
Table 12. Additional dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C.
Symbol Parameter
Conditions
Min Typ
Max Unit
f(-3dB)
−3 dB frequency response
RL = 600 Ω; CL = 50 pF; see Figure 21
VCC = 1.65 V
-
-
-
-
135
145
150
155
-
-
-
-
MHz
MHz
MHz
MHz
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
RL = 50 Ω; CL = 10 pF; see Figure 21
VCC = 1.65 V
-
-
-
-
200
350
410
440
-
-
-
-
MHz
MHz
MHz
MHz
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
RL = 50 Ω; CL = 5 pF; see Figure 21
VCC = 1.65 V
-
-
-
-
> 500
> 500
> 500
> 500
-
-
-
-
MHz
MHz
MHz
MHz
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
αiso
isolation (OFF-state)
RL = 600 Ω; CL = 50 pF; fi = 1 MHz; see Figure 22
VCC = 1.65 V
-
-
-
-
−46
−46
−46
−46
-
-
-
-
dB
dB
dB
dB
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
RL = 50 Ω; CL = 5 pF; fi = 1 MHz; see Figure 22
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
-
-
-
-
−37
−37
−37
−37
-
-
-
-
dB
dB
dB
dB
Vct
crosstalk voltage
between digital inputs and switch; RL = 600 Ω;
CL = 50 pF; fi = 1 MHz; tr = tf = 2 ns; see Figure 23
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
-
-
-
-
-
-
-
-
-
mV
mV
mV
mV
91
119
205
74LVC2G66_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 1 July 2008
13 of 24
74LVC2G66
NXP Semiconductors
Bilateral switch
Table 12. Additional dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C.
Symbol Parameter
Conditions
Min Typ
Max Unit
Xtalk
crosstalk
between switches; RL = 600 Ω; CL = 50 pF;
fi = 1 MHz; see Figure 24
VCC = 1.65 V
VCC = 2.3 V
VCC = 3 V
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
−56
−56
−56
VCC = 4.5 V
between switches; RL = 50 Ω; CL = 5 pF;
fi = 1 MHz; see Figure 24
VCC = 1.65 V
VCC = 2.3 V
VCC = 3 V
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
−29
−28
−28
VCC = 4.5 V
Qinj
charge injection
CL = 0.1 nF; Vgen = 0 V; Rgen = 0 Ω; fi = 1 MHz;
RL = 1 MΩ; see Figure 25
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 5.5 V
-
-
-
-
-
3.3
4.1
5.0
6.4
7.5
-
-
-
-
-
pC
pC
pC
pC
pC
11.3 Test circuits
V
0.5V
CC
CC
E
V
R
L
IH
10 pF
Y/Z
Z/Y
V
O
f
600 Ω
C
L
D
i
001aag492
Test conditions:
VCC = 1.65 V: Vi = 1.4 V (p-p).
VCC = 2.3 V: Vi = 2 V (p-p).
VCC = 3 V: Vi = 2.5 V (p-p).
VCC = 4.5 V: Vi = 4 V (p-p).
Fig 20. Test circuit for measuring total harmonic distortion
74LVC2G66_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 1 July 2008
14 of 24
74LVC2G66
NXP Semiconductors
Bilateral switch
V
0.5V
CC
CC
E
V
R
L
IH
0.1 µF
50 Ω
Y/Z
Z/Y
V
O
f
C
L
dB
i
001aag491
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads −3 dB.
Fig 21. Test circuit for measuring the frequency response when switch is in ON-state
0.5V
V
0.5V
CC
CC
CC
E
R
L
V
R
L
IL
0.1 µF
Y/Z
Z/Y
V
O
f
50 Ω
C
L
dB
i
001aag493
Adjust fi voltage to obtain 0 dBm level at input.
Fig 22. Test circuit for measuring isolation (OFF-state)
V
CC
E
Y/Z
Z/Y
V
O
logic
input
G
R
L
C
L
50 Ω
600 Ω
0.5V
0.5V
001aag494
CC
CC
Fig 23. Test circuit for measuring crosstalk voltage (between digital inputs and switch)
74LVC2G66_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 1 July 2008
15 of 24
74LVC2G66
NXP Semiconductors
Bilateral switch
0.5V
CC
1E
V
R
L
IH
0.1 µF
50 Ω
R
i
1Y or 1Z
1Z or 1Y
600 Ω
CHANNEL
ON
C
50 pF
L
f
V
O1
i
0.5V
CC
2E
V
R
L
IL
2Y or 2Z
2Z or 2Y
CHANNEL
OFF
C
50 pF
L
R
600 Ω
i
V
O2
001aag496
20 log10 (VO2 / VO1) or 20 log10 (VO1 / VO2).
Fig 24. Test circuit for measuring crosstalk between switches
V
CC
E
R
gen
Y/Z
Z/Y
V
O
R
1 MΩ
C
L
0.1 nF
G
logic
input
L
V
gen
001aag495
a. Test circuit
logic
input (E)
off
on
off
V
O
∆V
O
mna675
b. Input and output pulse definitions
Qinj = ∆VO × CL.
∆VO = output voltage variation.
Rgen = generator resistance.
Vgen = generator voltage.
Fig 25. Test circuit for measuring charge injection
74LVC2G66_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 1 July 2008
16 of 24
74LVC2G66
NXP Semiconductors
Bilateral switch
12. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.65
0.25
0.5
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
Fig 26. Package outline SOT505-2 (TSSOP8)
74LVC2G66_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 1 July 2008
17 of 24
74LVC2G66
NXP Semiconductors
Bilateral switch
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
Fig 27. Package outline SOT765-1 (VSSOP8)
74LVC2G66_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 1 July 2008
18 of 24
74LVC2G66
NXP Semiconductors
Bilateral switch
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
b
1
2
3
4
4×
(2)
L
L
1
e
8
7
6
5
e
1
e
1
e
1
8×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
1
L
L
1
max max
0.25
0.17
2.0
1.9
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
- - -
07-11-14
07-12-07
SOT833-1
- - -
MO-252
Fig 28. Package outline SOT833-1 (XSON8)
74LVC2G66_4
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Product data sheet
Rev. 04 — 1 July 2008
19 of 24
74LVC2G66
NXP Semiconductors
Bilateral switch
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
SOT996-2
D
B
A
E
A
A
1
detail X
terminal 1
index area
e
1
C
M
M
v
C A
C
B
b
e
L
1
y
y
w
C
1
1
4
L
2
L
8
5
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
b
D
E
e
e
1
L
L
L
v
w
y
y
1
1
2
max
0.05 0.35
0.00 0.15
2.1
1.9
3.1
2.9
0.5
0.3
0.15
0.05
0.6
0.4
mm
0.5
0.5
1.5
0.1
0.05 0.05
0.1
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
- - -
JEDEC
JEITA
07-12-18
07-12-21
SOT996-2
- - -
Fig 29. Package outline SOT996-2 (XSON8U)
74LVC2G66_4
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Product data sheet
Rev. 04 — 1 July 2008
20 of 24
74LVC2G66
NXP Semiconductors
Bilateral switch
XQFN8U: plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm
SOT902-1
D
B
A
terminal 1
index area
E
A
A
1
detail X
e
L
1
e
C
y
y
C
1
L
M
M
v
C A
C
B
4
w
5
6
7
3
2
metal area
not for soldering
e
1
b
e
1
1
terminal 1
index area
8
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
b
D
E
e
e
1
L
L
v
w
y
y
1
1
max
0.05 0.25 1.65 1.65
0.00 0.15 1.55 1.55
0.35 0.15
0.25 0.05
mm
0.5
0.55
0.5
0.1
0.05 0.05 0.05
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
MO-255
JEITA
05-11-25
07-11-14
SOT902-1
- - -
- - -
Fig 30. Package outline SOT902-1 (XQFN8U)
74LVC2G66_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 1 July 2008
21 of 24
74LVC2G66
NXP Semiconductors
Bilateral switch
13. Abbreviations
Table 13. Abbreviations
Acronym
CMOS
TTL
Description
Complementary Metal-Oxide Semiconductor
Transistor-Transistor Logic
Human Body Model
HBM
ESD
ElectroStatic Discharge
Machine Model
MM
DUT
Device Under Test
14. Revision history
Table 14. Revision history
Document ID
74LVC2G66_4
Modifications:
Release date
20080701
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LVC2G66_3
• Section 8: derating factor for TSSOP8 package corrected.
• Added type number 74LVC2G66GD (XSON8U package).
74LVC2G66_3
74LVC2G66_2
74LVC2G66_1
20080310
20070828
20040629
Product data sheet
Product data sheet
Product data sheet
-
-
-
74LVC2G66_2
74LVC2G66_1
-
74LVC2G66_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 1 July 2008
22 of 24
74LVC2G66
NXP Semiconductors
Bilateral switch
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC2G66_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 1 July 2008
23 of 24
74LVC2G66
NXP Semiconductors
Bilateral switch
17. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
8
9
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
10
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 7
ON resistance test circuit and graphs. . . . . . . . 8
10.1
10.2
10.3
11
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms and test circuit . . . . . . . . . . . . . . . 11
Additional dynamic characteristics . . . . . . . . . 12
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
11.1
11.2
11.3
12
13
14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 23
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 23
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 1 July 2008
Document identifier: 74LVC2G66_4
相关型号：
74LVC2G74DP,125
74LVC2G74 - Single D-type flip-flop with set and reset; positive edge trigger TSSOP 8-Pin
NXP
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