74LVC2G74GF,115 [NXP]
74LVC2G74 - Single D-type flip-flop with set and reset; positive edge trigger SON 8-Pin;
| 型号： | 74LVC2G74GF,115 |
| 厂家： | 
NXP |
| 描述： | 74LVC2G74 - Single D-type flip-flop with set and reset; positive edge trigger SON 8-Pin 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总25页 (文件大小：302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC2G74
Single D-type flip-flop with set and reset; positive edge trigger
Rev. 10 — 2 April 2013
Product data sheet
1. General description
The 74LVC2G74 is a single positive-edge triggered D-type flip-flop with individual data (D)
inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q
outputs.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing damaging backflow current through the device
when it is powered down.
The set and reset are asynchronous active LOW inputs and operate independently of the
clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs must be stable, one set-up time
prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt-trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
24 mA output drive (VCC = 3.0 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC2G74DP
74LVC2G74DC
74LVC2G74GT
74LVC2G74GF
74LVC2G74GD
74LVC2G74GM
74LVC2G74GN
74LVC2G74GS
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
TSSOP8 plastic thin shrink small outline package; 8 leads; body SOT505-2
width 3 mm; lead length 0.5 mm
VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
XSON8
XSON8
XSON8
XQFN8
XSON8
XSON8
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 1.95 0.5 mm
extremely thin small outline package; no leads;
SOT1089
8 terminals; body 1.35 1 0.5 mm
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; body 3 2 0.5 mm
plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 1.6 0.5 mm
SOT902-2
SOT1116
SOT1203
extremely thin small outline package; no leads;
8 terminals; body 1.2 1.0 0.35 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35 1.0 0.35 mm
4. Marking
Table 2.
Marking codes
Type number
74LVC2G74DP
74LVC2G74DC
74LVC2G74GT
74LVC2G74GF
74LVC2G74GD
74LVC2G74GM
74LVC2G74GN
74LVC2G74GS
Marking code[1]
V74
V74
V74
Y4
V74
V74
Y4
Y4
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
74LVC2G74
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 10 — 2 April 2013
2 of 25
74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
5. Functional diagram
SD
SD
Q
Q
D
D
Q
Q
CP
S
CP
FF
C1
1D
R
RD
RD
001aah725
001aah726
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Q
C
C
C
C
C
C
C
Q
C
D
RD
SD
CP
mna421
C
C
Fig 3. Logic diagram
74LVC2G74
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 10 — 2 April 2013
3 of 25
74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
6. Pinning information
6.1 Pinning
74LVC2G74
CP
D
1
2
3
4
8
7
6
5
V
CC
SD
RD
Q
74LVC2G74
Q
1
2
3
4
8
7
6
5
CP
D
V
CC
SD
RD
Q
GND
Q
GND
001aaf643
Transparent top view
001aaf642
Fig 4. Pin configuration SOT505-2 and SOT765-1
Fig 5. Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
74LVC2G74
terminal 1
index area
SD
1
7
6
5
CP
D
CP
D
1
2
3
4
8
7
6
5
V
CC
RD
Q
2
3
SD
RD
Q
74LVC2G74
Q
Q
GND
001aaf644
001aah947
Transparent top view
Transparent top view
Fig 6. Pin configuration SOT996-2
Fig 7. Pin configuration SOT902-2
74LVC2G74
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 10 — 2 April 2013
4 of 25
74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SOT505-2, SOT765-1, SOT833-1, SOT1089,
SOT996-2, SOT1116 and SOT1203
SOT902-2
CP
D
1
2
3
4
5
6
7
8
7
6
5
4
3
2
1
8
clock input (LOW-to-HIGH, edge-triggered)
data input
Q
complement output
GND
Q
ground (0 V)
true output
RD
SD
VCC
asynchronous reset-direct input (active LOW)
asynchronous set-direct input (active LOW)
supply voltage
7. Functional description
Table 4.
Function table for asynchronous operation[1]
Input
SD
L
Output
RD
H
CP
X
D
X
X
X
Q
H
L
Q
L
H
L
X
H
H
L
L
X
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Table 5.
Input
SD
Function table for synchronous operation[1]
Output
RD
H
CP
D
L
Qn+1
L
Qn+1
H
H
H
H
H
H
L
[1] H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH CP transition; Qn+1 = state after the next LOW-to-HIGH CP transition.
74LVC2G74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 10 — 2 April 2013
5 of 25
74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
0.5
50
0.5
-
Max
+6.5
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
VI
+6.5
50
IOK
output clamping current
output voltage
VO > VCC or VO < 0 V
Active mode
mA
[1][2]
[1][2]
VO
0.5
0.5
-
VCC + 0.5 V
Power-down mode
VO = 0 V to VCC
+6.5
50
100
-
V
IO
output current
mA
mA
mA
mW
C
ICC
IGND
Ptot
Tstg
supply current
-
ground current
100
-
[3]
total power dissipation
storage temperature
Tamb = 40 C to +125 C
300
+150
65
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP8 packages: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 packages: above 110 C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8 and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 7.
Symbol
VCC
Operating conditions
Parameter
Conditions
Min
Max
5.5
Unit
V
supply voltage
input voltage
1.65
VI
0
5.5
V
VO
output voltage
Active mode
0
VCC
5.5
V
Power-down mode; VCC = 0 V
0
V
Tamb
ambient temperature
40
+125
20
C
ns/V
ns/V
t/V
input transition rise and fall rate
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
-
-
10
74LVC2G74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 10 — 2 April 2013
6 of 25
74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
10. Static characteristics
Table 8.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
Tamb = 40 C to +85 C
VIH
HIGH-level input voltage VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.65 VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7
-
VCC = 2.7 V to 3.6 V
2.0
-
VCC = 4.5 V to 5.5 V
0.7 VCC
-
VIL
LOW-level input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
-
-
-
-
0.35 VCC
0.7
0.8
0.3 VCC
VOH
HIGH-level output voltage VI = VIH or VIL
IO = 100 A; VCC = 1.65 V to 5.5 V
VCC 0.1
1.2
-
-
-
-
-
-
-
V
V
V
V
V
V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
1.54
2.15
2.50
2.62
4.11
1.9
2.2
2.3
3.8
VOL
LOW-level output voltage VI = VIH or VIL
IO = 100 A; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
-
-
-
-
-
-
-
-
0.10
0.45
0.30
0.40
0.55
0.55
5
V
0.07
0.12
0.17
0.33
0.39
0.1
V
V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
V
V
V
II
input leakage current
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
A
IOFF
ICC
power-off leakage current VI or VO = 5.5 V; VCC = 0 V
supply current VI = 5.5 V or GND;
CC = 1.65 V to 5.5 V; IO = 0 A
-
-
0.1
10
A
A
0.1
10
V
ICC
additional supply current per pin; VI = VCC 0.6 V; IO = 0 A;
-
-
5
500
-
A
VCC = 2.3 V to 5.5 V
CI
input capacitance
4.0
pF
74LVC2G74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 10 — 2 April 2013
7 of 25
74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
Tamb = 40 C to +125 C
VIH
HIGH-level input voltage VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.65 VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7
-
VCC = 2.7 V to 3.6 V
2.0
-
VCC = 4.5 V to 5.5 V
0.7 VCC
-
VIL
LOW-level input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
-
-
-
-
0.35 VCC
0.7
0.8
0.3 VCC
VOH
HIGH-level output voltage VI = VIH or VIL
IO = 100 A; VCC = 1.65 V to 5.5 V
VCC 0.1
0.95
1.7
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
1.9
2.0
3.4
VOL
LOW-level output voltage VI = VIH or VIL
IO = 100 A; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.10
0.70
0.45
0.60
0.80
0.80
20
V
V
V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
V
V
V
II
input leakage current
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
A
IOFF
ICC
power-off leakage current VI or VO = 5.5 V; VCC = 0 V
-
-
-
-
20
A
A
supply current
VI = 5.5 V or GND;
40
VCC = 1.65 V to 5.5 V; IO = 0 A
ICC
additional supply current per pin; VI = VCC 0.6 V; IO = 0 A;
-
-
5000
A
VCC = 2.3 V to 5.5 V
[1] All typical values are measured at Tamb = 25 C.
74LVC2G74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 10 — 2 April 2013
8 of 25
74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
11. Dynamic characteristics
Table 9.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol Parameter Conditions 40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
[2]
[2]
[2]
tpd
propagation delay CP to Q, Q; see Figure 8
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
1.0
1.0
1.0
1.0
6.0
3.5
3.5
3.5
2.5
13.4
7.1
7.1
5.9
4.1
1.5
1.0
1.0
1.0
1.0
13.4
7.1
7.1
5.9
4.1
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
SD to Q, Q; see Figure 9
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
1.0
1.0
1.0
1.0
6.0
3.5
3.5
3.0
2.5
12.9
7.0
7.0
5.9
4.1
1.5
1.0
1.0
1.0
1.0
12.9
7.0
7.0
5.9
4.1
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
RD to Q, Q; see Figure 9
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
1.5
1.0
1.0
1.0
1.0
5.0
3.5
3.5
3.0
2.5
12.9
7.0
7.0
5.9
4.1
1.5
1.0
1.0
1.0
1.0
12.9
7.0
7.0
5.9
4.1
ns
ns
ns
ns
ns
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
tW
pulse width
CP HIGH or LOW;
see Figure 8
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
6.2
2.7
2.7
2.7
2.0
-
-
-
-
-
-
-
6.2
2.7
2.7
2.7
2.0
-
-
-
-
-
ns
ns
ns
ns
ns
-
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
1.3
-
SD and RD LOW;
see Figure 9
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
6.2
2.7
2.7
2.7
2.0
-
-
-
-
-
-
-
6.2
2.7
2.7
2.7
2.0
-
-
-
-
-
ns
ns
ns
ns
ns
-
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
1.6
-
74LVC2G74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 10 — 2 April 2013
9 of 25
74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
Table 9.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
trec
recovery time
set-up time
hold time
SD or RD; see Figure 9
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.9
1.4
-
-
-
-
-
-
1.9
1.4
-
-
-
-
-
ns
ns
ns
ns
ns
-
1.3
-
3.0
-
1.3
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
D to CP; see Figure 8
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
+1.2
1.0
+1.2
1.0
tsu
2.9
1.7
1.7
1.3
1.1
-
-
-
-
-
-
-
2.9
1.7
1.7
1.3
1.1
-
-
-
-
-
ns
ns
ns
ns
ns
-
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
D to CP; see Figure 8
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
0.5
-
th
1.5
1.0
1.0
1.0
1.0
-
-
-
-
-
-
-
1.5
1.0
1.0
1.0
1.0
-
-
-
-
-
ns
ns
ns
ns
ns
-
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
CP; see Figure 8
0.6
-
fmax
maximum
frequency
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
80
175
175
175
200
-
-
-
-
-
-
-
-
-
80
175
175
175
200
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
pF
-
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
280
-
[3]
CPD
power dissipation VI = GND to VCC
capacitance VCC = 3.3 V
;
15
[1] Typical values are measured at Tamb = 25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL
[3] PD is used to determine the dynamic power dissipation (PD in W).
.
C
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
74LVC2G74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 10 — 2 April 2013
10 of 25
74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
12. Waveforms
t
W
V
I
V
CP input
M
GND
1/f
max
V
I
V
D input
M
GND
t
t
h
h
t
t
su
su
t
t
PLH
PHL
V
OH
V
Q output
Q output
M
V
OL
V
OH
V
M
V
OL
t
t
PHL
PLH
mnb141
Measurement points are given in Table 10.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. The clock input (CP) to output (Q, Q) propagation delays, the clock pulse width, the D to CP set-up, the
CP to D hold times and the CP maximum frequency
Table 10. Measurement points
Supply voltage
VCC
Input
Output
VM
VM
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5 VCC
0.5 VCC
1.5 V
0.5 VCC
0.5 VCC
1.5 V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
1.5 V
0.5 VCC
0.5 VCC
74LVC2G74
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Product data sheet
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11 of 25
74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
V
I
V
M
CP input
GND
t
t
rec
rec
V
I
V
M
SD input
RD input
GND
t
t
W
W
V
I
V
M
GND
t
t
PHL
PLH
V
OH
Q output
Q output
V
V
M
V
OL
V
OH
M
V
OL
t
t
PLH
PHL
mnb142
Measurement points are given in Table 10.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9. The set (SD) and reset (RD) input to output (Q, Q) propagation delays, the set and reset pulse widths and
the RD to CP recovery time
74LVC2G74
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Product data sheet
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12 of 25
74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
mna616
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 10. Test circuit for measuring switching times
Table 11. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPZH, tPHZ
GND
tPZL, tPLZ
2VCC
2VCC
6 V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
VCC
2.0 ns
2.0 ns
2.5 ns
2.5 ns
2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 k
500
500
500
500
open
GND
open
GND
3.0 V to 3.6 V
4.5 V to 5.5 V
open
GND
6 V
open
GND
2VCC
74LVC2G74
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Product data sheet
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13 of 25
74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
13. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.65
0.25
0.5
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
Fig 11. Package outline SOT505-2 (TSSOP8)
74LVC2G74
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Product data sheet
Rev. 10 — 2 April 2013
14 of 25
74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
Fig 12. Package outline SOT765-1 (VSSOP8)
74LVC2G74
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Product data sheet
Rev. 10 — 2 April 2013
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74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
b
1
2
3
4
4×
(2)
L
L
1
e
8
7
6
5
e
1
e
1
e
1
8×
A
(2)
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
1
L
L
1
max max
0.25
0.17
2.0
1.9
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
- - -
07-11-14
07-12-07
SOT833-1
- - -
MO-252
Fig 13. Package outline SOT833-1 (XSON8)
74LVC2G74
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Product data sheet
Rev. 10 — 2 April 2013
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74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1 x 0.5 mm
SOT1089
E
terminal 1
index area
D
A
A
1
detail X
(2)
(4×)
e
L
(2)
(8×)
b
4
5
e
1
1
8
terminal 1
index area
L
1
X
0
0.5
1 mm
scale
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
L
1
1
max 0.5 0.04 0.20 1.40 1.05
0.35 0.40
0.15 1.35 1.00 0.55 0.35 0.30 0.35
0.12 1.30 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1089_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
10-04-09
10-04-12
SOT1089
MO-252
Fig 14. Package outline SOT1089 (XSON8)
74LVC2G74
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74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
XSON8: plastic extremely thin small outline package; no leads;
8 terminals; body 3 x 2 x 0.5 mm
SOT996-2
D
B
A
E
A
A
1
detail X
terminal 1
index area
e
1
C
v
C
C
A
B
b
e
L
1
y
1
y
w
C
1
4
L
2
L
8
5
X
0
1
2 mm
scale
Dimensions (mm are the original dimensions)
(1)
Unit
A
A
1
b
D
E
e
e
1
L
L
1
L
2
v
w
y
y
1
max
mm nom 0.5
min
0.05 0.35 2.1 3.1
0.00 0.15 1.9 2.9
0.5 0.15 0.6
0.3 0.05 0.4
0.5 1.5
0.1 0.05 0.05 0.1
sot996-2_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
07-12-21
12-11-20
SOT996-2
Fig 15. Package outline SOT996-2 (XSON8)
74LVC2G74
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Product data sheet
Rev. 10 — 2 April 2013
18 of 25
74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
XQFN8: plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 x 1.6 x 0.5 mm
SOT902-2
X
D
B
A
E
terminal 1
index area
A
A
1
detail X
e
C
v
C
C
A
B
b
y
y
w
C
1
4
3
2
5
e
1
6
7
1
terminal 1
index area
8
L
metal area
not for soldering
L
1
0
1
2 mm
scale
Dimensions
(1)
Unit
A
A
1
b
D
E
e
e
1
L
L
v
w
y
y
1
1
max 0.5 0.05 0.25 1.65 1.65
0.35 0.15
0.20 1.60 1.60 0.55 0.5 0.30 0.10 0.1 0.05 0.05 0.05
0.00 0.15 1.55 1.55 0.25 0.05
mm nom
min
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot902-2_po
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
JEITA
- - -
10-11-02
11-03-31
SOT902-2
MO-255
Fig 16. Package outline SOT902-2 (XQFN8)
74LVC2G74
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Product data sheet
Rev. 10 — 2 April 2013
19 of 25
74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.2 x 1.0 x 0.35 mm
SOT1116
b
4
(2)
1
2
3
(4×)
L
L
1
e
8
7
6
5
e
1
e
1
e
1
(2)
(8×)
A
1
A
D
E
terminal 1
index area
0
0.5
scale
1 mm
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
L
1
1
max 0.35 0.04 0.20 1.25 1.05
0.35 0.40
0.15 1.20 1.00 0.55 0.3 0.30 0.35
0.12 1.15 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1116_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
10-04-02
10-04-07
SOT1116
Fig 17. Package outline SOT1116 (XSON8)
74LVC2G74
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Product data sheet
Rev. 10 — 2 April 2013
20 of 25
74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1.0 x 0.35 mm
SOT1203
b
4
(2)
(4×)
1
2
3
L
L
1
e
8
7
6
5
e
1
e
1
e
1
(2)
(8×)
A
1
A
D
E
terminal 1
index area
0
L
0.5
scale
1 mm
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
1
1
max 0.35 0.04 0.20 1.40 1.05
0.35 0.40
0.15 1.35 1.00 0.55 0.35 0.30 0.35
0.12 1.30 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1203_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
10-04-02
10-04-06
SOT1203
Fig 18. Package outline SOT1203 (XSON8)
74LVC2G74
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Product data sheet
Rev. 10 — 2 April 2013
21 of 25
74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
14. Abbreviations
Table 12. Abbreviations
Acronym
CMOS
HBM
ESD
Description
Complementary Metal-Oxide Semiconductor
Human Body Model
ElectroStatic Discharge
Machine Model
MM
DUT
Device Under Test
TTL
Transistor-Transistor Logic
15. Revision history
Table 13. Revision history
Document ID
74LVC2G74 v.10
Modifications:
Release date
20130402
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LVC2G74 v.9
• For type number 74LVC2G74GD XSON8U has changed to XSON8.
20120522 Product data sheet 74LVC2G74 v.8
• For type number 74LVC2G74GM the sot code has changed to SOT902-2.
74LVC2G74 v.9
Modifications:
-
74LVC2G74 v.8
Modifications:
20111128
Product data sheet
-
74LVC2G74 v.7
• Legal pages updated.
74LVC2G74 v.7
74LVC2G74 v.6
74LVC2G74 v.5
74LVC2G74 v.4
74LVC2G74 v.3
74LVC2G74 v.2
74LVC2G74 v.1
20101011
20091223
20080630
20080207
20070809
20061214
20051103
Product data sheet
-
-
-
-
-
-
-
74LVC2G74 v.6
74LVC2G74 v.5
74LVC2G74 v.4
74LVC2G74 v.3
74LVC2G74 v.2
74LVC2G74 v.1
-
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product data sheet
74LVC2G74
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Rev. 10 — 2 April 2013
22 of 25
74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
16.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
74LVC2G74
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Product data sheet
Rev. 10 — 2 April 2013
23 of 25
74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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Product data sheet
Rev. 10 — 2 April 2013
24 of 25
74LVC2G74
NXP Semiconductors
Single D-type flip-flop with set and reset; positive edge trigger
18. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 23
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 24
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 April 2013
Document identifier: 74LVC2G74
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