74LVC2GU04GF [NXP]
Dual inverter; 双变频器
| 型号： | 74LVC2GU04GF |
| 厂家： | 
NXP |
| 描述： | Dual inverter |
| 文件： | 总16页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC2GU04
Dual inverter
Rev. 05 — 27 October 2009
Product data sheet
1. General description
The 74LVC2GU04 provides two inverters. Each inverter is a single stage with unbuffered
output.
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
2. Features
I Wide supply voltage range from 1.65 V to 5.5 V
I 5 V tolerant input/output for interfacing with 5 V logic
I High noise immunity
I ±24 mA output drive (VCC = 3.0 V)
I CMOS low power consumption
I Latch-up performance exceeds 250 mA
I Input accepts voltages up to 5 V
I Multiple package options
I ESD protection:
N HBM JESD22-A114F exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
−40 °C to +125 °C
−40 °C to +125 °C
Name
SC-88
TSOP6
Description
Version
SOT363
SOT457
74LVC2GU04GW
74LVC2GU04GV
plastic surface-mounted package; 6 leads
plastic surface-mounted package (TSOP6);
6 leads
74LVC2GU04GM
74LVC2GU04GF
−40 °C to +125 °C
−40 °C to +125 °C
XSON6
XSON6
plastic extremely thin small outline package;
no leads; 6 terminals; body 1 × 1.45 × 0.5 mm
SOT886
SOT891
plastic extremely thin small outline package;
no leads; 6 terminals; body 1 × 1 × 0.5 mm
74LVC2GU04
NXP Semiconductors
Dual inverter
4. Marking
Table 2.
Marking codes
Type number
Marking[1]
YD
74LVC2GU04GW
74LVC2GU04GV
74LVC2GU04GM
74LVC2GU04GF
VU4
YD
YD
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
V
CC
V
CC
1A
2A
1Y
6
4
1
3
1
1
1
3
6
4
100 Ω
Y
A
2Y
mnb106
mnb107
mna636
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram (one gate)
6. Pinning information
6.1 Pinning
74LVC2GU04
74LVC2GU04
1A
GND
2A
1
2
3
6
5
4
1Y
74LVC2GU04
1
2
3
6
5
4
1A
GND
2A
1Y
1A
GND
2A
1
2
3
6
5
4
1Y
V
CC
V
CC
V
CC
2Y
2Y
2Y
001aab681
001aag421
Transparent top view
Transparent top view
001aab680
Fig 4. Pin configuration SOT363
and SOT457
Fig 5. Pin configuration SOT886
Fig 6. Pin configuration SOT891
74LVC2GU04_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 27 October 2009
2 of 16
74LVC2GU04
NXP Semiconductors
Dual inverter
6.2 Pin description
Table 3.
Symbol
1A
Pin description
Pin
1
Description
data input
GND
2A
2
ground (0 V)
data input
3
2Y
4
data output
supply voltage
data output
VCC
5
1Y
6
7. Functional description
Table 4.
Function table[1]
Input
nA
L
Output
nY
H
H
L
[1] H = HIGH voltage level;
L = LOW voltage level.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
−0.5
−50
−0.5
−50
−0.5
-
Max
+6.5
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
VI
+6.5
-
IOK
output clamping current
output voltage
VO < 0 V
mA
V
[1][2]
VO
Active mode
VO = 0 V to VCC
VCC + 0.5
±50
100
-
IO
output current
mA
mA
mA
°C
ICC
supply current
-
IGND
Tstg
Ptot
ground current
−100
−65
-
storage temperature
total power dissipation
+150
250
[3]
Tamb = −40 °C to +125 °C
mW
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
74LVC2GU04_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 27 October 2009
3 of 16
74LVC2GU04
NXP Semiconductors
Dual inverter
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
Min
Typ
Max
5.5
Unit
V
VCC
VI
supply voltage
input voltage
1.65
-
-
-
-
-
-
0
5.5
V
VO
output voltage
ambient temperature
Active mode
0
VCC
+125
20
V
Tamb
∆t/∆V
−40
°C
input transition rise and fall rate VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
-
-
ns/V
ns/V
10
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C[1]
VIH
VIL
HIGH-level input voltage VCC = 1.65 V to 5.5 V
LOW-level input voltage VCC = 1.65 V to 5.5 V
0.75 × VCC
-
-
-
V
V
-
0.25 × VCC
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −100 µA;
VCC − 0.1
-
-
V
VCC = 1.65 V to 5.5 V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −24 mA; VCC = 3.0 V
IO = −32 mA; VCC = 4.5 V
1.2
1.9
2.2
2.3
3.8
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
VOL
LOW-level output voltage VI = VIH or VIL
IO = 100 µA;
CC = 1.65 V to 5.5 V
-
-
0.1
V
V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VI = 5.5 V or GND;
-
-
-
-
-
-
-
0.45
0.3
V
-
V
-
0.4
V
-
0.55
0.55
±5
V
-
V
[2]
II
input leakage current
supply current
±0.1
µA
V
CC = 0 V to 5.5 V
VI = 5.5 V or GND; IO = 0 A;
CC = 1.65 V to 5.5 V
VCC = 3.3 V; VI = GND to VCC
ICC
CI
-
-
0.1
5
10
-
µA
V
input capacitance
pF
74LVC2GU04_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 27 October 2009
4 of 16
74LVC2GU04
NXP Semiconductors
Dual inverter
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +125 °C
VIH
VIL
HIGH-level input voltage VCC = 1.65 V to 5.5 V
LOW-level input voltage VCC = 1.65 V to 5.5 V
0.8 × VCC
-
-
-
V
V
-
0.2 × VCC
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −100 µA;
VCC − 0.1
-
-
V
VCC = 1.65 V to 5.5 V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −24 mA; VCC = 3.0 V
IO = −32 mA; VCC = 4.5 V
0.95
1.7
1.9
2.0
3.4
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
VOL
LOW-level output voltage VI = VIH or VIL
IO = 100 µA;
CC = 1.65 V to 5.5 V
-
-
0.1
V
V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VI = 5.5 V or GND;
-
-
-
-
-
-
-
-
-
-
-
-
0.7
0.45
0.6
0.8
0.8
±20
V
V
V
V
V
II
input leakage current
supply current
µA
V
CC = 0 V to 5.5 V
VI = 5.5 V or GND; IO = 0 A;
CC = 1.65 V to 5.5 V
ICC
-
-
40
µA
V
[1] All typical values are measured at Tamb = 25 °C.
[2] These typical values are measured at VCC = 3.3 V.
74LVC2GU04_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 27 October 2009
5 of 16
74LVC2GU04
NXP Semiconductors
Dual inverter
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.
Symbol Parameter Conditions −40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
[2]
tpd
propagation delay nA to nY; see Figure 7
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.5
0.3
0.3
0.3
0.3
-
2.3
1.8
2.6
2.3
1.7
7.8
5.0
4.0
4.5
3.7
3.0
-
0.5
0.3
0.3
0.3
0.3
6.3
5.0
5.6
4.5
3.8
ns
ns
ns
ns
ns
pF
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
[3]
CPD
power dissipation VI = GND to VCC; VCC = 3.3 V
capacitance
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL
.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
12. Waveforms
V
I
V
V
M
nA input
M
GND
t
t
PHL
PLH
V
OH
V
V
M
nY output
M
V
OL
mna344
Measurement points are given in Table 9.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 7. The input (nA) to output (nY) propagation delay times
74LVC2GU04_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 27 October 2009
6 of 16
74LVC2GU04
NXP Semiconductors
Dual inverter
Table 9.
Measurement points
Supply voltage
VCC
Input
Output
VM
VM
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5 × VCC
0.5 × VCC
1.5 V
0.5 × VCC
0.5 × VCC
1.5 V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
1.5 V
0.5 × VCC
0.5 × VCC
V
EXT
V
CC
R
L
L
V
V
O
I
G
DUT
R
T
C
L
R
mna616
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8. Load circuitry for switching times
Table 10. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr = tf
RL
tPLH, tPHL
open
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
500 Ω
open
open
3.0 V to 3.6 V
4.5 V to 5.5 V
open
open
74LVC2GU04_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 27 October 2009
7 of 16
74LVC2GU04
NXP Semiconductors
Dual inverter
mnb108
160
g
fs
(mA/V)
120
R
= 560 kΩ
bias
80
40
0
V
CC
0.47 µF
100 µF
input
output
V
I
A
I
O
0
1
2
3
4
5
6
mna638
V
(V)
CC
Tamb = 25 °C.
∆IO
g fs
=
---------
∆VI
fi = 1 kHz.
VO is constant.
Fig 9. Typical forward transconductance as a
function of supply voltage
Fig 10. Test set-up for measuring forward
transconductance
74LVC2GU04_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 27 October 2009
8 of 16
74LVC2GU04
NXP Semiconductors
Dual inverter
13. Application information
Some applications are:
• Linear amplifier (see Figure 11)
• In crystal oscillator design (see Figure 12)
Remark: All values given are typical unless otherwise specified.
R2
R1
V
CC
R2
1 µF
R1
U04
U04
C1
C2
Z
L
out
mna053
mna052
Vo(p-p) = VCC − 1.5 V centered at 0.5VCC
.
C1 = 47 pF (typical).
C2 = 22 pF (typical).
AOL
Au = –
-----------------------------------------
R1 = 1 MΩ to 10 MΩ (typical).
R1
1 +
(1 + A
)
------
OL
R2 optimum value depends on the frequency and
required stability against changes in VCC or average
minimum ICC (ICC is typically 2 mA at VCC = 3.3 V and
f = 10 MHz).
R2
AOL = open loop amplification.
Au = voltage amplification.
R1 ≥ 3 kΩ, R2 ≤ 1 MΩ.
ZL > 10 kΩ; AOL = 20 (typical).
Typical unity gain bandwidth product is 5 MHz.
Fig 11. Linear amplifier configuration
Fig 12. Crystal oscillator configuration
74LVC2GU04_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 27 October 2009
9 of 16
74LVC2GU04
NXP Semiconductors
Dual inverter
14. Package outline
Plastic surface-mounted package; 6 leads
SOT363
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
1
2
3
c
e
1
b
p
L
p
w
M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-08
06-03-16
SOT363
SC-88
Fig 13. Package outline SOT363 (SC-88)
74LVC2GU04_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 27 October 2009
10 of 16
74LVC2GU04
NXP Semiconductors
Dual inverter
Plastic surface-mounted package (TSOP6); 6 leads
SOT457
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
c
1
2
3
L
p
e
b
p
w
M B
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A
b
c
D
E
e
H
L
Q
v
w
y
p
1
p
E
0.1
0.013
0.40
0.25
1.1
0.9
0.26
0.10
3.1
2.7
1.7
1.3
3.0
2.5
0.6
0.2
0.33
0.23
mm
0.95
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
05-11-07
06-03-16
SOT457
SC-74
Fig 14. Package outline SOT457 (TSOP6)
74LVC2GU04_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 27 October 2009
11 of 16
74LVC2GU04
NXP Semiconductors
Dual inverter
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L
1
e
6
5
4
e
1
e
1
6×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
1.5
1.4
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
04-07-15
04-07-22
SOT886
MO-252
Fig 15. Package outline SOT886 (XSON6)
74LVC2GU04_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 27 October 2009
12 of 16
74LVC2GU04
NXP Semiconductors
Dual inverter
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
SOT891
b
1
2
3
4×
(1)
L
L
1
e
6
5
4
e
1
e
1
6×
(1)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.20 1.05 1.05
0.12 0.95 0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.55 0.35
Note
1. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
05-04-06
07-05-15
SOT891
Fig 16. Package outline SOT891 (XSON6)
74LVC2GU04_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 27 October 2009
13 of 16
74LVC2GU04
NXP Semiconductors
Dual inverter
15. Abbreviations
Table 11. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
16. Revision history
Table 12. Revision history
Document ID
74LVC2GU04_5
Modifications:
Release date
Data sheet status
Change notice
Supersedes
20091027
Product data sheet
-
74LVC4GU04_4
• Section 2: JESD22-A114E changed to JESD22-A114F
• Section 4 “Marking”: marking code for 74LVC2GU04GV changed from YU4 into VU4
• Figure 8: drawing amended/improved
74LVC2GU04_4
74LVC2GU04_3
74LVC2GU04_2
74LVC2GU04_1
20070521
20040921
20040524
20030829
Product data sheet
Product specification
Product specification
Product specification
-
-
-
-
74LVC4GU04_3
74LVC2GU04_2
74LVC2GU04_1
-
74LVC2GU04_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 27 October 2009
14 of 16
74LVC2GU04
NXP Semiconductors
Dual inverter
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
17.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC2GU04_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 27 October 2009
15 of 16
74LVC2GU04
NXP Semiconductors
Dual inverter
19. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Application information. . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
8
9
10
11
12
13
14
15
16
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
17.1
17.2
17.3
17.4
18
19
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 27 October 2009
Document identifier: 74LVC2GU04_5
相关型号：
©2020 ICPDF网 联系我们和版权申明