74LVC373AD,112_技术文档

74LVC373A

Octal D-type transparent latch with 5 V tolerant

inputs/outputs; 3-state

Rev. 3 — 22 November 2012

Product data sheet

1. General description

The 74LVC373A consists of eight D-type transparent latches, featuring separate D-type

inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable

input (pin LE) and an output enable input (pin OE) are common to all internal latches.

When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this

condition, the latches are transparent, that is, a latch output will change each time its

corresponding D-input changes. When pin LE is LOW, the latches store the information

that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of

pin LE.

When pin OE is LOW, the contents of the eight latches are available at the Q-outputs (pins

Q0 to Q7). When pin OE is HIGH, the outputs go to the high-impedance OFF-state.

Operation of input pin OE does not affect the state of the latches.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be

applied to the outputs. These features allow the use of these devices as translators in

mixed 3.3 V and 5 V applications.

The 74LVC373A is functionally identical to the 74LVC573A, but has a different pin

arrangement.

2. Features and benefits

 5 V tolerant inputs/outputs for interfacing with 5 V logic

 Wide supply voltage range from 1.2 V to 3.6 V

 CMOS low power consumption

 Direct interface with TTL levels

 High-impedance outputs when V_CC= 0 V

 Complies with JEDEC standard:

 JESD8-7A (1.65 V to 1.95 V)

 JESD8-5A (2.3 V to 2.7 V)

 JESD8-C/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-B exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Specified from 40 C to +85 C and 40 C to +125 C

74LVC373A

NXP Semiconductors

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVC373AD

40 C to +125 C

SO20

plastic small outline package; 20 leads; body width 7.5 SOT163-1

mm

74LVC373ADB 40 C to +125 C

74LVC373APW 40 C to +125 C

74LVC373ABQ 40 C to +125 C

SSOP20

TSSOP20

plastic shrink small outline package; 20 leads;

body width 5.3 mm

SOT339-1

plastic thin shrink small outline package; 20 leads;

body width 4.4 mm

SOT360-1

DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1

thin quad flat package; no leads; 20 terminals; body

2.5  4.5  0.85 mm

4. Functional diagram

1

EN

11

D7

D6

D5

D4

D3

D2

D1

D0

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

18

17

14

13

8

19

C1

16

3

2

1D

15

12

9

4

7

8

5

6

9

7

6

13

14

17

18

12

15

16

19

4

5

3

2

LE OE

mna881

11

1

mna880

Fig 1. Logic symbol

Fig 2. IEC logic symbol

74LVC373A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 22 November 2012

2 of 19

74LVC373A

NXP Semiconductors

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

D0

3

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

2

5

D1

4

D2

7

6

D3

8

9

LATCH

D4

3-STATE

OUTPUTS

13

14

17

18

12

15

16

19

1 to 8

LE

D5

D6

D7

LE

11

1

D

Q

OE

mna189

mna882

Fig 3. Functional diagram

Fig 4. Logic diagram for one latch

D0

D1

D2

D3

D4

D5

D6

D7

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

LE LE

LE

OE

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

mna883

Fig 5. Logic diagram

74LVC373A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 22 November 2012

3 of 19

74LVC373A

NXP Semiconductors

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

5. Pinning information

5.1 Pinning

terminal 1

index area

2

3

4

5

6

7

8

9

19

18

17

16

15

14

13

12

Q0

D0

D1

Q1

Q2

D2

D3

Q3

Q7

D7

D6

Q6

Q5

D5

D4

Q4

1

2

20

19

18

17

16

15

14

13

12

11

OE

Q0

V

CC

Q7

D7

D6

Q6

Q5

D5

D4

Q4

LE

3

D0

373A

4

D1

5

Q1

373A

6

Q2

(1)

GND

7

D2

8

D3

9

Q3

001aad089

10

GND

001aad090

Transparent top view

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Fig 6. Pin configuration for SO20 and (T)SSOP20

Fig 7. Pin configuration for DHVQFN20

5.2 Pin description

Table 2.

Symbol

OE

Pin description

1

Description

output enable input (active LOW)

latch enable input (active HIGH)

data input

LE

11

D[0:7]

Q[0:7]

GND

V_CC

3, 4, 7, 8, 13, 14, 17, 18

2, 5, 6, 9, 12, 15, 16, 19

latch output

10

20

ground (0 V)

supply voltage

74LVC373A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 22 November 2012

4 of 19

74LVC373A

NXP Semiconductors

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

6. Functional description

Table 3.

Functional table^[1]

Operating modes

Input

Internal latch

Output

OE

L

LE

H

L

Dn

L

H

l

Qn

L

Enable and read register

(transparent mode)

L

H

L

H

L

Latch and read register

L

h

l

H

L

H

Z

Latch register and disable

outputs

H

L

h

H

Z

[1] H = HIGH voltage level

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition

L = LOW voltage level

l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition

Z = High-impedance OFF-state

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

0.5

50

0.5

-

Max

+6.5

-

Unit

V

supply voltage

input clamping current

input voltage

V_I< 0

mA

V

[1]

V_I

+6.5

50

V_CC+ 0.5

+6.5

50

100

-

I_OK

output clamping current

output voltage

V_O> V_CCor V_O< 0

HIGH or LOW-state

3-state

mA

V

[2]

V_O

0.5

-

V

I_O

output current

V_O= 0 V to V_CC

mA

C

I_CC

I_GND

T_stg

P_tot

supply current

-

ground current

100

65

-

storage temperature

total power dissipation

+150

500

[3]

T_amb= 40 C to +125 C

mW

[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.

[2] The output voltage ratings may be exceeded if the output current ratings are observed.

[3] For SO20 packages: above 70 C the value of P_totderates linearly with 8 mW/K.

For (T)SSOP20 packages: above 60 C the value of P_totderates linearly with 5.5 mW/K.

For DHVQFN20 packages: above 60 C the value of P_totderates linearly with 4.5 mW/K.

74LVC373A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 22 November 2012

5 of 19

74LVC373A

NXP Semiconductors

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

8. Recommended operating conditions

Table 5.

Recommended operating conditions

Symbol Parameter

Conditions

Min

1.65

1.2

0

Typ

Max

3.6

-

Unit

V

V_CC

supply voltage

-

functional

V

V_I

input voltage

5.5

V_CC

5.5

+125

20

V

V_O

output voltage

HIGH or LOW-state

3-state

0

V

0

V

T_amb

ambient temperature

in free air

40

0

C

ns/V

t/V

input transition rise and fall rate V_CC= 1.65 V to 2.7 V

V_CC= 2.7 V to 3.6 V

0

10

9. Static characteristics

Table 6.

Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C

Unit

Min

Typ^[1]

Max

Min

Max

V_IH

HIGH-level

input voltage

V_CC= 1.2 V

1.08

-

1.08

-

V

V_CC= 1.65 V to 1.95 V

0.65  V_CC

-

0.65  V_CC

-

V_CC= 2.3 V to 2.7 V

1.7

-

1.7

-

V_CC= 2.7 V to 3.6 V

V_CC= 1.2 V

2.0

-

0.12

2.0

-

0.12

V_IL

LOW-level

input voltage

-

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_I= V_IHor V_IL

0.35  V_CC

0.7

0.35  V_CC

0.7

0.8

V_OH

HIGH-level

output

voltage

I_O= 100 A;

V_CC= 1.65 V to 3.6 V

V_CC 0.2

-

V_CC 0.3

-

V

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 18 mA; V_CC= 3.0 V

I_O= 24 mA; V_CC= 3.0 V

V_I= V_IHor V_IL

1.2

1.8

2.2

2.4

2.2

-

1.05

1.65

2.05

2.25

2.0

-

V

V_OL

LOW-level

output

voltage

I_O= 100 A;

-

0.2

-

0.3

V

V_CC= 1.65 V to 3.6 V

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

-

0.45

0.6

-

0.65

0.8

V

-

V

-

0.4

0.6

V

0.55

5

0.8

V

I_I

input leakage V_CC= 3.6 V; V_I= 5.5 V or GND

current

0.1

20

A

74LVC373A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 22 November 2012

6 of 19

74LVC373A

NXP Semiconductors

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

Table 6.

Static characteristics …continued

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C

Unit

Min

Typ^[1]

Max

Min

Max

I_OZ

OFF-state

output

V_I= V_IHor V_IL; V_CC= 3.6 V;

V_O= 5.5 V or GND;

-

0.1

5

-

20

A

current

I_OFF

power-off

leakage

supply

V_CC= 0 V; V_Ior V_O= 5.5 V

-

0.1

10

-

20

A

I_CC

supply

current

V_CC= 3.6 V; V_I= V_CCor GND;

I_O= 0 A

-

0.1

5

10

-

40

A

I_CC

additional

supply

per input pin; V_CC= 2.7 V to 3.6

V; V_I= V_CC 0.6 V; I_O= 0 A

500

5000

current

C_I

input

V_CC= 0 V to 3.6 V;

-

5.0

-

pF

capacitance V_I= GND to V_CC

[1] All typical values are measured at V_CC= 3.3 V (unless stated otherwise) and T_amb= 25 C.

10. Dynamic characteristics

Table 7.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 12.

Symbol Parameter Conditions 40 C to +85 C

40 C to +125 C Unit

Min

Typ^[1]

Max

Min

Max

[2]

t_pd

propagation delay Dn to Qn; see Figure 8

V_CC= 1.2 V

-

14

6.5

3.4

2.9

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.5

1.0

1.5

15.8

8.2

7.8

6.8

1.5

1.0

1.5

18.2

9.4

10.0

8.5

V_CC= 3.0 V to 3.6 V

LE to Qn; see Figure 9

V_CC= 1.2 V

-

16

7.3

3.9

3.5

3.3

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

2.2

1.5

16.8

8.6

8.2

7.2

2.2

1.5

19.3

10.0

10.5

9.0

V_CC= 3.0 V to 3.6 V

t_en

enable time

OE to Qn; see Figure 10

V_CC= 1.2 V

-

17

6.8

3.8

3.1

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.5

17.6

9.7

8.7

7.7

1.5

20.3

11.2

11.0

10.0

V_CC= 3.0 V to 3.6 V

74LVC373A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 22 November 2012

7 of 19

74LVC373A

NXP Semiconductors

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

Table 7.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 12.

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C Unit

Min

Typ^[1]

Max

Min

Max

[2]

t_dis

disable time

OE to Qn; see Figure 10

V_CC= 1.2 V

-

8.0

4.3

2.4

3.2

3.0

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

2.3

1.0

1.5

10.3

5.8

7.1

6.1

2.3

1.0

1.5

11.9

6.8

9.0

8.0

V_CC= 3.0 V to 3.6 V

LE HIGH; see Figure 9

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

t_W

t_su

t_h

pulse width

set-up time

hold time

5.0

4.0

3.0

-

5.0

4.0

3.0

-

ns

-

V_CC= 3.0 V to 3.6 V

Dn to LE; see Figure 11

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.5

4.0

3.0

2.0

-

4.0

3.0

2.0

-

ns

-

V_CC= 3.0 V to 3.6 V

Dn to LE; see Figure 11

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

0.0

3.0

2.0

1.5

-

3.0

2.0

1.5

-

ns

-

V_CC= 3.0 V to 3.6 V

0.3

-

[3]

[4]

t_sk(0)

C_PD

output skew time

1.0

1.5

power dissipation per latch; V_I= GND to V_CC

capacitance

V_CC= 1.65 V to 1.95 V

-

16.6

19.2

21.6

-

pF

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

[1] Typical values are measured at T_amb= 25 C and V_CC= 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.

[2] t_pdis the same as t_PLHand t_PHL

t_enis the same as t_PZLand t_PZH

t_disis the same as t_PLZand t_PHZ

[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[4] _PDis used to determine the dynamic power dissipation (P_Din W).

.

C

P_D= C_PD V_CC² f_i N + (C_L V_CC² f_o) where:

f_i= input frequency in MHz; f_o= output frequency in MHz

C_L= output load capacitance in pF

V_CC= supply voltage in Volts

N = number of inputs switching

(C_L V_CC² f_o) = sum of the outputs

74LVC373A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 22 November 2012

8 of 19

74LVC373A

NXP Semiconductors

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

11. AC waveforms

V

I

V

Dn input

M

GND

t

PLH

PHL

V

OH

V

Qn output

M

V

OL

mna884

Measurement points are given in Table 8.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 8. Input (Dn) to output (Qn) propagation delays

V

I

LE input

V

M

GND

t

W

t

PLH

PHL

V

OH

V

Qn output

M

V

OL

mna885

Measurement points are given in Table 8.

_OLand V_OHare typical output voltage levels that occur with the output load.

V

Fig 9. Latch Enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays

74LVC373A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 22 November 2012

9 of 19

74LVC373A

NXP Semiconductors

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

V

I

OE input

V

M

t

GND

t

PLZ

PZL

V

CC

Qn output

LOW-to-OFF

OFF-to-LOW

V

M

V

X

V

OL

t

PZH

PHZ

V

OH

V

Y

Qn output

V

HIGH-to-OFF

OFF-to-HIGH

M

GND

output

enabled

output

enabled

output

disabled

mna886

Measurement points are given in Table 8.

_OLand V_OHare typical output voltage levels that occur with the output load.

V

Fig 10. 3-state enable and disable times

V

I

V

Dn input

M

GND

t

h

t

su

V

I

LE input

V

M

GND

mna887

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig 11. Data set-up and hold times for the Dn input to the LE input

Table 8.

Measurement points

Supply voltage

V_CC

Input

V_I

Output

V_M

V_X

V_Y

1.2 V

V_CC

2.7 V

0.5  V_CC

1.5 V

0.5  V_CC

1.5 V

V_OL+ 0.15 V

V_OL+ 0.3 V

V_OH 0.15 V

V_OH 0.3 V

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

3.0 V to 3.6 V

1.5 V

74LVC373A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 22 November 2012

10 of 19

74LVC373A

NXP Semiconductors

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

EXT

R

V

CC

L

V

O

I

G

DUT

R

T

C

L

R

L

001aae331

Test data is given in Table 9.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig 12. Test circuit for measuring switching times

Table 9.

Test data

Supply voltage

Input

V_I

Load

C_L

V_EXT

t_r, t_f

R_L

t_PLH, t_PHL

open

t_PLZ, t_PZL

2  V_CC

t_PHZ, t_PZH

GND

1.2 V

V_CC

2.7 V

 2 ns

 2.5 ns

30 pF

50 pF

1 k

500 

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

open

GND

open

GND

open

GND

3.0 V to 3.6 V

open

GND

74LVC373A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 22 November 2012

11 of 19

74LVC373A

NXP Semiconductors

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

12. Package outline

SO20: plastic small outline package; 20 leads; body width 7.5 mm

SOT163-1

D

E

A

X

c

y

H

E

v

M

A

Z

20

11

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

10

w

detail X

e

M

b

p

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

max.

(1)

UNIT

mm

A

b

c

D

E

e

H

L

Q

v

w

y

θ

1

2

3

p

E

p

Z

0.3

0.1

2.45

2.25

0.49

0.36

0.32

0.23

13.0

12.6

7.6

7.4

10.65

10.00

1.1

0.4

1.1

1.0

0.9

0.4

2.65

0.1

0.25

0.01

1.27

0.05

1.4

0.25 0.25

0.1

8^o

0^o

0.012 0.096

0.004 0.089

0.019 0.013 0.51

0.014 0.009 0.49

0.30

0.29

0.419

0.394

0.043 0.043

0.016 0.039

0.035

0.016

inches

0.055

0.01 0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT163-1

075E04

MS-013

Fig 13. Package outline SOT163-1 (SO20)

74LVC373A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 22 November 2012

12 of 19

74LVC373A

NXP Semiconductors

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm

SOT339-1

D

E

A

X

v

c

H

M

A

y

E

Z

20

11

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

10

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.21

0.05

1.80

1.65

0.38

0.25

0.20

0.09

7.4

7.0

5.4

5.2

7.9

7.6

1.03

0.63

0.9

0.7

0.9

0.5

mm

2

0.65

0.25

1.25

0.2

0.13

0.1

Note

1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT339-1

MO-150

Fig 14. Package outline SOT339-1 (SSOP20)

74LVC373A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 22 November 2012

13 of 19

74LVC373A

NXP Semiconductors

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm

SOT360-1

D

E

A

X

c

H

v

M

A

y

E

Z

11

20

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

1

10

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

6.6

6.4

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.5

0.2

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT360-1

MO-153

Fig 15. Package outline SOT360-1 (TSSOP20)

74LVC373A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 22 November 2012

14 of 19

74LVC373A

NXP Semiconductors

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

20 terminals; body 2.5 x 4.5 x 0.85 mm

SOT764-1

B

A

D

A

1

E

c

detail X

terminal 1

index area

C

terminal 1

index area

e

1

y

e

b

v

M

C

A

B

C

1

w

M

2

9

L

1

10

E

h

e

20

11

19

12

D

h

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

1

y

D

E

L

v

w

y

1

h

max.

0.05 0.30

0.00 0.18

4.6

4.4

3.15

2.85

2.6

2.4

1.15

0.85

0.5

0.3

mm

0.05

0.1

1

0.2

0.5

3.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-10-17

03-01-27

SOT764-1

- - -

MO-241

- - -

Fig 16. Package outline SOT764-1 (DHVQFN20)

74LVC373A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 22 November 2012

15 of 19

74LVC373A

NXP Semiconductors

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

13. Abbreviations

Table 10. Abbreviations

Acronym

CDM

DUT

Description

Charged Device Model

Device Under Test

ESD

ElectroStatic Discharge

Human Body Model

Machine Model

HBM

MM

TTL

Transistor-Transistor Logic

14. Revision history

Table 11. Revision history

Document ID

74LVC373A v.3

Modifications:

Release date

20121122

Data sheet status

Change notice

Supersedes

Product data sheet

-

74LVC373A v.2

• The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Table 4, Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage ranges.

74LVC373A v.2

74LVC373A v.1

20030519

Product specification

-

74LVC373A v.1

19980729

Product specification

-

74LVC373A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 22 November 2012

16 of 19

74LVC373A

NXP Semiconductors

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

15.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

74LVC373A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 22 November 2012

17 of 19

74LVC373A

NXP Semiconductors

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

74LVC373A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 22 November 2012

18 of 19

74LVC373A

NXP Semiconductors

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

17. Contents

1

2

3

4

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6

Functional description . . . . . . . . . . . . . . . . . . . 5

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Recommended operating conditions. . . . . . . . 6

Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16

7

8

9

10

11

12

13

14

15

Legal information. . . . . . . . . . . . . . . . . . . . . . . 17

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

15.1

15.2

15.3

15.4

16

17

Contact information. . . . . . . . . . . . . . . . . . . . . 18

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 22 November 2012

Document identifier: 74LVC373A


型号：	74LVC373AD,112
厂家：	NXP
描述：	74LVC373A - Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-State SOP 20-Pin
文件：	总19页 (文件大小：144K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74LVC373AD,112 [NXP]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E