74LVC373ADB [NXP]
Octal D-type transparent latch with 5-volt tolerant inputs/outputs 3-State; 八路D型透明锁存器，5伏容限输入/输出三态
| 型号： | 74LVC373ADB |
| 厂家： | 
NXP |
| 描述： | Octal D-type transparent latch with 5-volt tolerant inputs/outputs 3-State |
| 文件： | 总12页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74LVC373A
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
Product specification
1998 Jul 29
Philips
Semiconductors
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
74LVC373A
The 74LVC373A is an octal D-type transparent latch featuring
separate D-type inputs for each latch and 3-State outputs for
bus-oriented applications. A latch enable (LE) input and an output
enable (OE) input are common to all internal latches.
FEATURES
• 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
• Supply voltage range of 2.7V to 3.6V
• Complies with JEDEC standard no. 8-1A
• CMOS low power consumption
• Direct interface with TTL levels
• High impedance when V = 0V
The ’373’ consists of eight D-type transparent latches with 3-State
true outputs. When LE is HIGH, data at the D inputs enters the
n
latches. In this condition, the latches are transparent, i.e. a latch
output will change each time its corresponding D-input changes.
When LE is LOW, the latches store the information that was present
at the D-inputs one setup time preceding the HIGH-to-LOW
transition of LE. When OE is LOW, the contents of the eight latches
are available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
CC
DESCRIPTION
The 74LVC373A is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
The ’373’ is functionally identical to the ’573’, but the ’573’ has a
different pin arrangement.
Inputs can be driven from either 3.3V or 5V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
Propagation delay
D to Q
C = 50pF
L
t
/t
ns
PHL PLH
V
CC
= 3.3V
4.2
4.6
n
n;
LE to Q
n
C
C
Input capacitance
Power dissipation capacitance per latch Notes 1 and 2
5.0
20
pF
pF
I
PD
NOTE:
1. C is used to determine the dynamic power dissipation (P in mW):
PD
D
2
2
P
= C x V
x f + S (C x V
x f ) where:
D
PD
CC
i
L
CC o
f = input frequency in MHz; C = output load capacity in pF;
i
L
f = output frequency in MHz; V = supply voltage in V;
o
CC
2
S (C x V
x f ) = sum of outputs.
L
CC
o
2. The condition is V = GND to V
I
CC
ORDERING INFORMATION
TEMPERATURE
RANGE
OUTSIDE
NORTH AMERICA
PACKAGES
NORTH AMERICA
PKG. DWG. #
20-Pin Plastic Shrink Small Outline (SO)
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74LVC373A D
74LVC373A DB
74LVC373A PW
74LVC373A D
74LVC373A DB
7LVC373APW DH
SOT163-1
SOT339-1
SOT360-1
20-Pin Plastic Shrink Small Outline (SSOP) Type II
20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I
2
1998 Jul 29
853-1860 19802
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
74LVC373A
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
1
EN
11
20
V
CC
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
C1
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
3
2
5
1D
4
7
8
6
9
13
14
12
15
17
18
16
19
GND 10
11
LE
SA00383
SA00385
PIN DESCRIPTION
FUNCTIONAL DIAGRAM
PIN NUMBER SYMBOL
FUNCTION
1
OE
Output enable input (active-Low)
Data inputs
3
4
D0
D1
D2
D3
D4
D5
Q0
Q1
Q2
Q3
Q4
Q5
2
5
6
3, 4, 7, 8, 13,
14, 17, 18
D0-D7
7
2, 5, 6, 9, 12,
15, 16, 19
Q0-Q7
Data outputs
8
9
3-State
OUTPUTS
LATCH
1 to 8
11
10
20
LE
Latch enable input (active-High)
Ground (0V)
12
13
14
GND
15
V
CC
Positive supply voltage
17
18
D6
D7
Q6
Q7
16
19
LOGIC SYMBOL
LE
11
1
OE
3
4
7
8
13 14 17 18
SA00387
D0 D1 D2 D3 D4 D5 D6 D7
11
1
LE
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2
5
6
9
12 15 16 19
SA00384
3
1998 Jul 29
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
74LVC373A
LOGIC DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SA00386
FUNCTION TABLE
INPUTS
LE
OUTPUTS
OPERATING MODES
INTERNAL LATCHES
OE
D
Q to Q
n
0
7
Enable and read register
(transparent mode)
L
L
H
H
L
H
L
H
L
H
Latch and read register
L
L
L
L
l
h
L
H
H
H
Latch register and
disable outputs
H
H
L
L
l
h
L
H
Z
Z
H
h
L
l
X
Z
= HIGH voltage level
= HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition
= LOW voltage level
= LOW voltage level one setup time prior to the HIGH-to-LOW LE transition
= Don’t care
= High impedance OFF-state
4
1998 Jul 29
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
74LVC373A
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN
2.7
1.2
0
MAX
DC supply voltage (for max. speed performance)
DC supply voltage (for low-voltage applications)
DC Input voltage range
3.6
3.6
5.5
V
CC
V
V
V
I
DC Output voltage range; output HIGH or LOW
state
0
V
CC
V
O
V
DC output voltage range; output 3-State
0
5.5
T
amb
Operating ambient temperature range in free-air
–40
+85
°C
V
CC
V
CC
= 1.2 to 2.7V
= 2.7 to 3.6V
0
0
20
10
t , t
r
Input rise and fall times
ns/V
f
1
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
UNIT
V
V
CC
I
IK
–0.5 to +6.5
–50
DC input diode current
V t0
mA
V
I
V
I
DC input voltage
Note 2
uV or V t 0
–0.5 to +6.5
"50
I
DC output diode current
V
O
mA
OK
CC
O
DC output voltage; output HIGH or LOW state
DC output voltage; output 3-State
DC output source or sink current
Note 2
Note 2
–0.5 to V +0.5
CC
V
V
O
–0.5 to 6.5
"50
I
O
V
O
= 0 to V
CC
mA
mA
°C
I
, I
DC V or GND current
"100
GND CC
CC
T
stg
Storage temperature range
–65 to +150
Power dissipation per package
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
P
TOT
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
500
500
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5
1998 Jul 29
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
74LVC373A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
1
MIN
TYP
MAX
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.2V
V
CC
V
HIGH level Input voltage
LOW level Input voltage
V
V
IH
= 2.7 to 3.6V
= 1.2V
2.0
GND
0.8
V
IL
= 2.7 to 3.6V
= 2.7V; V = V or V ; I = –12mA
V
V
V
V
*0.5
I
IH
IL
O
CC
CC
CC
CC
= 3.0V; V = V or V ; I = –100µA
*0.2
*0.6
*0.8
V
CC
I
IH
IL
O
O
O
V
OH
HIGH level output voltage
LOW level output voltage
V
= 3.0V; V = V or V
I
I
= –18mA
= –24mA
I
IH
IL;
IL;
= 3.0V; V = V or V
I
IH
= 2.7V; V = V or V ; I = 12mA
0.40
0.20
0.55
"5
I
IH
IL
O
= 3.0V; V = V or V ; I = 100µA
GND
V
OL
V
I
IH
IL
O
O
= 3.0V; V = V or V
I
= 24mA
I
IH
IL;
2
I
Input leakage current
= 3.6V; V = 5.5V or GND
"0.1
0.1
µA
µA
µA
µA
I
I
I
3-State output OFF-state current
Power off leakage supply
Quiescent supply current
= 3.6V; V = V or V ; V = 5.5V or GND
"10
"10
10
OZ
I
IH
IL
O
I
off
= 0.0V; V or V = 5.5V
0.1
I
O
I
= 3.6V; V = V or GND; I = 0
0.1
CC
I
CC
O
Additional quiescent supply current
per input pin
∆I
CC
V
CC
= 2.7V to 3.6V; V = V –0.6V; I = 0
5
500
µA
I
CC
O
NOTES:
1. All typical values are at V = 3.3V and T
= 25°C.
amb
CC
2. The specified overdrive current at the data input forces the data input to the opposite logic input state.
6
1998 Jul 29
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
74LVC373A
AC CHARACTERISTICS
GND = 0V; t = t v 2.5ns; C = 50pF; R = 500Ω; T
= –40°C to +85°C.
r
f
L
L
amb
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V ±0.3V
V
CC
= 2.7V
V = 1.2V
CC
UNIT
1
MIN
TYP
MAX
MIN
MAX
TYP
t
t
Propagation delay
D to Q
PHL
PLH
1, 5
2, 5
3, 5
1.5
1.5
1.5
4.2
6.8
7.2
7.7
1.5
7.8
8.2
8.7
19
21
22
ns
ns
ns
n
n
t
t
Propagation delay
LE to Q
PHL
PLH
4.6
4.8
1.5
1.5
n
t
3-State output enable time
OE to Q
PZH
t
PZL
n
t
t
3-State output disable time
OE to Q
PHZ
PLZ
3, 5
2
1.5
3.0
2.0
4.3
1.5
0
6.1
–
1.5
3.0
2.0
7.1
–
15
–
ns
ns
ns
n
t
W
LE pulse width HIGH
Setup time
D to LE
n
t
4
–
–
–
SU
Hold time
D to LE
n
t
h
4
1.5
0.3
–
1.5
–
–
ns
NOTE:
1. Unless otherwise stated, all typical values are at V = 3.3V and T
= 25°C.
CC
amb
AC WAVEFORMS
V
V
= 1.5V at V w 2.7V; V = 0.5 V at V t 2.7V.
M
CC M CC CC
and V are the typical output voltage drop that occur with the
V
I
OL
OH
output load.
V
X
V
Y
= V + 0.3V at V w 2.7V; V = V + 0.1 V at V t2.7V
OL CC X OL CC CC
V
nOE INPUT
GND
M
= V –0.3V at V w2.7V; V = V – 0.1 V at V t2.7V
OH
CC
Y
OH
CC
CC
V
I
INPUT
GND
V
M
t
t
t
PZL
PLZ
V
CC
Q
n
OUTPUT
LOW-to-OFF
OFF-to-LOW
t
PHL
PLH
V
V
M
OH
V
X
V
OUTPUT
V
OL
M
t
t
PZH
V
PHZ
OL
SY00041
V
OH
Waveform 1. Input (D ) to output (Qn) propagation delays.
Q
OUTPUT
V
n
n
Y
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
V
I
V
M
LE INPUT
SW00207
GND
t
Waveform 3. 3-State enable and disable times.
w
t
t
PLH
PHL
V
OH
V
Qn OUTPUT
M
V
OL
SA00388
Waveform 2. Latch enable input (LE) pulse width, the latch
enable input to output (Q ) propagation delays
n
7
1998 Jul 29
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
74LVC373A
AC WAVEFORMS
TEST CIRCUIT
with 5-volt tolerant inputs/outputs V = 1.5V at V w 2.7V; V =
M
CC
M
S
1
0.5 V at V t 2.7V.
CC
CC
V
2<V
CC
CC
V
OL
and V are the typical output voltage drop that occur with the
Open
OH
output load.
GND
V
X
V
Y
= V + 0.3V at V w 2.7V; V = V + 0.1 V at V t2.7V
OL CC X OL CC CC
R =500 Ω
L
= V –0.3V at V w2.7V; V = V – 0.1 V at V t2.7V
OH
CC
Y
OH
CC
CC
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
V
I
Dn
INPUT
V
M
R =500 Ω
L
R
C
L
T
GND
th
th
t
t
SU
SU
Test Circuit for 3-State Outputs
SWITCH POSITION
V
I
LE
INPUT
V
M
V
V
IN
TEST
SWITCH
Open
CC
GND
t 2.7V
2.7 – 3.6V 2.7V
V
CC
t
/t
PLH PHL
NOTE: The shaded areas indicate when the input is permitted to change
t
/t
2<V
for predictable output performance.
PLZ PZL
CC
t
/t
GND
PHZ PZH
SW00073
Waveform 4. Data setup and hold times for the D input to the
LE input. (The shaded areas indicate when the input is
permitted to change for predictable output performance).
n
DEFINITIONS
R = Load resistor
C = Load capacitance includes jig and probe capacitance
L
L
R = Termination resistance should be equal to Z
T
OUT
of pulse generators.
SW00047
Waveform 5. Load circuitry for switching times.
8
1998 Jul 29
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
74LVC373A
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
9
1998 Jul 29
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
74LVC373A
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
10
1998 Jul 29
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
74LVC373A
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
11
1998 Jul 29
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
74LVC373A
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 08-98
9397-750-04506
Document order number:
Philips
Semiconductors
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