74LVC38ABQ [NXP]
Quad 2-input NAND gate (open drain); 四2输入与非门（漏极开路）
| 型号： | 74LVC38ABQ |
| 厂家： | 
NXP |
| 描述： | Quad 2-input NAND gate (open drain) |
| 文件： | 总14页 (文件大小：98K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVC38A
Quad 2-input NAND gate (open
drain)
Product specification
2004 Mar 22
Supersedes data of 2004 Mar 10
Philips Semiconductors
Product specification
Quad 2-input NAND gate (open drain)
74LVC38A
FEATURES
DESCRIPTION
The 74LVC38A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
• 5 V tolerant inputs for interfacing with 5 V logic
• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
Inputs can be driven from either 3.3 or 5 V devices. This
feature allows the use of these devices as translators in a
mixed 3.3 and 5 V environment.
• Direct interface with TTL levels
• Open-drain outputs
• Inputs accept voltages up to 5.5 V
• Complies with JEDEC standard no. 8-1A
• Specified from −40 to +85 °C and −40 to +125 °C.
The 74LVC38A provides the 2-input NAND function.
The outputs of the 74LVC38A devices are open drain and
can be connected to other open-drain outputs to
implement active-LOW wired-OR or active-HIGH
wired-AND functions.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
tPZL
PARAMETER
CONDITIONS
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
TYPICAL
1.7
UNIT
propagation delay nA, nB to nY
propagation delay nA, nB to nY
input capacitance
ns
ns
pF
pF
tPLZ
CI
2.3
4.0
5.5
CPD
power dissipation capacitance per gate
VCC = 3.3 V; notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC
ORDERING INFORMATION
TYPE NUMBER
.
PACKAGE
TEMPERATURE RANGE
PINS
PACKAGE
MATERIAL
CODE
74LVC38AD
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
14
14
14
14
SO14
plastic
plastic
plastic
plastic
SOT108-1
SOT337-1
SOT402-1
SOT762-1
74LVC38ADB
74LVC38APW
74LVC38ABQ
SSOP14
TSSOP14
DHVQFN14
2004 Mar 22
2
Philips Semiconductors
Product specification
Quad 2-input NAND gate (open drain)
74LVC38A
FUNCTION TABLE
See note 1.
INPUTS
OUTPUTS
nA
nB
nY
L
L
L
H
L
Z
Z
Z
L
H
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level:
Z = high-impedance OFF-state.
PINNING
PIN
1
SYMBOL
DESCRIPTION
1A
1B
1Y
2A
2B
2Y
data input
data input
data output
data input
data input
data output
ground (0 V)
data output
data input
data input
data output
data input
data input
supply voltage
2
3
4
5
6
7
GND
3Y
8
9
3A
10
11
12
13
14
3B
4Y
4A
4B
VCC
2004 Mar 22
3
Philips Semiconductors
Product specification
Quad 2-input NAND gate (open drain)
74LVC38A
V
1A
1
handbook, halfpage
CC
14
handbook, halfpage
1A
1B
1
2
3
4
5
6
7
V
CC
14
13
12
11
10
9
1B
2
3
13 4B
12 4A
4B
4A
4Y
3B
3A
3Y
1Y
1Y
(1)
2A
2B
2Y
4
5
6
GND
11 4Y
10 3B
2A
38
2B
2Y
9
3A
8
GND
7
8
MNA696
GND 3Y
Top view
MNA977
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration SO14 and (T)SSOP14.
Fig.2 Pin configuration (DHVQFN14).
1
handbook, halfpage
&
&
&
&
3
6
2
handbook, halfpage
1
2
1A
1B
1Y
2Y
3Y
3
6
8
4
5
4
5
2A
2B
9
3A
3B
9
8
10
10
12
13
4A
4B
4Y 11
12
13
11
MNA697
MNA698
Fig.3 Logic symbol.
Fig.4 Logic symbol (IEEE/IEC).
2004 Mar 22
4
Philips Semiconductors
Product specification
Quad 2-input NAND gate (open drain)
74LVC38A
handbook, halfpage
A
Y
B
GND
MNA699
Fig.5 Logic diagram (one gate).
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
MAX.
3.6
UNIT
VCC
for maximum speed performance 2.7
V
for low-voltage applications
1.2
0
3.6
5.5
5.5
+125
20
V
VI
input voltage
V
VO
output voltage
0
V
Tamb
tr, tf
operating ambient temperature
input rise and fall times
−40
0
°C
VCC = 1.2 to 2.7 V
VCC = 2.7 to 3.6 V
ns/V
ns/V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+6.5
UNIT
VCC
IIK
V
input diode current
input voltage
VI < 0
note 1
VO < 0
note 1
−
−50
+6.5
−50
+6.5
50
mA
V
VI
−0.5
−
IOK
VO
IO
output diode current
output voltage
mA
V
−0.5
−
output sink current
VO = 0 to VCC
mA
mA
°C
ICC, IGND VCC or GND current
−
±100
+150
500
Tstg
Ptot
storage temperature
power dissipation
−65
−
Tamb = −40 to +125 °C; note 2
mW
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO14 packages: above 70 °C derate linearly with 8 mW/K.
For (T)SSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.
2004 Mar 22
5
Philips Semiconductors
Product specification
Quad 2-input NAND gate (open drain)
74LVC38A
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX. UNIT
OTHER
V
CC (V)
Tamb = −40 to +85 °C; note 1
VIH
VIL
HIGH-level input voltage
1.2
VCC
−
−
−
−
−
V
V
V
V
2.7 to 3.6 2.0
−
LOW-level input voltage
LOW-level output voltage
1.2
−
−
GND
0.8
2.7 to 3.6
VOL
VI = VIH or VIL
IO = 100 µA
IO = 12 mA
2.7 to 3.6
2.7
−
−
−
−
−
GND
−
0.20
0.40
0.55
±5
V
V
IO = 24 mA
3.0
−
V
ILI
input leakage current
VI = 5.5 V or GND
3.6
±0.1
0.1
µA
µA
IOZ
3-state output OFF-state
current
VI = VIH or VIL;
3.6
±10
VO = 5.5 V or GND
ICC
quiescent supply current
VI = VCC or GND; IO = 0 3.6
−
−
0.1
5
10
µA
µA
∆ICC
additional quiescent supply VI = VCC − 0.6 V; IO = 0
current per input pin
2.7 to 3.6
1.2
500
Tamb = −40 to +125 °C
VIH
HIGH-level input voltage
VCC
−
−
−
−
−
V
V
V
V
2.7 to 3.6 2.0
−
VIL
LOW-level input voltage
LOW-level output voltage
1.2
−
−
GND
0.8
2.7 to 3.6
VOL
VI = VIH or VIL
IO = 100 µA
2.7 to 3.6
2.7
−
−
−
−
−
−
−
−
−
−
0.3
0.6
0.8
±20
±20
V
IO = 12 mA
V
IO = 24 mA
3.0
V
ILI
input leakage current
VI = 5.5 V or GND
3.6
µA
µA
IOZ
3-state output OFF-state
current
VI = VIH or VIL;
3.6
VO = 5.5 V or GND
ICC
quiescent supply current
VI = VCC or GND; IO = 0 3.6
−
−
−
−
40
µA
µA
∆ICC
additional quiescent supply VI = VCC − 0.6 V; IO = 0
2.7 to 3.6
5000
current per input pin
Note
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
2004 Mar 22
6
Philips Semiconductors
Product specification
Quad 2-input NAND gate (open drain)
74LVC38A
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.5 ns.
TEST CONDITIONS
WAVEFORMS VCC (V)
SYMBOL
PARAMETER
MIN.
TYP
MAX.
UNIT
Tamb = −40 to +85 °C; note 1
tPZL
propagation delay nA, nB to nY see Figs 6 and 7
propagation delay nA, nB to nY see Figs 6 and 7
1.2
−
5.7
−
ns
2.7
0.5
0.5
−
1.7
1.7(2)
2.9
3.0
−
ns
ns
ns
ns
ns
ns
3.0 to 3.6
1.2
tPLZ
4.8
2.7
1.0
1.0
−
2.6
2.3(2)
3.8
3.6
1.0
3.0 to 3.6
tsk(0)
skew
note 3
−
Tamb = −40 to +125 °C
tPZL
propagation delay nA, nB to nY see Figs 6 and 7
propagation delay nA, nB to nY see Figs 6 and 7
1.2
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
2.7
0.5
0.5
−
4.0
4.0
−
3.0 to 3.6
1.2
tPLZ
2.7
1.0
1.0
−
5.0
4.5
1.5
3.0 to 3.6
tsk(0)
skew
note 3
Notes
1. All typical values are measured at Tamb = 25 °C.
2. These typical values are measured at VCC = 3.3 V.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed
by design.
2004 Mar 22
7
Philips Semiconductors
Product specification
Quad 2-input NAND gate (open drain)
74LVC38A
AC WAVEFORMS
V
I
(1)
nA, nB input
V
t
M
GND
t
PLZ
PZL
V
CC
(1)
nY output
V
M
(3)
(2)
V
V
X
OL
MNA700
(1) VM = 1.5 V at VCC ≥ 2.7 V.
VM = 0.5VCC at VCC < 2.7 V.
(2) VOL and VOH are typical output voltage drop that occur with the output load.
(3) X = VOL + 0.3 V at VCC ≥ 2.7 V.
VX = VOL + 0.15 V at VCC < 2.7 V.
V
Fig.6 The input nA, nB to output nY propagation delays.
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
R
R
L
L
T
MNA616
VCC
VEXT
2 × VCC
VI
CL
RL
1.2
VCC
30 pF
50 pF
50 pF
500 Ω(1)
500 Ω
2.7
6 V
6 V
2.7 V
2.7 V
3.3 to 3.6
500 Ω
Note
1. The circuit performs better when RL = 1000 Ω.
Definitions for test circuits:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
tr = tf ≤ 2.5 ns; when measuring fmax, there is no constraint on tr, tf with 50% duty factor.
Fig.7 Load circuitry for switching times.
8
2004 Mar 22
Philips Semiconductors
Product specification
Quad 2-input NAND gate (open drain)
74LVC38A
PACKAGE OUTLINES
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
2004 Mar 22
9
Philips Semiconductors
Product specification
Quad 2-input NAND gate (open drain)
74LVC38A
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
7
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.4
0.9
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT337-1
MO-150
2004 Mar 22
10
Philips Semiconductors
Product specification
Quad 2-input NAND gate (open drain)
74LVC38A
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
2004 Mar 22
11
Philips Semiconductors
Product specification
Quad 2-input NAND gate (open drain)
74LVC38A
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
e
e
1
y
D
D
E
L
v
w
y
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
2004 Mar 22
12
Philips Semiconductors
Product specification
Quad 2-input NAND gate (open drain)
74LVC38A
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2004 Mar 22
13
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R20/03/pp14
Date of release: 2004 Mar 22
Document order number: 9397 750 13029
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SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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