74LVC3G14DC,125 [NXP]
74LVC3G14 - Triple inverting Schmitt trigger with 5 V tolerant input SSOP 8-Pin;
| 型号： | 74LVC3G14DC,125 |
| 厂家： | 
NXP |
| 描述： | 74LVC3G14 - Triple inverting Schmitt trigger with 5 V tolerant input SSOP 8-Pin 栅 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总23页 (文件大小：296K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
Rev. 12 — 9 April 2013
Product data sheet
1. General description
The 74LVC3G14 provides three inverting buffers with Schmitt trigger input. It is capable of
transforming slowly changing input signals into sharply defined, jitter-free output signals.
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment. Schmitt trigger action at the inputs
makes the circuit tolerant of slower input rise and fall time. This device is fully specified for
partial power-down applications using IOFF. The IOFF circuitry disables the output,
preventing the damaging backflow current through the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Unlimited rise and fall times
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C.
3. Applications
Wave and pulse shaper for highly noisy environment
Astable multivibrator
Monostable multivibrator.
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC3G14DP 40 C to +125 C
74LVC3G14DC 40 C to +125 C
74LVC3G14GT 40 C to +125 C
74LVC3G14GF 40 C to +125 C
74LVC3G14GD 40 C to +125 C
74LVC3G14GM 40 C to +125 C
74LVC3G14GN 40 C to +125 C
74LVC3G14GS 40 C to +125 C
TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
SOT833-1
SOT1089
SOT996-2
SOT902-2
SOT1116
SOT1203
XSON8
XSON8
XSON8
XQFN8
XSON8
XSON8
plastic extremely thin small outline package; no leads;
8 terminals; body 1 1.95 0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35 1 0.5 mm
plastic extremely thin small outline package; no leads;
8 terminals; body 3 2 0.5 mm
plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 1.6 0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.2 1.0 0.35 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35 1.0 0.35 mm
5. Marking
Table 2.
Marking codes
Type number
74LVC3G14DP
74LVC3G14DC
74LVC3G14GT
74LVC3G14GF
74LVC3G14GD
74LVC3G14GM
74LVC3G14GN
74LVC3G14GS
Marking code[1]
V14
V14
V14
VK
V14
V14
VK
VK
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
74LVC3G14
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 12 — 9 April 2013
2 of 23
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
6. Functional diagram
1A
3Y
2A
1Y
3A
2Y
A
Y
001aah728
mna025
001aah729
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram
(one Schmitt trigger)
7. Pinning information
7.1 Pinning
74LVC3G14
1A
3Y
1
2
3
4
8
7
6
5
V
CC
1Y
3A
2Y
74LVC3G14
2A
1
2
3
4
8
7
6
5
1A
3Y
V
CC
1Y
3A
2Y
GND
2A
GND
001aab834
Transparent top view
001aag081
Fig 4. Pin configuration SOT505-2 and SOT765-1
Fig 5. Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
74LVC3G14
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 12 — 9 April 2013
3 of 23
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
74LVC3G14
terminal 1
index area
1Y
1
7
6
5
1A
3Y
2A
74LVC3G14
1A
3Y
1
2
3
4
8
7
6
5
V
CC
3A
2Y
2
3
1Y
3A
2Y
2A
GND
001aag082
001aai242
Transparent top view
Transparent top view
Fig 6. Pin configuration SOT996-2
Fig 7. Pin configuration SOT902-2
7.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT902-2
SOT996-2, SOT1116 and SOT1203
1A, 2A, 3A
1Y, 2Y, 3Y
GND
1, 3, 6
7, 5, 2
data input
7, 5, 2
1, 3, 6
data output
ground (0 V)
supply voltage
4
8
4
8
VCC
8. Functional description
Table 4.
Function table [1]
Input nA
Output nY
L
H
L
H
[1] H = HIGH voltage level; L = LOW voltage level
74LVC3G14
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 12 — 9 April 2013
4 of 23
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
9. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
0.5
50
0.5
-
Max
+6.5
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
VI
+6.5
50
VCC + 0.5
+6.5
50
100
-
IOK
output clamping current
output voltage
VO > VCC or VO < 0 V
Active mode
mA
V
[1][2]
[1][2]
VO
0.5
0.5
-
Power-down mode
VO = 0 V to VCC
V
IO
output current
mA
mA
mA
mW
C
ICC
IGND
Ptot
Tstg
supply current
-
ground current
100
-
[3]
total power dissipation
storage temperature
Tamb = 40 C to +125 C
250
+150
65
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
For XSON8 and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
10. Recommended operating conditions
Table 6.
Symbol
VCC
Operating conditions
Parameter
Conditions
Min
1.65
0
Max
5.5
Unit
V
supply voltage
input voltage
VI
5.5
V
VO
output voltage
Active mode
0
VCC
5.5
V
Power-down mode; VCC = 0 V
0
V
Tamb
ambient temperature
40
+125
C
74LVC3G14
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 12 — 9 April 2013
5 of 23
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
11. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ [1]
Max
Unit
Tamb = 40 C to +85 C
VOH
HIGH-level output voltage
VI = VT+ or VT
IO = 100 A; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VI = VT+ or VT
VCC 0.1 -
-
-
-
-
-
-
V
V
V
V
V
V
1.2
1.9
2.2
2.3
3.8
-
-
-
-
-
VOL
LOW-level output voltage
IO = 100 A; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
-
-
-
-
-
-
-
-
-
-
0.1
V
-
0.45
0.3
V
-
V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
VI or VO = 5.5 V; VCC = 0 V
-
0.4
V
-
0.55
0.55
5
V
-
V
II
input leakage current
power-off leakage current
supply current
0.1
0.1
0.1
A
A
A
IOFF
ICC
10
10
VI = 5.5 V or GND; IO = 0 A;
VCC = 1.65 V to 5.5 V
ICC
additional supply current
input capacitance
VI = VCC 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V
-
-
5
500
-
A
CI
VCC = 3.3 V; VI = GND to VCC
3.5
pF
Tamb = 40 C to +125 C
VOH HIGH-level output voltage
VI = VT+ or VT
IO = 100 A; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VI = VT+ or VT
VCC 0.1 -
-
-
-
-
-
-
V
V
V
V
V
V
0.95
1.7
1.9
2.0
3.4
-
-
-
-
-
VOL
LOW-level output voltage
IO = 100 A; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.7
0.45
0.6
0.8
0.8
20
V
V
V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
V
V
V
II
input leakage current
A
74LVC3G14
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 12 — 9 April 2013
6 of 23
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
IOFF power-off leakage current
ICC
Conditions
Min
Typ [1]
Max
20
40
Unit
A
VI or VO = 5.5 V; VCC = 0 V
-
-
-
-
supply current
VI = 5.5 V or GND; IO = 0 A;
VCC = 1.65 V to 5.5 V
A
ICC
additional supply current
VI = VCC 0.6 V; IO = 0 A;
-
-
5000
A
VCC = 2.3 V to 5.5 V
[1] All typical values are measured at maximum VCC and Tamb = 25 C.
Table 8.
Transfer characteristics
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 9
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
VT+
positive-going
see Figure 10 and
threshold voltage Figure 11
VCC = 1.8 V
0.70
1.00
1.30
1.90
2.20
1.10
1.40
1.76
2.47
2.91
1.50
1.80
2.20
3.10
3.60
0.70
1.00
1.30
1.90
2.20
1.70
2.00
2.40
3.30
3.80
V
VCC = 2.3 V
VCC = 3.0 V
V
V
V
V
VCC = 4.5 V
VCC = 5.5 V
VT
negative-going
see Figure 10 and
threshold voltage Figure 11
VCC = 1.8 V
0.25
0.40
0.60
1.00
1.20
0.61
0.80
1.04
1.55
1.86
0.90
1.15
1.50
2.00
2.30
0.25
0.40
0.60
1.00
1.20
1.10
1.35
1.70
2.20
2.50
V
V
V
V
V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
[2]
VH
hysteresis voltage see Figure 10, Figure 11
and Figure 12
VCC = 1.8 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
0.15
0.25
0.40
0.60
0.70
0.49
0.60
0.73
0.92
1.02
1.00
1.10
1.20
1.50
1.70
0.15
0.25
0.40
0.60
0.70
1.20
1.30
1.40
1.70
1.90
V
V
V
V
V
[1] All typical values are measured at Tamb = 25 C
[2] VH = VT+ VT
74LVC3G14
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 12 — 9 April 2013
7 of 23
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
12. Dynamic characteristics
Table 9.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.
Symbol Parameter Conditions 40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
[2]
tpd
propagation delay nA to nY; see Figure 8
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
1.0
0.5
0.5
0.5
0.5
-
4.2
3.0
3.8
11.0
6.5
7.0
6.0
4.3
-
1.0
0.5
0.5
0.5
0.5
-
12.0
7.2
7.7
6.7
4.7
-
ns
ns
ns
ns
ns
pF
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
3.2
2.4
18.1
VCC = 4.5 V to 5.5 V
[3]
CPD
power dissipation VI = GND to VCC; VCC = 3.3 V
capacitance
[1] Typical values are measured at Tamb = 25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL
.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
13. Waveforms
V
I
V
V
M
nA input
M
GND
t
t
PHL
PLH
V
OH
V
V
M
nY output
M
V
mna344
OL
Measurement points are given in Table 10. VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. The data input (nA) to output (nY) propagation delays
74LVC3G14
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 12 — 9 April 2013
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74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
Table 10. Measurement points
VCC
Input VM
0.5 VCC
0.5 VCC
1.5 V
Output VM
0.5 VCC
0.5 VCC
1.5 V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
1.5 V
0.5 VCC
0.5 VCC
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
mna616
Test data is given in Table 11. Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
EXT = External voltage for measuring switching times.
V
Fig 9. Test circuit for measuring switching times
Table 11. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr = tf
RL
tPLH, tPHL
open
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
VCC
2.0 ns
2.0 ns
2.5 ns
2.5 ns
2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 k
500
500
500
500
open
open
3.0 V to 3.6 V
4.5 V to 5.5 V
open
open
14. Waveforms transfer characteristics
V
T+
V
O
V
I
V
H
V
T−
V
O
V
I
mna208
V
H
V
V
T+
T−
mna207
VT+ and VT limits at 70 % and 20 %.
Fig 10. Transfer characteristic
Fig 11. Definition of VT+, VT and VH
74LVC3G14
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 12 — 9 April 2013
9 of 23
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
mdb627
14
12
I
CC
(mA)
10
8
6
4
2
0
0
0.5
1
1.5
2
V (V)
I
VCC = 3.0 V
Fig 12. Typical transfer characteristics
15. Application information
The slow input rise and fall times cause additional power dissipation, this can be
calculated using the following formula:
Padd = fi (tr ICC(AV) + tf ICC(AV)) VCC where:
Padd = additional power dissipation (W);
fi = input frequency (MHz);
tr = input rise time (ns); 10 % to 90 %;
tf = input fall time (ns); 90 % to 10 %;
ICC(AV) = average additional supply current (A).
ICC(AV) differs with positive or negative input transitions, as shown in Figure 13.
An example of a relaxation circuit using the 74LVC3G14 is shown in Figure 14.
74LVC3G14
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 12 — 9 April 2013
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74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
mnb086
50
ΔI
(mA)
CC(AV)
(1)
40
30
20
(2)
10
0
2
3
4
5
6
V
CC
(V)
Linear change of VI between 0.8 V to 2.0 V. All values given are typical unless otherwise specified.
(1) Positive-going edge.
(2) Negative-going edge.
Fig 13. ICC(AV) as a function of VCC
R
C
mna035
1
T
1
-- ---------------------
f =
0.8 RC
Fig 14. Relaxation oscillator
74LVC3G14
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 12 — 9 April 2013
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74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
16. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.65
0.25
0.5
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
Fig 15. Package outline SOT505-2 (TSSOP8)
74LVC3G14
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 12 — 9 April 2013
12 of 23
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
Fig 16. Package outline SOT765-1 (VSSOP8)
74LVC3G14
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Product data sheet
Rev. 12 — 9 April 2013
13 of 23
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
b
1
2
3
4
4×
(2)
L
L
1
e
8
7
6
5
e
1
e
1
e
1
8×
A
(2)
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
1
L
L
1
max max
0.25
0.17
2.0
1.9
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
- - -
07-11-14
07-12-07
SOT833-1
- - -
MO-252
Fig 17. Package outline SOT833-1 (XSON8)
74LVC3G14
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Product data sheet
Rev. 12 — 9 April 2013
14 of 23
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1 x 0.5 mm
SOT1089
E
terminal 1
index area
D
A
A
1
detail X
(2)
(4×)
e
L
(2)
(8×)
b
4
5
e
1
1
8
terminal 1
index area
L
1
X
0
0.5
1 mm
scale
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
L
1
1
max 0.5 0.04 0.20 1.40 1.05
0.35 0.40
0.15 1.35 1.00 0.55 0.35 0.30 0.35
0.12 1.30 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1089_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
10-04-09
10-04-12
SOT1089
MO-252
Fig 18. Package outline SOT1089 (XSON8)
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Product data sheet
Rev. 12 — 9 April 2013
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74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
XSON8: plastic extremely thin small outline package; no leads;
8 terminals; body 3 x 2 x 0.5 mm
SOT996-2
D
B
A
E
A
A
1
detail X
terminal 1
index area
e
1
C
v
C
C
A
B
b
e
L
1
y
1
y
w
C
1
4
L
2
L
8
5
X
0
1
2 mm
scale
Dimensions (mm are the original dimensions)
(1)
Unit
A
A
1
b
D
E
e
e
1
L
L
1
L
2
v
w
y
y
1
max
mm nom 0.5
min
0.05 0.35 2.1 3.1
0.00 0.15 1.9 2.9
0.5 0.15 0.6
0.3 0.05 0.4
0.5 1.5
0.1 0.05 0.05 0.1
sot996-2_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
07-12-21
12-11-20
SOT996-2
Fig 19. Package outline SOT996-2 (XSON8)
74LVC3G14
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Product data sheet
Rev. 12 — 9 April 2013
16 of 23
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
XQFN8: plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 x 1.6 x 0.5 mm
SOT902-2
X
D
B
A
terminal 1
index area
E
A
A
1
detail X
e
C
v
C
C
A
B
b
y
y
w
C
1
4
3
2
5
e
1
6
7
1
terminal 1
index area
8
L
metal area
not for soldering
L
1
0
1
2 mm
scale
Dimensions
(1)
Unit
A
A
1
b
D
E
e
e
1
L
L
v
w
y
y
1
1
max 0.5 0.05 0.25 1.65 1.65
0.35 0.15
0.20 1.60 1.60 0.55 0.5 0.30 0.10 0.1 0.05 0.05 0.05
0.00 0.15 1.55 1.55 0.25 0.05
mm nom
min
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot902-2_po
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
JEITA
- - -
10-11-02
11-03-31
SOT902-2
MO-255
Fig 20. Package outline SOT902-2 (XQFN8)
74LVC3G14
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Product data sheet
Rev. 12 — 9 April 2013
17 of 23
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.2 x 1.0 x 0.35 mm
SOT1116
b
(2)
1
2
3
4
(4×)
L
L
1
e
8
7
6
5
e
1
e
1
e
1
(2)
(8×)
A
1
A
D
E
terminal 1
index area
0
0.5
scale
1 mm
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
L
1
1
max 0.35 0.04 0.20 1.25 1.05
0.35 0.40
0.15 1.20 1.00 0.55 0.3 0.30 0.35
0.12 1.15 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1116_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
10-04-02
10-04-07
SOT1116
Fig 21. Package outline SOT1116 (XSON8)
74LVC3G14
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Product data sheet
Rev. 12 — 9 April 2013
18 of 23
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1.0 x 0.35 mm
SOT1203
b
(2)
(4×)
1
2
3
4
L
L
1
e
8
7
6
5
e
1
e
1
e
1
(2)
(8×)
A
1
A
D
E
terminal 1
index area
0
L
0.5
scale
1 mm
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
1
1
max 0.35 0.04 0.20 1.40 1.05
0.35 0.40
0.15 1.35 1.00 0.55 0.35 0.30 0.35
0.12 1.30 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1203_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
10-04-02
10-04-06
SOT1203
Fig 22. Package outline SOT1203 (XSON8)
74LVC3G14
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Product data sheet
Rev. 12 — 9 April 2013
19 of 23
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
17. Abbreviations
Table 12. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
Ultra-Thin Leadless Package
UTLP
18. Revision history
Table 13. Revision history
Document ID
Release date
20130409
Data sheet status
Change notice
Supersedes
74LVC3G14 v.12
Modifications:
Product data sheet
-
74LVC3G14 v.11
• For type number 74LVC3G14GD XSON8U has changed to XSON8.
20120706 Product data sheet 74LVC3G14 v.10
• For type number 74LVC3G14GM the SOT code has changed to SOT902-2.
74LVC3G14 v.11
Modifications:
-
74LVC3G14 v.10
Modifications:
20111123
Product data sheet
-
74LVC3G14 v.9
• Legal pages updated.
74LVC3G14 v.9
74LVC3G14 v.8
74LVC3G14 v.7
74LVC3G14 v.6
74LVC3G14 v.5
74LVC3G14 v.4
74LVC3G14 v.3
74LVC3G14 v.2
74LVC3G14 v.1
20110922
20100819
20080612
20080207
20071005
20070314
20050131
20041027
20040510
Product data sheet
-
-
-
-
-
-
-
-
-
74LVC3G14 v.8
74LVC3G14 v.7
74LVC3G14 v.6
74LVC3G14 v.5
74LVC3G14 v.4
74LVC3G14 v.3
74LVC3G14 v.2
74LVC3G14 v.1
-
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product data sheet
74LVC3G14
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Product data sheet
Rev. 12 — 9 April 2013
20 of 23
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
19.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74LVC3G14
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Product data sheet
Rev. 12 — 9 April 2013
21 of 23
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC3G14
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Product data sheet
Rev. 12 — 9 April 2013
22 of 23
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
21. Contents
1
2
3
4
5
6
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Waveforms transfer characteristics. . . . . . . . . 9
Application information. . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20
9
10
11
12
13
14
15
16
17
18
19
Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
19.1
19.2
19.3
19.4
20
21
Contact information. . . . . . . . . . . . . . . . . . . . . 22
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 April 2013
Document identifier: 74LVC3G14
相关型号：
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