74LVC4066D-Q100J [NXP]
74LVC4066-Q100 - Quad bilateral switch SOIC 14-Pin;型号: | 74LVC4066D-Q100J |
厂家: | NXP |
描述: | 74LVC4066-Q100 - Quad bilateral switch SOIC 14-Pin 光电二极管 |
文件: | 总23页 (文件大小:195K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74LVC4066-Q100
Quad bilateral switch
Rev. 1 — 7 August 2012
Product data sheet
1. General description
The 74LVC4066-Q100 is a high-speed Si-gate CMOS device.
The 74LVC4066-Q100 provides four single pole, single-throw analog switch functions.
Each switch has two input/output terminals (nY and nZ) and an active HIGH enable input
(nE). When nE is LOW, the analog switch is turned off.
Schmitt-trigger action at the enable inputs makes the circuit tolerant of slower input rise
and fall times across the entire VCC range from 1.65 V to 5.5 V.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide supply voltage range from 1.65 V to 5.5 V
Very low ON resistance:
7.5 (typical) at VCC = 2.7 V
6.5 (typical) at VCC = 3.3 V
6 (typical) at VCC = 5 V
Switch current capability of 32 mA
High noise immunity
CMOS low-power consumption
Direct interface TTL-levels
Latch-up performance exceeds 250 mA
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Enable inputs accept voltages up to 5 V
Multiple package options
74LVC4066-Q100
NXP Semiconductors
Quad bilateral switch
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC4066D-Q100
40 C to +125 C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LVC4066PW-Q100 40 C to +125 C
74LVC4066BQ-Q100 40 C to +125 C
TSSOP14
plastic thin small outline package; 14 leads;
body width 4.4 mm
SOT402-1
DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1
very thin quad flat package; no leads;
14 terminals; body 2.5 3 0.85 mm
4. Functional diagram
1
1Y
1Z
2
1
2
3
1
1
1
1
1
13
#
#
#
#
X1
13 1E
1
2
3
13
#
#
#
#
4
5
4
5
8
2Y
2E
3Y
3E
2Z
3Z
3
9
1
4
5
X1
8
6
9
1
8
6
9
X1
6
11
12
11
12
10
11
12
10
1
4Z 10
4Y
4E
X1
(a)
(b)
mnb111
mnb112
Fig 1. Logic symbol
Fig 2. Logic symbol (IEEE/IEC)
nZ
nY
nE
V
CC
mna658
Fig 3. Logic diagram (one switch)
74LVC4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
2 of 23
74LVC4066-Q100
NXP Semiconductors
Quad bilateral switch
5. Pinning information
5.1 Pinning
ꢀꢁꢂꢃꢄꢁꢅꢆꢆꢇꢈꢉꢅꢅ
ꢀꢁꢂꢃꢄꢁꢅꢆꢆꢇꢈꢉꢅꢅ
ꢇꢆꢁ#ꢋꢃꢂ$ꢈꢓ
ꢋꢃ%ꢆ&ꢈꢂꢁꢆꢂ
ꢀ
ꢆ
ꢈ
ꢇ
ꢌ
ꢍ
ꢎ
ꢀꢇ
ꢀꢈ
ꢀꢆ
ꢀꢀ
ꢀꢐ
ꢑ
ꢀꢁ
ꢀꢄ
ꢂ
ꢃꢃ
ꢀꢅ
ꢇꢅ
ꢇꢁ
ꢇꢄ
ꢈꢄ
ꢈꢁ
ꢐ
ꢍ
ꢑ
ꢝ
ꢛ
ꢓꢍ
ꢓꢐ
ꢓꢓ
ꢓ
ꢜ
ꢓꢏ
ꢓꢎ
ꢑꢎ
ꢑꢒ
ꢑꢏ
ꢍꢏ
ꢐꢏ
ꢐꢒ
ꢐꢎ
ꢍꢎ
ꢆꢄ
ꢆꢁ
ꢗꢓꢘ
ꢔꢕꢖ
ꢆꢅ
ꢈꢅ
ꢀꢀꢀꢁꢂꢂꢃꢄꢅꢇ
ꢏ
ꢉꢊꢋ
ꢀꢁꢂꢃꢄꢅꢂꢁꢆꢃꢇꢈꢇꢉꢅꢈꢊꢋꢆꢌ
ꢀꢀꢀꢁꢂꢂꢃꢄꢅꢆ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4. Pin configuration for SO14 and TSSOP14
Fig 5. Pin configuration for DHVQFN14
5.2 Pin description
Table 2.
Symbol
1Y
Pin description
Pin
1
Description
independent input/output
independent output/input
independent output/input
independent input/output
1Z
2
2Z
3
2Y
4
2E
5
enable input (active HIGH)
enable input (active HIGH)
ground (0 V)
3E
6
GND
3Y
7
8
independent input/output
independent output/input
independent output/input
independent input/output
enable input (active HIGH)
enable input (active HIGH)
supply voltage
3Z
9
4Z
10
11
12
13
14
4Y
4E
1E
VCC
74LVC4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
3 of 23
74LVC4066-Q100
NXP Semiconductors
Quad bilateral switch
6. Functional description
Table 3.
Function table[1]
Input nE
Switch
OFF
L
H
ON
[1] H = HIGH voltage level;
L = LOW voltage level.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
0.5
0.5
50
-
Max
+6.5
+6.5
-
Unit
V
supply voltage
[1]
[2]
input voltage
V
IIK
input clamping current
switch clamping current
switch voltage
VI < 0.5 V or VI < VCC + 0.5 V
VI < 0.5 V or VI < VCC + 0.5 V
enable and disable mode
mA
mA
V
ISK
50
+6.5
50
100
-
VSW
ISW
0.5
-
switch current
0.5 < VSW < VCC + 0.5 V
mA
mA
mA
C
ICC
supply current
-
IGND
Tstg
Ptot
ground current
100
65
-
storage temperature
total power dissipation
+150
500
[3]
Tamb = 40 C to +125 C
mW
[1] The minimum input voltage rating may be exceeded if the input current rating is observed.
[2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed.
[3] For SO14 packages: above 70 C derate linearly with 8 mW/K.
For TSSOP14 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 C derate linearly with 4.5 mW/K.
74LVC4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
4 of 23
74LVC4066-Q100
NXP Semiconductors
Quad bilateral switch
8. Recommended operating conditions
Table 5.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
5.5
Unit
V
supply voltage
1.65
-
-
-
-
-
-
VI
input voltage
0
5.5
V
[1]
VSW
switch voltage
0
VCC
+125
20
V
Tamb
ambient temperature
input transition rise and fall rate
40
C
[2]
[2]
t/V
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
-
-
ns/V
ns/V
10
[1] To avoid sinking GND current from terminal nZ when switch current flows in terminal nY, the voltage drop across the bidirectional switch
must not exceed 0.4 V. If the switch current flows into terminal nZ, no GND current flows from terminal nY. In this case, there is no limit
for the voltage drop across the switch.
[2] Applies to control signal levels.
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
VIH
HIGH-level
input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.65VCC
-
-
0.65VCC
-
V
V
V
V
V
V
V
V
A
1.7
-
-
1.7
-
-
2.0
-
-
-
2.0
0.7VCC
-
0.7VCC
-
VIL
LOW-level
input voltage
-
-
-
-
-
-
0.35VCC
0.7
-
-
-
-
-
0.35VCC
0.7
-
-
-
0.8
0.8
0.3VCC
5
0.3VCC
20
[2]
[2]
II
input leakage pin nE; VCC = 5.5 V;
current
0.1
VI = 5.5 V or GND
IS(OFF)
OFF-state
leakage
current
VSW = VCC GND; VCC = 5.5 V;
see Figure 6
-
-
0.1
0.1
5
5
-
-
20
20
40
A
A
A
[2]
IS(ON)
ON-state
leakage
current
VSW = VCC GND; VCC = 5.5 V;
see Figure 7
[2]
[2]
ICC
supply current VI = VCC or GND; VSW = GND or
VCC; VCC = 5.5 V
-
-
0.1
5
10
-
-
ICC
additional
pin nE; VI = VCC 0.6 V; VCC = 5.5 V;
500
5000 A
supply current VSW = GND or VCC
74LVC4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
5 of 23
74LVC4066-Q100
NXP Semiconductors
Quad bilateral switch
Table 6.
Static characteristics …continued
At recommended operating conditions voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
CI
input
capacitance
-
-
-
12.5
-
-
-
-
-
pF
pF
pF
CS(OFF) OFF-state
capacitance
8.0
-
-
-
-
CS(ON)
ON-state
14.0
capacitance
[1] All typical values are measured at Tamb = 25 C.
[2] These typical values are measured at VCC = 3.3 V.
9.1 Test circuits
V
CC
V
CC
nE
nZ
nE
nZ
V
V
IH
IL
nY
nY
I
I
S
S
GND
GND
V
V
V
V
O
I
O
I
001aag488
001aag489
VI = VCC or GND and VO = GND or VCC
.
VI = VCC or GND and VO = open circuit.
Fig 6. Test circuit for measuring OFF-state leakage
current
Fig 7. Test circuit for measuring ON-state leakage
current
9.2 ON resistance
Table 7.
ON resistance
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 9 to Figure 14.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
RON(peak) ON resistance (peak) VI = GND to VCC; see Figure 8
ISW = 4 mA;
-
34.0
130
-
195
VCC = 1.65 V to 1.95 V
ISW = 8 mA; VCC = 2.3 V to 2.7 V
ISW = 12 mA; VCC = 2.7 V
-
-
-
-
12.0
10.4
7.8
30
25
20
15
-
-
-
-
45
38
30
23
ISW = 24 mA; VCC = 3 V to 3.6 V
ISW = 32 mA; VCC = 4.5 V to 5.5 V
6.2
74LVC4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
6 of 23
74LVC4066-Q100
NXP Semiconductors
Quad bilateral switch
Table 7.
ON resistance …continued
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 9 to Figure 14.
Symbol Parameter
Conditions
40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
RON(rail)
ON resistance (rail)
VI = GND; see Figure 8
ISW = 4 mA;
-
8.2
18
-
27
VCC = 1.65 V to 1.95 V
ISW = 8 mA; VCC = 2.3 V to 2.7 V
ISW = 12 mA; VCC = 2.7 V
ISW = 24 mA; VCC = 3 V to 3.6 V
ISW = 32 mA; VCC = 4.5 V to 5.5 V
VI = VCC; see Figure 8
-
-
-
-
7.1
6.9
6.5
5.8
16
14
12
10
-
-
-
-
24
21
18
15
ISW = 4 mA;
-
10.4
30
-
45
VCC = 1.65 V to 1.95 V
ISW = 8 mA; VCC = 2.3 V to 2.7 V
ISW = 12 mA; VCC = 2.7 V
-
-
-
-
7.6
7.0
6.1
4.9
20
18
15
10
-
-
-
-
30
27
23
15
ISW = 24 mA; VCC = 3 V to 3.6 V
ISW = 32 mA; VCC = 4.5 V to 5.5 V
VI = GND to VCC
[2]
RON(flat)
ON resistance
(flatness)
ISW = 4 mA;
-
26.0
-
-
-
VCC = 1.65 V to 1.95 V
I
SW = 8 mA; VCC = 2.3 V to 2.7 V
-
-
-
-
5.0
3.5
2.0
1.5
-
-
-
-
-
-
-
-
-
-
-
-
ISW = 12 mA; VCC = 2.7 V
ISW = 24 mA; VCC = 3 V to 3.6 V
ISW = 32 mA; VCC = 4.5 V to 5.5 V
[1] Typical values are measured at Tamb = 25 C and nominal VCC
.
[2] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
74LVC4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
7 of 23
74LVC4066-Q100
NXP Semiconductors
Quad bilateral switch
9.3 ON resistance test circuit and graphs
mna673
40
R
ON
(Ω)
30
V
SW
(1)
20
10
0
V
CC
nE
nY
(2)
(3)
V
IH
nZ
(4)
(5)
4
GND
V
I
I
SW
0
1
2
3
5
V (V)
I
001aag490
RON = VSW / ISW
.
(1) VCC = 1.8 V.
(2) CC = 2.5 V.
V
(3) VCC = 2.7 V.
(4) VCC = 3.3 V.
(5)
VCC = 5.0 V.
Fig 8. Test circuit for measuring ON resistance
Fig 9. Typical ON resistance as a function of input
voltage; Tamb = 25 C
001aaa712
001aaa708
55
15
R
ON
R
ON
(Ω)
(Ω)
45
13
35
25
15
5
11
9
(4)
(3)
(2)
(1)
(1)
(2)
(3)
(4)
7
5
0
0.4
0.8
1.2
1.6
2.0
0
0.5
1.0
1.5
2.0
2.5
V (V)
I
V (V)
I
(1) Tamb = 125 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(1) Tamb = 125 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(4)
Tamb = 40 C.
(4) Tamb = 40 C.
Fig 10. ON resistance as a function of input voltage;
VCC = 1.8 V
Fig 11. ON resistance as a function of input voltage;
VCC = 2.5 V
74LVC4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
8 of 23
74LVC4066-Q100
NXP Semiconductors
Quad bilateral switch
001aaa709
001aaa710
13
10
R
(Ω)
ON
R
(Ω)
ON
11
8
6
4
(1)
(1)
(2)
9
7
5
(2)
(3)
(3)
(4)
(4)
0
0.5
1.0
1.5
2.0
2.5 3.0
V (V)
I
0
1
2
3
4
V (V)
I
(1) Tamb = 125 C.
(2) amb = 85 C.
(1) Tamb = 125 C.
(2) amb = 85 C.
T
T
(3) Tamb = 25 C.
(4) Tamb = 40 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
Fig 12. ON resistance as a function of input voltage;
VCC = 2.7 V
Fig 13. ON resistance as a function of input voltage;
VCC = 3.3 V
001aaa711
7
R
ON
(Ω)
6
5
4
3
(1)
(2)
(3)
(4)
0
1
2
3
4
5
V (V)
I
(1) Tamb = 125 C.
(2) amb = 85 C.
T
(3) Tamb = 25 C.
(4) Tamb = 40 C.
Fig 14. ON resistance as a function of input voltage; VCC = 5.0 V
74LVC4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
9 of 23
74LVC4066-Q100
NXP Semiconductors
Quad bilateral switch
10. Dynamic characteristics
Table 8.
Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit Figure 17.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
[2][3]
tpd
propagation delay nY to nZ or nZ to nY;
see Figure 15
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
-
-
-
-
-
0.8
0.4
0.4
0.3
0.2
2.0
1.2
1.0
0.8
0.6
-
-
-
-
-
3.0
2.0
1.5
1.5
1.0
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
[4]
[5]
[6]
ten
enable time
nE to nY or nZ; see Figure 16
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.0
1.0
1.0
1.0
1.0
5.3
3.0
2.6
2.5
1.9
10
1.0
1.0
1.0
1.0
1.0
12.5
7.0
6.5
5.5
5.0
ns
ns
ns
ns
ns
5.6
5.0
4.4
3.9
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
nE to nY or nZ; see Figure 16
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
tdis
disable time
1.0
1.0
1.0
1.0
1.0
4.2
2.4
3.6
3.4
2.5
9.0
5.5
6.5
6.0
5.0
1.0
1.0
1.0
1.0
1.0
11.5
7.0
8.5
7.5
6.5
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
CPD
power dissipation CL = 50 pF; fi = 10 MHz;
capacitance
VI = GND to VCC
VCC = 2.5 V
-
-
-
11.0
12.5
15.6
-
-
-
-
-
-
-
-
-
pF
pF
pF
VCC = 3.3 V
VCC = 5.0 V
[1] Typical values are measured at Tamb = 25 C and nominal VCC
.
[2] tpd is the same as tPLH and tPHL
.
[3] Propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when
driven by an ideal voltage source (zero output impedance).
[4] ten is the same as tPZH and tPZL
[5] tdis is the same as tPLZ and tPHZ
[6] PD is used to determine the dynamic power dissipation (PD in W).
.
.
C
PD = CPD VCC2 fi N + {(CL + CS(ON)) VCC2 fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
CS(ON) = maximum ON-state switch capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
{(CL + CS(ON)) VCC2 fo} = sum of the outputs.
74LVC4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
10 of 23
74LVC4066-Q100
NXP Semiconductors
Quad bilateral switch
10.1 Waveforms and test circuit
V
I
nY or nZ
input
V
V
M
M
GND
t
t
PLH
PHL
V
OH
nZ or nY
output
V
V
M
M
V
OL
001aaa541
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 15. Input (nY or nZ) to output (nZ or nY) propagation delays
V
I
nE input
V
M
GND
t
t
PZL
PLZ
V
CC
output
nY or nZ
nY or nZ
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
switch
enabled
switch
enabled
switch
disabled
001aaa542
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 16. Enable and disable times
Table 9. Measurement points
Supply voltage
VCC
Input
VM
Output
VM
VX
VY
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5VCC
0.5VCC
1.5 V
1.5 V
0.5VCC
0.5 VCC
0.5VCC
1.5 V
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
VOL + 0.3 V
VOH 0.15 V
VOH 0.15 V
VOH 0.3 V
VOH 0.3 V
VOH 0.3 V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
0.5VCC
74LVC4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
11 of 23
74LVC4066-Q100
NXP Semiconductors
Quad bilateral switch
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
mna616
Test data is given in Table 10.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
VEXT = External voltage for measuring switching times.
Fig 17. Load circuit for switching times
Table 10. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPZH, tPHZ
GND
tPZL, tPLZ
2VCC
2VCC
6 V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
VCC
2.0 ns
2.0 ns
2.5 ns
2.5 ns
2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 k
500
500
500
500
open
GND
open
GND
3.0 V to 3.6 V
4.5 V to 5.5 V
open
GND
6 V
open
GND
2VCC
10.2 Additional dynamic characteristics
Table 11. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
THD
total harmonic distortion
RL = 10 k; CL = 50 pF; fi = 1 kHz;
see Figure 18
VCC = 1.65 V
VCC = 2.3 V
VCC = 3 V
-
-
-
-
0.032
0.008
0.006
0.005
-
-
-
-
%
%
%
%
VCC = 4.5 V
RL = 10 k; CL = 50 pF; fi = 10 kHz;
see Figure 18
VCC = 1.65 V
VCC = 2.3 V
VCC = 3 V
-
-
-
-
0.068
0.009
0.008
0.006
-
-
-
-
%
%
%
%
VCC = 4.5 V
74LVC4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
12 of 23
74LVC4066-Q100
NXP Semiconductors
Quad bilateral switch
Table 11. Additional dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
f(|-3dB)
|-3 dB frequency response RL = 600 ; CL = 50 pF;
see Figure 19
VCC = 1.65 V
VCC = 2.3 V
VCC = 3 V
-
-
-
-
170
210
212
215
-
-
-
-
MHz
MHz
MHz
MHz
VCC = 4.5 V
RL = 50 ; CL = 5 pF; see Figure 19
VCC = 1.65 V
VCC = 2.3 V
VCC = 3 V
-
-
-
-
> 500
> 500
> 500
> 500
-
-
-
-
MHz
MHz
MHz
MHz
VCC = 4.5 V
iso
isolation (OFF-state)
RL = 600 ; CL = 50 pF; fi = 1 MHz;
see Figure 20
VCC = 1.65 V
VCC = 2.3 V
VCC = 3 V
-
-
-
-
46
46
46
46
-
-
-
-
dB
dB
dB
dB
VCC = 4.5 V
RL = 50 ; CL = 5 pF; fi = 1 MHz; see
Figure 20
VCC = 1.65 V
VCC = 2.3 V
VCC = 3 V
-
-
-
-
42
42
42
42
-
-
-
-
dB
dB
dB
dB
VCC = 4.5 V
Vct
crosstalk voltage
between digital inputs and switch;
RL = 600 ; CL = 50 pF; fi = 1 MHz;
tr = tf = 2 ns; see Figure 21
VCC = 1.65 V
VCC = 2.3 V
VCC = 3 V
-
-
-
-
69
-
-
-
-
mV
mV
mV
mV
87
156
302
VCC = 4.5 V
Xtalk
crosstalk
between switches; RL = 600 ;
CL = 50 pF; fi = 1 MHz; see Figure 22
VCC = 1.65 V
VCC = 2.3 V
VCC = 3 V
-
-
-
-
58
58
58
58
-
-
-
-
dB
dB
dB
dB
VCC = 4.5 V
between switches; RL = 50 ;
CL = 5 pF; fi = 1 MHz; see Figure 22
VCC = 1.65 V
VCC = 2.3 V
VCC = 3 V
-
-
-
-
58
58
58
58
-
-
-
-
dB
dB
dB
dB
VCC = 4.5 V
74LVC4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
13 of 23
74LVC4066-Q100
NXP Semiconductors
Quad bilateral switch
Table 11. Additional dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Qinj
charge injection
CL = 0.1 nF; Vgen = 0 V; Rgen = 0 ;
fi = 1 MHz; RL = 1 M; see Figure 23
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 5.5 V
-
-
-
-
-
3.3
4.1
5.0
6.4
7.5
-
-
-
-
-
pC
pC
pC
pC
pC
10.2.1 Test circuits
V
0.5V
CC
CC
nE
V
R
L
IH
10 μF
nY/nZ
nZ/nY
V
O
f
600 Ω
C
L
D
i
001aag492
Test conditions:
VCC = 1.65 V: Vi = 1.4 V (p-p).
V
CC = 2.3 V: Vi = 2 V (p-p).
VCC = 3 V: Vi = 2.5 V (p-p).
VCC = 4.5 V: Vi = 4 V (p-p).
Fig 18. Test circuit for measuring total harmonic distortion
V
0.5V
CC
CC
nE
V
R
L
IH
0.1 μF
50 Ω
nY/nZ
nZ/nY
V
O
f
C
L
dB
i
001aag491
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3 dB.
Fig 19. Test circuit for measuring the frequency response when switch is in ON-state
74LVC4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
14 of 23
74LVC4066-Q100
NXP Semiconductors
Quad bilateral switch
0.5V
V
0.5V
CC
CC
CC
nE
R
L
V
R
L
IL
0.1 μF
nY/nZ
nZ/nY
V
O
f
50 Ω
C
L
dB
i
001aag493
Adjust fi voltage to obtain 0 dBm level at input.
Fig 20. Test circuit for measuring isolation (OFF-state)
V
CC
nE
nY/nZ
nZ/nY
V
O
logic
input
G
R
L
C
L
50 Ω
600 Ω
0.5V
0.5V
001aag494
CC
CC
Fig 21. Test circuit for measuring crosstalk voltage (between digital inputs and switch)
0.5V
CC
1E
V
IH
R
L
0.1 μF
50 Ω
R
i
1Y or 1Z
1Z or 1Y
600 Ω
CHANNEL
ON
C
50 pF
L
f
V
O1
i
0.5V
CC
2E
V
R
L
IL
2Y or 2Z
2Z or 2Y
CHANNEL
OFF
C
50 pF
L
R
600 Ω
i
V
O2
001aag496
20 log10 (VO2 / VO1) or 20 log10 (VO1 / VO2).
Fig 22. Test circuit for measuring crosstalk between switches
74LVC4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
15 of 23
74LVC4066-Q100
NXP Semiconductors
Quad bilateral switch
V
CC
nE
R
gen
nY/nZ
nZ/nY
V
O
R
1 MΩ
C
L
0.1 nF
G
logic
input
L
V
gen
001aag495
logic
input (nE)
off
on
off
V
O
ΔV
O
mna675
Qinj = VO CL.
VO = output voltage variation.
gen = generator resistance.
Vgen = generator voltage.
R
Fig 23. Test circuit for measuring charge injection
74LVC4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
16 of 23
74LVC4066-Q100
NXP Semiconductors
Quad bilateral switch
11. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
v
c
y
H
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 24. Package outline SOT108-1 (SO14)
74LVC4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
17 of 23
74LVC4066-Q100
NXP Semiconductors
Quad bilateral switch
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 25. Package outline SOT402-1 (TSSOP14)
74LVC4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
18 of 23
74LVC4066-Q100
NXP Semiconductors
Quad bilateral switch
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
e
e
1
y
D
D
E
L
v
w
y
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
Fig 26. Package outline SOT762-1 (DHVQFN14)
74LVC4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
19 of 23
74LVC4066-Q100
NXP Semiconductors
Quad bilateral switch
12. Abbreviations
Table 12. Abbreviations
Acronym
CMOS
TTL
Description
Complementary Metal Oxide Semiconductor
Transistor-Transistor Logic
Human Body Model
HBM
ESD
ElectroStatic Discharge
Machine Model
MM
DUT
Device Under Test
MIL
Military
13. Revision history
Table 13. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVC4066_Q100 v.1 20120807
Product data sheet
-
-
74LVC4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
20 of 23
74LVC4066-Q100
NXP Semiconductors
Quad bilateral switch
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
14.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
14.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74LVC4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
21 of 23
74LVC4066-Q100
NXP Semiconductors
Quad bilateral switch
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC4066_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
22 of 23
74LVC4066-Q100
NXP Semiconductors
Quad bilateral switch
16. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
7
8
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
9
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance test circuit and graphs. . . . . . . . 8
9.1
9.2
9.3
10
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms and test circuit . . . . . . . . . . . . . . . 11
Additional dynamic characteristics . . . . . . . . . 12
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
10.1
10.2
10.2.1
11
12
13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20
14
Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
14.1
14.2
14.3
14.4
15
16
Contact information. . . . . . . . . . . . . . . . . . . . . 22
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 August 2012
Document identifier: 74LVC4066_Q100
相关型号:
©2020 ICPDF网 联系我们和版权申明