74LVC4245APWDH-T [NXP]
IC LVC/LCX/Z SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, Bus Driver/Transceiver;
| 型号： | 74LVC4245APWDH-T |
| 厂家： | 
NXP |
| 描述： | IC LVC/LCX/Z SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, Bus Driver/Transceiver |
| 文件： | 总16页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVC4245A
Octal dual supply translating
transceiver; 3-state
1999 Jun 15
Product specification
Supersedes data of 1998 Jul 29
File under Integrated Circuits, IC24
Philips Semiconductors
Product specification
Octal dual supply translating transceiver; 3-state
74LVC4245A
FEATURES
DESCRIPTION
• In accordance with JEDEC
standard no. 8-1A
The 74LVC4245A is a high-performance, low-power, low-voltage, Si-gate
CMOS device, superior to most advanced CMOS compatible TTL families.
• Wide supply voltage range:
3 V port: 1.5 to 3.6 V
The 74LVC4245A is an octal dual supply translating transceiver featuring
non-inverting 3-state bus compatible outputs in both send and receive
directions. It is designed to interface between a 3 and 5 V bus in a mixed 3/5 V
supply environment.
5 V port: 1.5 to 5.5 V
• CMOS low power consumption
• Direct interface with TTL levels
The 74LVC4245A features an output enable (OE) input for easy cascading and
a send/receive (DIR) input for direction control. (OE) controls the outputs so
that the buses are effectively isolated.
• Control inputs accept voltages up
to 5.5 V.
In suspend mode, when VCCA is zero, there will be no current flow from one
supply to the other supply. The A-outputs must be set 3-state and the voltage
on the A-bus must be smaller than Vdiode (typ. 0.7 V). VCCA ≥ VCCB (except in
suspend mode).
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
tPHL/tPLH
PARAMETER
CONDITIONS
CL = 50 pF
TYPICAL
UNIT
propagation delay
An to Bn
VCCA = 5.0 V
VCCB = 3.3 V
4.0
4.0
ns
ns
pF
Bn to An
CI/O
input/output capacitance
A port
10.0
CPDA
An to Bn
VI = GND to VCC; note 1
VI = GND to VCC; note 1
7.8
pF
pF
Bn to An
27.9
CPDB
B port
An to Bn
VI = GND to VCC; note 1
VI = GND to VCC; note 1
26
pF
pF
Bn to An
10.4
Note
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
Σ(CL × VCC2 × fo) = sum of the outputs.
1999 Jun 15
2
Philips Semiconductors
Product specification
Octal dual supply translating transceiver; 3-state
74LVC4245A
FUNCTION TABLE
See note 1.
INPUT
INPUT/OUTPUT
OE
DIR
An
Bn
L
L
L
H
X
A = B
inputs
Z
inputs
B = A
Z
H
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
ORDERING INFORMATION
OUTSIDE NORTH
PACKAGE
PINS PACKAGE MATERIAL
NORTH AMERICA
TEMPERATURE
RANGE
AMERICA
CODE
74LVC4245AD
74LVC4245ADB
74LVC4245APW
74LVC4245AD
74LVC4245ADB
74LVC4245ADH
−40 to +85 °C
24
24
24
SO
plastic
plastic
plastic
SOT137-1
SOT340-1
SOT355-1
SSOP
TSSOP
PINNING
PIN
SYMBOL
DESCRIPTION
1
2
VCCA
DIR
DC supply voltage (5 V bus)
direction control
3, 4, 5, 6, 7, 8, 9 and 10
11, 12 and 13
A0 to A7
GND
data inputs/outputs
ground (0 V)
14, 15, 16, 17, 18, 19, 20 and 21
B7 to B0
OE
data inputs/outputs
22
output enable input (active LOW)
DC supply voltage (3 V bus)
23 and 24
VCCB
1999 Jun 15
3
Philips Semiconductors
Product specification
Octal dual supply translating transceiver; 3-state
74LVC4245A
handbook, halfpage
V
1
2
24
23
22
21
20
19
18
17
16
15
14
13
V
V
CCA
DIR
CCB
CCB
A
0
3
OE
A
1
4
B
0
A
2
5
B
1
A
3
6
B
2
4245
A
4
7
B
3
handbook, halfpage
2
A
5
8
DIR
B
4
A
6
9
B
5
OE
22
A
7
10
11
B
6
A
0
3
4
B
0
GND
B
7
21
A
1
GND 12
GND
B
1
MNA451
20
A
2
5
B
2
Fig.1 Pin configuration.
19
A
3
6
B
3
18
A
4
7
B
4
17
22
A
5
handbook, halfpage
G3
8
B
5
3EN1
2
16
3EN2
A
6
9
B
6
1
15
A
7
21
3
2
10
B
7
14
4
5
20
19
18
17
16
15
14
MNA453
6
7
8
9
10
MNA452
Fig.3 IEC logic symbol.
Fig.2 Logic symbol.
1999 Jun 15
4
Philips Semiconductors
Product specification
Octal dual supply translating transceiver; 3-state
74LVC4245A
RECOMMENDED OPERATING CONDITIONS
LIMITS
UNIT
SYMBOL
VCCA
PARAMETER
CONDITIONS
CCA ≥ VCCB (see Fig.5)
CCA ≥ VCCB (see Fig.5)
MIN.
MAX.
DC supply voltage 5 V port
(for maximum speed performance)
V
V
1.5
5.5
V
V
VCCB
DC supply voltage 3 V port
(for low-voltage applications)
1.5
3.6
VI
DC input voltage range (control inputs)
DC input voltage range; output 3-state
0
0
0
5.5
5.5
VCC
V
V
V
VI/O
DC output voltage range; output HIGH or
LOW state
Tamb
tr,tf
operating ambient temperature range
see DC and AC characteristics −40
per device
+85
°C
input rise and fall times
VCCB = 2.7 to 3.0 V
0
0
0
0
20
10
20
10
ns/V
V
CCB = 3.0 to 3.6 V
CCA = 3.0 to 4.5 V
V
VCCA = 4.5 to 5.5 V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
+6.5
UNIT
VCCA
VCCB
IIK
DC supply voltage 5 V port
DC supply voltage 3 V port
DC input diode current
DC input voltage
−0.5
−0.5
−
V
+4.6
V
VI < 0
note 1
−50
mA
V
VI
−0.5
−
+6.5
IOK
DC output diode current
VO > VCC or VO < 0
±50
mA
V
VI/O
DC output voltage; output HIGH or LOW note 1
−0.5
−0.5
−
VCC + 0.5
+6.5
DC input voltage; output 3-state
DC output diode current
DC VCC or GND current
storage temperature
note 1
V
IO
VO = 0 to VCC
±50
mA
mA
°C
I
GND, ICC
−
±100
+150
Tstg
Ptot
−65
power dissipation per package
plastic mini-pack (SO)
above 70 °C derate linearly
with 8 mW/K
−
−
500
500
mW
mW
plastic shrink mini-pack (SSOP and
TSSOP)
above 60 °C derate linearly
with 5.5 mW/K
Note
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1999 Jun 15
5
Philips Semiconductors
Product specification
Octal dual supply translating transceiver; 3-state
74LVC4245A
DC CHARACTERISTICS
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
−40 to +85
UNIT
VCCA/B
(V)
OTHER
MIN.
TYP.(1) MAX.
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
3 V port
5 V port
3 V port
5 V port
2.7 to 3.6 2.0
4.5 to 5.5 2.0
−
−
−
−
−
−
V
V
V
−
2.7 to 3.6
4.5 to 5.5
−
−
V
V
V
V
V
V
−
−
−
−
−
−
−
−
0.8
0.8
−
VOH
HIGH-level output voltage
(3 V port)
VI = VIH or VIL; IO = −12 mA 2.7
VI = VIH or VIL; IO = −100 µA 3.0
VI = VIH or VIL; IO = −24 mA 3.0
VI = VIH or VIL; IO = −12 mA 4.5
VI = VIH or VIL; IO = −100 µA 4.5
VI = VIH or VIL; IO = −24 mA 4.5
CC − 0.5
CC − 0.2 VCC
−
CC − 1.0
CC − 0.5
−
−
−
HIGH-level output voltage
(5 V port)
−
V
V
V
CC − 0.2 VCC
−
CC − 0.8
−
−
VOL
LOW-level output voltage
(3 V port)
VI = VIH or VIL; IO = 12 mA
VI = VIH or VIL; IO = 100 µA
VI = VIH or VIL; IO = 24 mA
VI = VIH or VIL; IO = 12 mA
VI = VIH or VIL; IO = 100 µA
VI = VIH or VIL; IO = 24 mA
VI = 5.5 V or GND; note 2
VI = VCC or GND
2.7
3.0
3.0
4.5
4.5
4.5
3.6
3.6
−
0.40
0.20
0.55
0.40
0.20
0.55
±5
±15
−
−
LOW-level output voltage
(5 V port)
−
−
−
II
IHZ/IILZ
input leakage current
±0.1
0.1
µA
µA
I
input current for common
I/O pins (3 V port)
input current for common
I/O pins (5 V port)
VI = VCC or GND
5.5
−
−
−
−
−
−
0.1
0.1
0.1
0.1
0.1
5
±15
±5
µA
µA
µA
µA
µA
µA
IOZ
3-state output OFF-state
current (3 V port)
VI = VIH or VIL;
VO = VCC or GND
3.6
3-state output OFF-state
current (5 V port)
VI = VIH or VIL;
VO = VCC or GND
5.5
±5
ICC
quiescent supply current
(3 V port)
VI = VCC or GND; IO = 0
3.6
10
quiescent supply current
(5 V port)
VI = VCC or GND; IO = 0
5.5
10
∆ICC
additional quiescent supply VI = VCC − 0.6 V; IO = 0
2.7 to 3.6
500
current per control pin (3 V
port)
additional quiescent supply VI = VCC − 2.1 V; IO = 0
4.5 to 5.5
−
5
500
µA
current per control pin (5 V
port)
Notes
1. All typical values are at VCCA = 5.0 V, VCCB = 3.3 V and Tamb = 25 °C.
2. Not for I/O pins.
1999 Jun 15
6
Philips Semiconductors
Product specification
Octal dual supply translating transceiver; 3-state
74LVC4245A
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; Tamb = −40 to 85 °C.
LIMITS
VCCA = 5 V ± 0.5 V
SYMBOL
PARAMETER
WAVEFORMS
UNIT
V
CCB = 3.3 V ± 0.3 V
VCCB = 2.7 V
MIN. TYP.(1) MAX. MIN. TYP.(2) MAX.
t
PHL/tPLH propagation delay
see Figs 4 and 7
see Figs 4 and 7
see Figs 6 and 7
see Figs 6 and 7
see Figs 6 and 7
see Figs 6 and 7
1.5
1.5
1.5
1.5
1.5
1.5
4.0
4.0
6.2
5.0
5.3
5.8
6.5
6.5
10
1.5
1.5
1.5
1.5
1.5
1.5
4.5
4.5
7.0
5.7
5.7
6.2
7.0
7.0
11.0
8.7
8.0
8.5
ns
ns
ns
ns
ns
ns
An to Bn
propagation delay
Bn to An
tPZH/tPZL 3-state output enable
time OE to An
3-state output enable
time OE to Bn
8.1
7.5
7.8
tPHZ/tPLZ 3-state output disable
time OE to An
3-state output disable
time OE to Bn
Notes
1. Typical values are measured at VCCA = 5.0 V and VCCB = 3.3 V and Tamb = 25 °C.
2. Typical values are measured at VCCA = 5.0 V and Tamb = 25 °C.
AC WAVEFORMS
MNA454
3.9
handbook, halfpag
V
V
≥ V
CCA CCB
CCB
(V)
3.6
3.3
3.0
2.7
2.4
2.1
1.8
1.5
1.2
0.9
V
handbook, halfpage
A , B
I
n
n
V
M
INPUT
GND
t
t
PHL
PLH
V
OH
B , A
n
n
V
M
OUTPUT
MNA366
V
OL
VM = 1.5 V at 2.7 V ≤ VCCB ≤ 3.6 V;
VM = 0.5VCCA at VCCA ≥ 4.5 V;
1.5
2.1
2.7
3.3
3.9
4.5
5.1
5.7
V
(V)
CCA
VOL and VOH are typical output voltage drop that occur
with the output load.
Full operation
Complies with TTL levels
Fig.4 The input (An, Bn) to output (Bn, An)
propagation delays.
Fig.5 Supply operation area.
1999 Jun 15
7
Philips Semiconductors
Product specification
Octal dual supply translating transceiver; 3-state
74LVC4245A
V
I
OE INPUT
V
M
GND
t
t
PZL
PLZ
V
CC
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA367
VM = 1.5 V at 2.7 V ≤ VCCB ≤ 3.6 V;
VY = VOH − 0.3 V at VCCB ≤ 3.6 V;
Y = VOH − 0.1 (VOH − GND) at VCCA ≥ 4.5 V;
V
M = 0.5VCCA at VCCA ≥ 4.5 V;
V
VX = VOL + 0.3 V at VCCB ≤ 3.6 V;
VOL and VOH are typical output voltage drop that occur with the output load.
VX = VOL + 0.1 (VCCA − VOL) at VCCA ≥ 4.5 V
Fig.6 The 3-state enable and disable times.
S1
2 × V
open
GND
CC
V
CC
R
L
500 Ω
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
50 pF
R
L
L
R
T
500 Ω
MNA368
VCC
VI
for A and B port VCC
<2.7 V
TEST
S1
open
Definitions for test circuit:
for B port
2.7 V
RL = Load resistor; see chapter “AC characteristics”.
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
2.7 to 3.6 V
CL = Load capacitance including jig and probe capacitance
(see chapter “AC characteristics”).
2 × VCC
for A port
3.0 V
RT = Termination resistance should be equal to the output
impedance Z0 of the pulse generator.
GND
4.5 to 5.5 V
Fig.7 Load circuitry for switching times.
8
1999 Jun 15
Philips Semiconductors
Product specification
Octal dual supply translating transceiver; 3-state
74LVC4245A
PACKAGE OUTLINES
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
H
v
M
A
E
y
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
mm
2.65
0.25
0.01
1.27
0.050
1.4
0.25 0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.61
0.014 0.009 0.60
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches 0.10
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-24
97-05-22
SOT137-1
075E05
MS-013AD
1999 Jun 15
9
Philips Semiconductors
Product specification
Octal dual supply translating transceiver; 3-state
74LVC4245A
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
D
E
A
X
c
H
v
M
A
y
E
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
8.4
8.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.8
0.4
mm
2.0
0.65
1.25
0.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
93-09-08
95-02-04
SOT340-1
MO-150AG
1999 Jun 15
10
Philips Semiconductors
Product specification
Octal dual supply translating transceiver; 3-state
74LVC4245A
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c
H
v
M
A
y
E
Z
13
24
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.10
0.65
0.25
1.0
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
93-06-16
95-02-04
SOT355-1
MO-153AD
1999 Jun 15
11
Philips Semiconductors
Product specification
Octal dual supply translating transceiver; 3-state
74LVC4245A
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
1999 Jun 15
12
Philips Semiconductors
Product specification
Octal dual supply translating transceiver; 3-state
74LVC4245A
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
not suitable(2)
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, SMS
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Jun 15
13
Philips Semiconductors
Product specification
Octal dual supply translating transceiver; 3-state
74LVC4245A
NOTES
1999 Jun 15
14
Philips Semiconductors
Product specification
Octal dual supply translating transceiver; 3-state
74LVC4245A
NOTES
1999 Jun 15
15
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© Philips Electronics N.V. 1999
SCA66
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Printed in The Netherlands
245004/03/pp16
Date of release: 1999 Jun 15
Document order number: 9397 750 06037
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