74LVC594ABQ-Q100X_技术文档

74LVC594A-Q100

8-bit shift register with output register

Rev. 1 — 15 November 2013

Product data sheet

1. General description

The 74LVC594A-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage

register. Separate clock and reset inputs are provided on both shift and storage registers.

The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of

this device in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial Power-down applications using I_OFF

.

The I_OFFcircuitry disables the output, preventing the damaging backflow current through

the device when it is powered down.

The shift register has a serial input (DS) and a serial output (Q7S) for cascading

purposes. Data is shifted on the positive-going transitions of the SHCP input. The data in

the shift register is transferred to the storage register on a positive-going transition of the

STCP input. If both clocks are connected together, the shift register is always one clock

pulse ahead of the storage register. A LOW level on one of the two register reset pins

(SHR and STR) clears the corresponding register.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 5 V tolerant inputs/outputs for interfacing with 5 V logic

 Wide supply voltage range from 1.2 V to 3.6 V

 CMOS low-power consumption

 Direct interface with TTL levels

 Balanced propagation delays

 All inputs have Schmitt-trigger action

 Complies with JEDEC standard:

 JESD8-7A (1.65 V to 1.95 V)

 JESD8-5A (2.3 V to 2.7 V)

 JESD8-C/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

74LVC594A-Q100

NXP Semiconductors

8-bit shift register with output register

3. Applications

 Serial-to-parallel data conversion

 Remote control holding register

4. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVC594AD-Q100

74LVC594APW-Q100

74LVC594ABQ-Q100

40 C to +125 C

SO16

plastic small outline package; 16 leads;

body width 3.9 mm

SOT109-1

SOT403-1

SOT763-1

TSSOP16

plastic thin shrink small outline package;

16 leads; body width 4.4 mm

DHVQFN16 plastic dual in-line compatible thermal

enhanced very thin quad flat package; no

leads; 16 terminals; body 2.5  3.5  0.85 mm

5. Functional diagram

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Fig 1. Logic symbol

Fig 2. Functional diagram

74LVC594A_Q100

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Product data sheet

Rev. 1 — 15 November 2013

2 of 20

74LVC594A-Q100

NXP Semiconductors

8-bit shift register with output register

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Fig 4. Timing diagram

74LVC594A_Q100

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Product data sheet

Rev. 1 — 15 November 2013

3 of 20

74LVC594A-Q100

NXP Semiconductors

8-bit shift register with output register

6. Pinning information

6.1 Pinning

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Fig 5. Pin configuration SO16 and TSSOP16

Fig 6. Pin configuration DHVQFN16

6.2 Pin description

Table 2.

Symbol

Pin description

Description

Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7

15, 1, 2, 3, 4, 5, 6, 7

parallel data output

ground (0 V)

GND

Q7S

SHR

SHCP

STCP

STR

DS

8

9

serial data output

10

11

12

13

14

16

shift register reset (active LOW)

shift register clock input

storage register clock input

storage register reset (active LOW)

serial data input

V_CC

supply voltage

74LVC594A_Q100

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Product data sheet

Rev. 1 — 15 November 2013

4 of 20

74LVC594A-Q100

NXP Semiconductors

8-bit shift register with output register

7. Functional description

Table 3.

Input

Function table^[1]

Output

Q7S

L

Function

SHCP STCP SHR STR

DS

X

Qn

NC

L

X



X



X

L

X

L

a LOW-state on SHR only affects the shift register

a LOW-state on STR only affects the storage register

empty shift register loaded into storage register

X

L

X

NC

H

X

L

H

Q6S

NC

logic HIGH level shifted into shift register stage 0. Contents of all

shift register stages shifted through, e.g. previous state of stage 6

(internal Q6S) appears on the serial output (Q7S).

X



H

X

NC

QnS

contents of shift register stages (internal QnS) are transferred to

the storage register and parallel output stages



Q6S

contents of shift register shifted through; previous contents of the

shift register is transferred to the storage register and the parallel

output stages

[1] H = HIGH voltage state;

L = LOW voltage state;

 = LOW-to-HIGH transition;

X = don’t care;

NC = no change;

8. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

0.5

50

0.5

-

Max

+6.5

-

Unit

V

supply voltage

input clamping current

input voltage

V_I< 0 V

mA

V

[1]

V_I

+6.5

50

6.5

I_OK

output clamping current

output voltage

V_O> V_CCor V_O< 0 V

3-state

mA

V

[1]

V_O

0.5

-

output HIGH or LOW state

V_O= 0 V to V_CC

V_CC+ 0.5

50

100

-

V

I_O

output current

mA

C

I_CC

I_GND

T_stg

P_tot

supply current

-

ground current

100

65

-

storage temperature

total power dissipation

+150

500

[2]

T_amb= 40 C to +125 C

mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For SO16 packages: above 70 C the value of P_totderates linearly with 8 mW/K.

For TSSOP16 packages: above 60 C the value of P_totderates linearly with 5.5 mW/K.

For DHVQFN16 packages: above 60 C the value of P_totderates linearly with 4.5 mW/K.

74LVC594A_Q100

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Product data sheet

Rev. 1 — 15 November 2013

5 of 20

74LVC594A-Q100

NXP Semiconductors

8-bit shift register with output register

9. Recommended operating conditions

Table 5.

Symbol

V_CC

Recommended operating conditions

Parameter

Conditions

Min

1.65

1.2

0

Typ

Max

3.6

-

Unit

V

supply voltage

-

functional

V

V_I

input voltage

5.5

V_CC

+125

20

V

V_O

output voltage

3-state

0

V

output HIGH or LOW state

0

V

T_amb

ambient temperature

40

-

C

ns/V

t/V

input transition rise and fall rate V_CC= 1.65 V to 2.7 V

V_CC= 2.7 V to 3.6 V

-

10

10. Static characteristics

Table 6.

Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C

Unit

Min

Typ^[1]

Max

Min

Max

V_IH

HIGH-level

input voltage

V_CC= 1.2 V

1.08

-

1.08

-

V

V_CC= 1.65 V to 1.95 V

0.65  V_CC

-

0.65  V_CC

-

V_CC= 2.3 V to 2.7 V

1.7

-

1.7

-

V_CC= 2.7 V to 3.6 V

V_CC= 1.2 V

2.0

-

0.12

2.0

-

0.12

V_IL

LOW-level

input voltage

-

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_I= V_IHor V_IL

0.35  V_CC

0.7

0.35  V_CC

0.7

0.8

V_OH

HIGH-level

output

voltage

I_O= 100 A;

V_CC= 1.65 V to 3.6 V

V_CC 0.2

-

V_CC 0.3

-

V

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 18 mA; V_CC= 3.0 V

I_O= 24 mA; V_CC= 3.0 V

V_I= V_IHor V_IL

1.2

1.8

2.2

2.4

2.2

-

1.05

1.65

2.05

2.25

2.0

-

V

V_OL

LOW-level

output

voltage

I_O= 100 A;

-

0.2

-

0.3

V

V_CC= 1.65 V to 3.6 V

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

-

0.45

0.6

-

0.65

0.8

V

-

V

-

0.4

0.6

V

0.55

5

0.8

V

I_I

input leakage V_CC= 3.6 V; V_I= 5.5 V or GND

current

0.1

20

A

74LVC594A_Q100

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Product data sheet

Rev. 1 — 15 November 2013

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74LVC594A-Q100

NXP Semiconductors

8-bit shift register with output register

Table 6.

Static characteristics …continued

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 40 C to +85 C

40 C to +125 C

Unit

Min

Typ^[1]

Max

Min

Max

I_OFF

power-off

leakage

current

V_CC= 0 V; V_Ior V_O= 5.5 V

-

0.1

10

-

20

A

I_CC

supply

current

V_CC= 3.6 V; V_I= V_CCor GND;

I_O= 0 A

-

0.1

5

10

-

40

A

I_CC

additional

supply

per input pin;

500

5000

V_CC= 1.65 V to 3.6 V;

current

V_I= V_CC 0.6 V; I_O= 0 A

C_I

input

V_CC= 0 V to 3.6 V;

-

5.0

-

pF

capacitance V_I= GND to V_CC

[1] All typical values are measured at V_CC= 3.3 V (unless stated otherwise) and T_amb= 25 C.

11. Dynamic characteristics

Table 7.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 13.

Symbol Parameter Conditions 40 C to +85 C

40 C to +125 C Unit

Min

Typ^[1]

Max

Min

Max

[2]

t_pd

propagation delay SHCP to Q7S; see Figure 7

V_CC= 1.2 V

-

17.5

5.2

3.2

3.5

3.1

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

2.0

1.5

15.8

8.1

7.6

6.7

2.0

1.5

18.2

9.3

8.7

7.7

V_CC= 3.0 V to 3.6 V

STCP to Qn; see Figure 8

V_CC= 1.2 V

[2]

-

19.3

7.6

4.8

5.2

4.5

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

2.0

1.5

1.2

15.8

8.1

7.6

6.7

2.0

1.5

1.2

18.2

9.3

8.7

7.7

V_CC= 3.0 V to 3.6 V

74LVC594A_Q100

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Product data sheet

Rev. 1 — 15 November 2013

7 of 20

74LVC594A-Q100

NXP Semiconductors

8-bit shift register with output register

Table 7.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 13.

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C Unit

Min

Typ^[1]

Max

Min

Max

t_PHL

HIGH to LOW

propagation delay

SHR to Q7S; see Figure 11

V_CC= 1.2 V

-

12.0

5.0

3.8

3.9

3.3

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

2.0

1.5

1.2

15.8

8.1

7.6

6.7

2.0

1.5

1.2

18.2

9.3

8.7

7.7

V_CC= 3.0 V to 3.6 V

STR to Qn; see Figure 12

V_CC= 1.2 V

-

20.0

7.7

5.0

5.3

4.4

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

2.0

1.5

1.2

15.8

8.1

7.6

6.7

2.0

1.5

1.2

18.2

9.3

8.7

7.7

V_CC= 3.0 V to 3.6 V

t_W

pulse width

SHCP, STCP HIGH or LOW;

see Figure 7 and Figure 8

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

6.0

5.0

4.5

4.0

2.5

2.0

1.5

-

7.0

5.5

5.0

4.5

-

ns

V_CC= 3.0 V to 3.6 V

SHR, STR LOW; see

Figure 11 and Figure 12

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

6.0

4.0

2.5

2.0

1.5

-

5.5

4.5

3.0

-

ns

V_CC= 3.0 V to 3.6 V

DS to SHCP; see Figure 9

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

t_su

set-up time

5.0

4.0

2.0

1.0

0.8

0.6

-

5.5

4.5

2.5

-

ns

V_CC= 3.0 V to 3.6 V

SHR to STCP; see Figure 10

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

8.0

5.0

4.0

3.5

2.1

1.8

1.7

-

8.5

5.5

4.5

-

ns

V_CC= 3.0 V to 3.6 V

SHCP to STCP; see Figure 8

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

8.0

5.0

4.0

3.5

2.1

1.8

1.7

-

8.5

5.5

4.5

-

ns

V_CC= 3.0 V to 3.6 V

74LVC594A_Q100

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Product data sheet

Rev. 1 — 15 November 2013

8 of 20

74LVC594A-Q100

NXP Semiconductors

8-bit shift register with output register

Table 7.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 13.

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C Unit

Min

Typ^[1]

Max

Min

Max

t_h

hold time

DS to SHCP; see Figure 9

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.5

0.2

0.1

-

2.0

-

ns

+1.5

+1.0

0.1

0.2

+2.0

+1.5

V_CC= 3.0 V to 3.6 V

t_rec

recovery time

SHR to SHCP, STR to STCP;

see Figure 11 and Figure 12

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

+5.0

+4.0

+2.0

2.7

1.5

1.0

-

+5.5

+4.5

+2.5

-

ns

V_CC= 3.0 V to 3.6 V

f_max

maximum

frequency

SHCP or STCP; see Figure 7

and Figure 8

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

80

100

110

130

-

130

140

150

180

-

70

90

100

115

-

MHz

ns

-

V_CC= 3.0 V to 3.6 V

-

[3]

[4]

t_sk(o)

C_PD

output skew time V_CC= 3.0 V to 3.6 V

power dissipation V_I= GND to V_CC

1.0

1.5

capacitance

V_CC= 1.65 V to 1.95 V

-

50

45

44

-

pF

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

[1] Typical values are measured at T_amb= 25 C and V_CC= 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.

[2] _pdis the same as t_PLHand t_PHL

t

.

[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[4] C_PDis used to determine the dynamic power dissipation (P_Din W).

P_D= C_PD V_CC² f_i N + (C_L V_CC² f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

(C_L V_CC² f_o) = sum of outputs.

74LVC594A_Q100

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Product data sheet

Rev. 1 — 15 November 2013

9 of 20

74LVC594A-Q100

NXP Semiconductors

8-bit shift register with output register

12. Waveforms

1/f

max

V

I

SHCP input

GND

V

M

t

W

t

PHL

PLH

V

OH

V

Q7S output

M

V

OL

mna557

Measurement points are given in Table 8.

V_OLand V_OHare typical output voltage drops that occur with the output load.

Fig 7. The shift clock (SHCP) to serial data output (Q7S) propagation delays, the shift clock pulse width and

maximum shift clock frequency

V

I

SHCP input

GND

V

M

t

1/f

max

su

V

I

STCP input

GND

V

M

t

W

t

PHL

PLH

V

OH

V

Qn output

M

V

OL

mna558

Measurement points are given in Table 8.

V_OLand V_OHare typical output voltage drops that occur with the output load.

Fig 8. The storage clock (STCP) to parallel data output (Qn) propagation delays, the storage clock pulse width

and the shift clock to storage clock set-up time

74LVC594A_Q100

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Product data sheet

Rev. 1 — 15 November 2013

10 of 20

74LVC594A-Q100

NXP Semiconductors

8-bit shift register with output register

V

I

V

SHCP input

M

GND

t

su

M

t

h

V

I

V

DS input

GND

V

OH

V

Q7S output

M

V

OL

mna560

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

V_OLand V_OHare typical output voltage drops that occur with the output load.

Fig 9. The data set-up and hold times for the serial data input (DS)

9

0

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W

VX

9

0

67&3ꢋLQSXW

9

0

4QꢋRXWSXWV

PEFꢀꢃꢆ

Measurement points are given in Table 8.

V

_OLand V_OHare typical output voltage drops that occur with the output load.

Fig 10. The shift reset (SHR) to storage clock (STCP) set-up times

74LVC594A_Q100

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Product data sheet

Rev. 1 — 15 November 2013

11 of 20

74LVC594A-Q100

NXP Semiconductors

8-bit shift register with output register

9

0

6+5ꢋLQSXW

6+&3ꢋLQSXW

4ꢀ6ꢋRXWSXW

W

:

W

UHF

9

0

W

3+/

9

0

PEFꢀꢃꢉ

Measurement points are given in Table 8.

V_OLand V_OHare typical output voltage drops that occur with the output load.

Fig 11. The shift reset (SHR) pulse width, the shift reset to serial data output (Q7S) propagation delays and the

shift reset to shift clock (SHCP) recovery time

9

0

675ꢋLQSXW

W

:

W

UHF

9

0

67&3ꢋLQSXW

W

3+/

9

0

4QꢋRXWSXWV

PEFꢀꢃꢊ

Measurement points are given in Table 8.

V

_OLand V_OHare typical output voltage drops that occur with the output load.

Fig 12. The storage reset (STR) pulse width, the storage reset to parallel data output (Qn) propagation delays and

the storage reset to storage clock (STCP) recovery time

Table 8.

Measurement points

Supply voltage

V_CC

Input

V_M

Output

V_M

V_CC< 2.7 V

V_CC 2.7 V

0.5  V_CC

1.5 V

0.5  V_CC

1.5 V

74LVC594A_Q100

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Product data sheet

Rev. 1 — 15 November 2013

12 of 20

74LVC594A-Q100

NXP Semiconductors

8-bit shift register with output register

W

:

9

,

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U

I

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:

9

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&&

/

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2

,

*

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5

7

&

/

5

/

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Test data is given in Table 9. Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig 13. Test circuit for measuring switching times

Table 9.

Test data

Supply voltage

Input

V_I

Load

C_L

V_EXT

t_r, t_f

R_L

t_PLH, t_PHL

open

t_PLZ, t_PZL

2  V_CC

t_PHZ, t_PZH

GND

1.2 V

V_CC

2.7 V

 2 ns

 2.5 ns

30 pF

50 pF

1 k

500 

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

open

GND

open

GND

open

GND

3.0 V to 3.6 V

open

GND

74LVC594A_Q100

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Product data sheet

Rev. 1 — 15 November 2013

13 of 20

74LVC594A-Q100

NXP Semiconductors

8-bit shift register with output register

13. Package outline

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Fig 14. Package outline SOT109-1 (SO16)

74LVC594A_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 15 November 2013

14 of 20

74LVC594A-Q100

NXP Semiconductors

8-bit shift register with output register

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Fig 15. Package outline SOT403-1 (TSSOP16)

74LVC594A_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 15 November 2013

15 of 20

74LVC594A-Q100

NXP Semiconductors

8-bit shift register with output register

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Fig 16. Package outline SOT763-1 (DHVQFN16)

74LVC594A_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 15 November 2013

16 of 20

74LVC594A-Q100

NXP Semiconductors

8-bit shift register with output register

14. Abbreviations

Table 10. Abbreviations

Acronym

CDM

Description

Charged Device Model

CMOS

DUT

Complementary Metal Oxide Semiconductor

Device Under Test

ESD

ElectroStatic Discharge

HBM

Human Body Model

TTL

Transistor-Transistor Logic

15. Revision history

Table 11. Revision history

Document ID

Release date

20131115

Data sheet status

Change notice

Supersedes

74LVC594A_Q100 v.1

Product data sheet

-

74LVC594A_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 15 November 2013

17 of 20

74LVC594A-Q100

NXP Semiconductors

8-bit shift register with output register

16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use in automotive applications — This NXP

16.2 Definitions

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

74LVC594A_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 15 November 2013

18 of 20

74LVC594A-Q100

NXP Semiconductors

8-bit shift register with output register

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

74LVC594A_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 15 November 2013

19 of 20

74LVC594A-Q100

NXP Semiconductors

8-bit shift register with output register

18. Contents

1

2

3

4

5

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7

Functional description . . . . . . . . . . . . . . . . . . . 5

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Recommended operating conditions. . . . . . . . 6

Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17

8

9

10

11

12

13

14

15

16

Legal information. . . . . . . . . . . . . . . . . . . . . . . 18

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19

16.1

16.2

16.3

16.4

17

18

Contact information. . . . . . . . . . . . . . . . . . . . . 19

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 15 November 2013

Document identifier: 74LVC594A_Q100


型号：	74LVC594ABQ-Q100X
厂家：	NXP
描述：	74LVC594A-Q100 - 8-bit shift register with output register QFN 16-Pin
文件：	总20页 (文件大小：202K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74LVC594ABQ-Q100X [NXP]

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