74LVC595AD [NXP]
8-bit serial-in/serial-out or parallel-out shift register; 3-state; 8位串行输入/串行输出或并行输出移位寄存器;三态
| 型号： | 74LVC595AD |
| 厂家： | 
NXP |
| 描述： | 8-bit serial-in/serial-out or parallel-out shift register; 3-state |
| 文件： | 总19页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Rev. 01 — 29 May 2007
Product data sheet
1. General description
The 74LVC595A is an 8-bit serial-in/serial or parallel-out shift register with a storage
register and 3-state outputs. Both the shift and storage register have separate clocks.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial Power-down applications using IOFF
.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
Data is shifted on the positive-going transitions of the SHCP input. The data in the shift
register is transferred to the storage register on a positive-going transition of the STCP
input. If both clocks are connected together, the shift register will always be one clock
pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial output (Q7S) for cascading
purposes. It is also provided with asynchronous reset input MR (active LOW) for all 8 shift
register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the
storage register appears at the output whenever the output enable input (OE) is LOW.
2. Features
■ 5 V tolerant inputs/outputs for interfacing with 5 V logic
■ Wide supply voltage range from 1.2 V to 3.6 V
■ CMOS low-power consumption
■ Direct interface with TTL levels
■ Balanced propagation delays
■ All inputs have Schmitt-trigger action
■ Complies with JEDEC standard JESD8-B/JESD36
■ ESD protection:
◆ HBM JESD22-A114-D exceeds 2000 V
◆ CDM JESD22-C101-C exceeds 1000 V
■ Specified from −40 °C to +85 °C and −40 °C to +125 °C.
3. Applications
■ Serial-to-parallel data conversion
■ Remote control holding register
74LVC595A
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register; 3-state
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
−40 °C to +125 °C
Name
Description
Version
74LVC595AD
74LVC595APW
74LVC595ABQ
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
−40 °C to +125 °C
−40 °C to +125 °C
TSSOP16
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1
very thin quad flat package; no leads; 16
terminals; body 2.5 × 3.5 × 0.85 mm
5. Functional diagram
11
12
SHCP
STCP
14 DS
9
15
1
Q7S
Q0
Q1
Q2
Q3
Q4
Q5
Q6
11 SHCP
8-STAGE SHIFT REGISTER
10 MR
Q7S
9
2
14
3
12 STCP
13 OE
DS
8-BIT STORAGE REGISTER
3-STATE OUTPUTS
4
5
6
7
Q7
OE
MR
10
Q0
15
Q1 Q2 Q3 Q4 Q5 Q6 Q7
13
mna552
1
2
3
4
5
6
7
mna554
Fig 1. Logic symbol
Fig 2. Functional diagram
74LVC595A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 29 May 2007
2 of 19
74LVC595A
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register; 3-state
STAGE 0
Q
STAGES 1 TO 6
STAGE 7
D Q
DS
Q7S
D
D
Q
FF7
CP
FF0
CP
R
R
SHCP
MR
D
Q
D
Q
LATCH
CP
LATCH
CP
STCP
OE
mna555
Q0
Q1 Q2 Q3 Q4 Q5 Q6
Q7
Fig 3. Logic diagram
SHCP
DS
STCP
MR
OE
Q0
Z-state
Z-state
Q1
Z-state
Z-state
Q6
Q7
Q7S
mna556
Fig 4. Timing diagram
74LVC595A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 29 May 2007
3 of 19
74LVC595A
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register; 3-state
6. Pinning information
6.1 Pinning
74LVC595A
terminal 1
index area
74LVC595A
2
3
4
5
6
7
15
14
13
12
11
10
Q2
Q3
Q4
Q5
Q6
Q7
Q0
DS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q1
Q2
V
CC
Q0
OE
Q3
DS
STCP
SHCP
MR
Q4
OE
Q5
STCP
SHCP
MR
Q6
Q7
001aaf570
GND
Q7S
001aaf569
Transparent top view
Fig 5. Pin configuration SO16 and TSSOP16
Fig 6. Pin configuration DHVQFN16
6.2 Pin description
Table 2.
Symbol
Q[0:7]
GND
Q7S
Pin description
Pin
Description
15, 1, 2, 3, 4, 5, 6, 7 parallel data output
8
ground (0 V)
9
serial data output
MR
10
11
12
13
14
16
master reset (active LOW)
shift register clock input
storage register clock input
output enable input (active LOW)
serial data input
SHCP
STCP
OE
DS
VCC
supply voltage
74LVC595A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 29 May 2007
4 of 19
74LVC595A
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register; 3-state
7. Functional description
Table 3.
Input
Function table[1]
Output
Function
SHCP STCP OE
MR
L
DS
X
Q7S
L
Qn
NC
L
X
X
X
↑
X
↑
L
L
H
L
a LOW-state on MR only affects the shift register
empty shift register loaded into storage register
L
X
L
X
X
L
X
L
Z
shift register clear; parallel outputs in high impedance OFF-state
H
H
Q6S
NC
logic HIGH-state shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
X
↑
↑
L
L
H
H
X
X
NC
QnS
QnS
contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
↑
Q6S
contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
[1] H = HIGH voltage state;
L = LOW voltage state;
↑ = LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
−0.5
−50
−0.5
-
Max
+6.5
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
VI
+6.5
±50
6.5
IOK
output clamping current
output voltage
VO > VCC or VO < 0 V
3-state
mA
V
[1]
[1]
VO
−0.5
−0.5
-
output HIGH or LOW state
VO = 0 V to VCC
VCC + 0.5
±50
100
-
V
IO
output current
mA
mA
mA
°C
ICC
IGND
Tstg
Ptot
supply current
-
ground current
−100
−65
-
storage temperature
total power dissipation
+150
500
[2]
Tamb = −40 °C to +125 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO16 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For TSSOP16 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K.
74LVC595A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 29 May 2007
5 of 19
74LVC595A
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register; 3-state
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol Parameter
Conditions
Min
1.65
1.2
0
Typ
Max
3.6
-
Unit
V
VCC
supply voltage
-
-
-
-
-
-
-
-
functional
V
VI
input voltage
5.5
5.5
VCC
V
VO
output voltage
3-state
0
V
output HIGH or LOW state
0
V
Tamb
ambient temperature
−40
0
+125 °C
∆t/∆V
input transition rise and fall rate
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 3.6 V
20
10
ns/V
ns/V
0
10. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
VIH
HIGH-level
input voltage
VCC = 1.2 V
1.08
-
-
-
-
-
-
-
-
-
1.08
-
V
V
V
V
V
V
V
V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.2 V
0.65 × VCC
-
0.65 × VCC
-
1.7
-
1.7
-
2.0
-
0.12
2.0
-
0.12
VIL
LOW-level
input voltage
-
-
-
-
-
-
-
-
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VI = VIH or VIL
0.35 × VCC
0.7
0.35 × VCC
0.7
0.8
0.8
VOH
HIGH-level
output
voltage
IO = −100 µA;
V
CC − 0.2
-
-
V
CC − 0.3
-
V
VCC = 1.65 V to 3.6 V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −18 mA; VCC = 3.0 V
IO = −24 mA; VCC = 3.0 V
VI = VIH or VIL
1.2
1.8
2.2
2.4
2.2
-
-
-
-
-
-
-
-
-
-
1.05
1.65
2.05
2.25
2.0
-
-
-
-
-
V
V
V
V
V
VOL
LOW-level
output
voltage
IO = 100 µA;
-
-
0.2
-
0.3
V
VCC = 1.65 V to 3.6 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
-
-
-
-
-
-
0.45
0.6
-
-
-
-
-
0.65
0.8
V
-
V
-
-
0.4
0.6
V
0.55
±5
0.8
V
II
input leakage VCC = 3.6 V;
current VI = 5.5 V or GND
±0.1
±20
µA
74LVC595A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 29 May 2007
6 of 19
74LVC595A
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
[2]
IOZ
OFF-state
output
VI = VIH or VIL;
VO = 5.5 V or GND;
-
0.1
±10
-
±20
µA
current
VCC = 3.6 V
IOFF
power-off
leakage
current
VCC = 0 V; VI or VO = 5.5 V
-
0.1
10
-
20
µA
ICC
supply
current
VCC = 3.6 V;
VI = VCC or GND; IO = 0 A
-
-
0.1
5
10
-
-
40
µA
µA
∆ICC
additional
supply
per input pin;
500
5000
VCC = 1.65 V to 3.6 V;
current
VI = VCC − 0.6 V; IO = 0 A
CI
input
VCC = 0 V to 3.6 V;
-
5.0
-
-
-
pF
capacitance VI = GND to VCC
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.
[2] For transceivers, the parameter IOZ includes the input leaking current.
11. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.
Symbol Parameter Conditions −40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
[2]
tpd
propagation delay SHCP to Q7S; see Figure 7
VCC = 1.2 V
-
17.5
6.6
4.2
4.7
4.0
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.0
1.5
1.5
1.5
15.8
8.1
7.6
6.7
2.0
1.5
1.5
1.5
18.2
9.3
8.7
7.7
VCC = 3.0 V to 3.6 V
STCP to Qn; see Figure 8
VCC = 1.2 V
[2]
-
16.8
5.8
3.7
4.0
3.3
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.0
1.5
1.5
1.2
15.8
8.1
7.6
6.7
2.0
1.5
1.5
1.2
18.2
9.3
8.7
7.7
VCC = 3.0 V to 3.6 V
tPHL
HIGH to LOW
propagation delay
MR to Q7S; see Figure 11
VCC = 1.2 V
-
17.3
6.9
4.3
4.5
3.8
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.0
1.5
1.5
1.2
15.8
8.1
7.6
6.7
2.0
1.5
1.5
1.2
18.2
9.3
8.7
7.7
VCC = 3.0 V to 3.6 V
74LVC595A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 29 May 2007
7 of 19
74LVC595A
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
[3]
ten
tdis
tW
enable time
disable time
pulse width
OE to Qn; see Figure 12
VCC = 1.2 V
-
17.9
6.4
4.2
4.5
3.8
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.0
1.5
1.5
1.2
14.1
8.0
7.6
6.7
2.0
1.5
1.5
1.2
16.2
9.2
8.7
7.7
VCC = 3.0 V to 3.6 V
OE to Qn; see Figure 12
VCC = 1.2 V
[4]
-
9.6
4.9
2.8
3.7
3.5
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.0
1.2
1.5
1.2
9.8
5.8
6.2
5.7
2.0
1.2
1.5
1.2
11.2
6.6
7.1
6.5
VCC = 3.0 V to 3.6 V
SHCP, STCP HIGH or LOW;
see Figure 7 and Figure 8
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
6.0
5.0
4.5
4.0
2.5
2.0
1.5
1.5
-
-
-
-
7.0
5.5
5.0
4.5
-
-
-
-
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
MR LOW; see Figure 11
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
5.0
4.0
2.5
2.5
2.0
1.5
1.0
1.0
-
-
-
-
5.5
4.5
3.0
3.0
-
-
-
-
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
DS to SHCP; see Figure 9
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
tsu
set-up time
5.0
4.0
2.0
2.0
0.4
0.1
0
-
-
-
-
5.5
4.5
2.5
2.5
-
-
-
-
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
MR to STCP; see Figure 10
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
−0.1
8.0
5.0
4.0
4.0
3.5
2.1
1.8
1.7
-
-
-
-
8.5
5.5
4.5
4.5
-
-
-
-
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
SHCP to STCP; see Figure 8
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
8.0
5.0
4.0
4.0
3.5
2.1
1.8
1.7
-
-
-
-
8.5
5.5
4.5
4.5
-
-
-
-
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
74LVC595A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 29 May 2007
8 of 19
74LVC595A
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
th
hold time
DS to SHCP; see Figure 9
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
1.5
1.5
1.0
0.2
0.1
-
-
-
-
2.0
2.0
2.0
1.5
-
-
-
-
ns
ns
ns
ns
−0.1
−0.2
VCC = 3.0 V to 3.6 V
MR to SHCP; see Figure 11
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
trec
recovery time
5.0
4.0
2.0
2.0
−2.7
−1.5
−1.0
−1.0
-
-
-
-
5.5
4.5
2.5
2.5
-
-
-
-
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
fmax
maximum
frequency
SHCP or STCP; see Figure 7
and Figure 8
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
80
100
110
130
-
130
140
150
180
-
-
70
90
-
MHz
MHz
MHz
MHz
ns
-
-
-
-
100
115
-
VCC = 3.0 V to 3.6 V
-
-
[5]
[6]
tsk(o)
CPD
output skew time VCC = 3.0 V to 3.6 V
power dissipation VI = GND to VCC
1.0
1.5
capacitance
VCC = 1.65 V to 1.95 V
-
-
-
50
45
44
-
-
-
-
-
-
-
-
-
pF
pF
pF
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL
[3] ten is the same as tPZH and tPZL
[4] tdis is the same as tPHZ and tPLZ
.
.
.
[5] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[6] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
74LVC595A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 29 May 2007
9 of 19
74LVC595A
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register; 3-state
12. Waveforms
1/f
max
V
I
SHCP input
GND
V
M
t
W
t
t
PHL
PLH
V
OH
V
Q7S output
M
V
OL
mna557
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 7. The shift clock (SHCP) to serial data output (Q7S) propagation delays, the shift clock pulse width and
maximum shift clock frequency
V
I
SHCP input
GND
V
M
t
1/f
max
su
V
I
STCP input
GND
V
M
t
t
W
t
PHL
PLH
V
OH
V
M
Qn output
V
OL
mna558
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 8. The storage clock (STCP) to parallel data output (Qn) propagation delays, the storage clock pulse width
and the shift clock to storage clock set-up time
74LVC595A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 29 May 2007
10 of 19
74LVC595A
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register; 3-state
V
I
V
SHCP input
M
GND
t
t
su
su
M
t
t
h
h
V
I
V
DS input
GND
V
OH
V
Q7S output
M
V
OL
mna560
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 9. The data set-up and hold times for the serial data input (DS)
V
I
V
MR input
GND
M
t
su
V
I
V
STCP input
GND
M
V
OH
V
Qn outputs
M
V
OL
001aaf571
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 10. The master reset (MR) to storage clock (STCP) set-up times
74LVC595A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 29 May 2007
11 of 19
74LVC595A
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register; 3-state
V
I
V
M
MR input
GND
t
t
rec
W
V
I
SHCP input
Q7S output
V
M
GND
t
PHL
V
OH
V
M
V
OL
mna561
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 11. The master reset (MR) pulse width, the master reset to serial data output (Q7S) propagation delays and the
master reset to shift clock (SHCP) recovery time
V
I
V
OE input
M
GND
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
V
X
OL
t
t
PHZ
PZH
V
OH
V
Y
output
V
HIGH-to-OFF
OFF-to-HIGH
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
001aae821
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 12. 3-state enable and disable times
Table 8.
Measurement points
Supply voltage
VCC
Input
VM
Output
VM
VX
VY
VCC < 2.7 V
0.5 × VCC
1.5 V
0.5 × VCC
1.5 V
V
V
OL + 0.15 V
OL + 0.3 V
V
OH − 0.15 V
VCC ≥ 2.7 V
VOH − 0.3 V
74LVC595A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 29 May 2007
12 of 19
74LVC595A
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register; 3-state
t
W
V
I
90 %
negative
pulse
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
V
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 9. Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 13. Load circuitry for switching times
Table 9.
Test data
Supply voltage
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPLZ, tPZL
2 × VCC
2 × VCC
2 × VCC
2 × VCC
2 × VCC
tPHZ, tPZH
GND
1.2 V
VCC
VCC
VCC
2.7 V
2.7 V
≤ 2 ns
≤ 2 ns
≤ 2 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
30 pF
50 pF
50 pF
1 kΩ
1 kΩ
500 Ω
500 Ω
500 Ω
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
open
GND
open
GND
open
GND
3.0 V to 3.6 V
open
GND
74LVC595A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 29 May 2007
13 of 19
74LVC595A
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register; 3-state
13. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 14. Package outline SOT109-1 (SO16)
74LVC595A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 29 May 2007
14 of 19
74LVC595A
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register; 3-state
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 15. Package outline SOT403-1 (TSSOP16)
74LVC595A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 29 May 2007
15 of 19
74LVC595A
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register; 3-state
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
y
D
D
E
L
v
w
y
1
1
h
1
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
Fig 16. Package outline SOT763-1 (DHVQFN16)
74LVC595A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 29 May 2007
16 of 19
74LVC595A
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register; 3-state
14. Abbreviations
Table 10. Abbreviations
Acronym
CDM
Description
Charged Device Model
CMOS
DUT
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 11. Revision history
Document ID
Release date
20070529
Data sheet status
Change notice
Supersedes
74LVC595A_1
Product data sheet
-
-
74LVC595A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 29 May 2007
17 of 19
74LVC595A
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register; 3-state
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
16.2 Definitions
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
17. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
74LVC595A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 29 May 2007
18 of 19
74LVC595A
NXP Semiconductors
8-bit serial-in/serial-out or parallel-out shift register; 3-state
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 29 May 2007
Document identifier: 74LVC595A_1
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