74LVC821AD [NXP]
10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State; 10位D型触发器，5伏的耐受的输入/输出;正边沿触发三态
| 型号： | 74LVC821AD |
| 厂家： | 
NXP |
| 描述： | 10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State |
| 文件： | 总12页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74LVC821A
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger
(3-State)
Product specification
1998 Sep 25
Philips
Semiconductors
Philips Semiconductors
Product specification
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
74LVC821A
FEATURES
DESCRIPTION
The 74LVC821A is a high performance, low-power, low-voltage
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
• 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
• Supply voltage range of 2.7V to 3.6V
• Complies with JEDEC standard no. 8-1A
• Inputs accept voltages up to 5.5V
• CMOS low power consumption
Inputs can be driven from either 3.3V or 5.0V devices. In 3-state
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC821A is a10-bit D-type flip-flop featuring separate D-type
inputs for each flip-flop and 3-State outputs for bus-oriented
applications. A clock (CP) and an output enable (OE) input are
common to all flip-flops. The ten flip-flops will store the state of their
individual D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition. When OE is LOW, the contents
of the ten flip-flops is available at the outputs.
• Direct interface with TTL levels
• 10-bit positive edge-triggered register
• Independent register and 3-State buffer operation
• Flow-through pin-out architecture
When OE is HIGH, the outputs go to the high impedance OFF-state.
Operation of the OE input does not affect the state of the flip-flops.
QUICK REFERENCE DATA
GND = 0 V; T
= 25°C; t = t ≤ 2.5 ns
amb
r f
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
Propagation delay
t
/t
5.4
ns
PHL PLH
C = 50 pF;
CP to Q
L
n
V
CC
= 3.3 V
f
Maximum clock frequency
Input capacitance
150
5.0
MHz
pF
max
C
I
Power dissipation capacitance per
flip-flop
C
Notes 1 and 2
26
pF
PD
NOTES:
1. C is used to determine the dynamic power dissipation (P in µW)
PD
D
2
2
P
= C × V
× f )ȍ (C × V
× f ) where:
D
PD
CC
i
L
CC o
f = input frequency in MHz; C = output load capacity in pF;
i
L
f = output frequency in MHz; V = supply voltage in V;
o
CC
2
ȍ (C × V
× f ) = sum of the outputs.
L
CC
o
2. The condition is V = GND to V
I
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDERING CODE
PKG. DWG. #
24-Pin Plastic SO
–40°C to +85°C
74LVC821A D
SOT137-1
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
–40°C to +85°C
–40°C to +85°C
74LVC821A DB
74LVC821A PW
SOT340-1
SOT355-1
2
1998 Sep 25
853-1970 20088
Philips Semiconductors
Product specification
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
74LVC821A
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
Output enable input
(active LOW)
1
OE
2, 3, 4, 5, 6,
7, 8, 9, 10, 11
D to D
0
Data inputs
9
23, 22, 21, 20,
19, 18, 17, 16,
15, 14
Q to Q
3-State flip-flop outputs
Ground (0 V)
0
9
12
13
24
GND
CP
Clock input (LOW-to-HIGH,
edge-triggered)
V
CC
Positive supply voltage
FUNCTION TABLE
INPUTS
CP
OUTPUTS
OPERATING MODES
INTERNAL FLIP-FLOPS
OE
D
Q to Q
n
0
9
Load and read register
L
L
↑
↑
l
h
L
H
L
H
Load register and disable outputs
Hold
H
H
↑
↑
l
h
L
H
Z
Z
L
H or L
X
NC
NC
H = HIGH voltage level
h
= HIGH voltage level one set-up time prior to the LOW-to-HIGH
CP transition
L
l
= LOW voltage level
= LOW voltage level one set-up time prior to the LOW-to-HIGH
CP transition
Z
= high impedance OFF-state
↑
= LOW–to–HIGH clock transition
NC= no change
PIN CONFIGURATION
LOGIC SYMBOL
13
1
24
23
22
21
20
19
18
17
16
15
OE
V
CC
2
3
D
0
D
1
D
2
D
3
D
4
Q
0
CP
2
3
D
D
D
D
D
D
D
D
D
D
23
22
21
20
19
18
17
16
15
14
Q
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
Q
1
Q
2
Q
3
Q
4
Q
Q
Q
Q
Q
Q
Q
Q
Q
4
4
5
5
6
6
7
D
D
D
D
D
Q
5
Q
6
Q
7
Q
8
5
7
8
6
7
8
9
8
9
9
10
11
12
10
11
14 Q9
13
CP
GND
OE
1
SA00413
SA00414
3
1998 Sep 25
Philips Semiconductors
Product specification
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
74LVC821A
LOGIC SYMBOL (IEEE/IEC)
FUNCTIONAL DIAGRAM
2
3
4
5
D
D
D
D
23
22
21
20
19
18
17
16
15
14
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
0
1
2
3
13
0
1
2
3
4
5
6
7
8
9
C1
1
EN
2
23
1D
6
D
D
D
D
D
D
3
22
21
20
19
18
17
16
15
14
4
5
6
7
8
9
3–STATE
OUTPUTS
FF0 to FF9
7
4
5
8
6
9
7
10
11
13
1
8
9
CP
OE
10
11
SA00416
SA00415
LOGIC DIAGRAM
D
D
D
D
D
D
D
6
D
7
D
D
9
0
1
2
3
4
5
8
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
FF1
FF2
FF3
FF4
FF5
FF6
FF7
FF8
FF9
FF0
CP
OE
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
9
0
1
2
3
4
5
6
7
8
SA00417
4
1998 Sep 25
Philips Semiconductors
Product specification
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
74LVC821A
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN
2.7
1.2
0
MAX
DC supply voltage (for max. speed performance)
DC supply voltage (for low-voltage applications)
DC Input voltage range
3.6
3.6
5.5
V
CC
V
V
V
I
DC output voltage range; output HIGH or LOW
state
0
V
CC
V
O
V
DC output voltage range; output 3-State
0
5.5
T
amb
Operating ambient temperature range in free-air
–40
+85
°C
V
CC
V
CC
= 1.2 to 2.7V
= 2.7 to 3.6V
0
0
20
10
t , t
r
Input rise and fall times
ns/V
f
1
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
UNIT
V
V
CC
I
IK
–0.5 to +6.5
–50
DC input diode current
V t0
mA
V
I
V
I
DC input voltage
Note 2
uV or V t 0
–0.5 to +6.5
"50
I
DC output diode current
V
O
mA
OK
CC
O
DC output voltage; output HIGH or LOW state
DC output voltage; output 3-State
DC output source or sink current
Note 2
Note 2
–0.5 to V +0.5
CC
V
V
O
–0.5 to 6.5
"50
I
O
V
O
= 0 to V
CC
mA
mA
°C
I
, I
DC V or GND current
"100
GND CC
CC
T
stg
Storage temperature range
–65 to +150
Power dissipation per package
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
P
TOT
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
500
500
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5
1998 Sep 25
Philips Semiconductors
Product specification
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
74LVC821A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
1
MIN
TYP
MAX
V
V
V
V
V
V
V
V
V
V
V
= 1.2V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
V
HIGH level Input voltage
LOW level Input voltage
V
V
IH
= 2.7 to 3.6V
= 1.2V
2.0
GND
0.8
V
IL
= 2.7 to 3.6V
= 2.7V; V = V or V ; I = –12mA
V
V
V
V
*0.5
I
IH
IL
O
CC
CC
CC
CC
= 3.0V; V = V or V ; I = –100µA
*0.2
*0.6
*0.8
V
CC
I
IH
IL
O
O
O
V
OH
HIGH level output voltage
LOW level output voltage
V
V
= 3.0V; V = V or V
I
I
= –18mA
= –24mA
I
IH
IL;
IL;
= 3.0V; V = V or V
I
IH
= 2.7V; V = V or V ; I = 12mA
0.40
0.20
0.55
"5
I
IH
IL
O
= 3.0V; V = V or V ; I = 100µA
V
OL
I
IH
IL
O
O
= 3.0V; V = V or V
I
= 24mA
I
IH
IL;
"0.1
0.1
I
Input leakage current
V
CC
V
CC
V
CC
V
CC
= 3.6V; V = 5.5V or GND
µA
µA
µA
µA
I
I
I
3-State output OFF-state current
Power off leakage supply
Quiescent supply current
= 3.6V; V = V or V ; V = 5.5V or GND
I IH IL O
"5
"10
10
OZ
I
off
= 0.0V; V or V = 5.5V
0.1
I
O
I
= 3.6V; V = V or GND; I = 0
0.1
CC
I
CC
O
Additional quiescent supply current
per input pin
∆I
CC
V
CC
= 2.7V to 3.6V; V = V –0.6V; I = 0
5
500
µA
I
CC
O
NOTES:
1. All typical values are at V = 3.3V and T
= 25°C.
amb
CC
2. The specified overdrive current at the data input forces the data input to the opposite logic input state.
AC CHARACTERISTICS
GND = 0V; t = t v 2.5ns; C = 50pF; R = 500Ω; T = –40°C to +85°C.
r
f
L
L
amb
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V ±0.3V
V
CC
= 2.7V
UNIT
1
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
CP to Q
PHL
PLH
Figures 1, 4
Figures 2, 4
Figures 2, 4
Figure 1
1.5
5.4
7.3
1.5
8.5
8.8
6.8
–
ns
ns
ns
ns
ns
n
t
3-State output enable time
OE to Q
PZH
1.5
1.5
3.3
1.9
5.5
3.8
1.7
0.6
0
7.6
6.2
–
1.5
1.5
3.3
0.9
t
PZL
n
t
3-State output disable time
OE to Q
PHZ
t
PLZ
n
Clock pulse width
HIGH or LOW
t
W
Setup time
D to CP
n
t
Figure 3
–
–
SU
Hold time
D to CP
n
t
h
Figure 3
Figure 1
1.5
–
–
1.5
–
–
ns
f
Maximum clock pulse frequency
150
200
150
MHz
max
NOTE:
1. Unless otherwise stated, all typical values are at V = 3.3V and T
= 25°C.
amb
CC
6
1998 Sep 25
Philips Semiconductors
Product specification
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
74LVC821A
AC WAVEFORMS
V
V
= 1.5V at V w 2.7V; V = 0.5 V at V t 2.7V.
M
CC M CC CC
V
I
and V are the typical output voltage drop that occur with the
OL
OH
CP
output load.
V
INPUT
M
V
X
V
Y
= V + 0.3V at V w 2.7V; V = V + 0.1 V at V t2.7V
OL CC X OL CC CC
GND
= V –0.3V at V w2.7V; V = V – 0.1 V at V t2.7V
OH
CC
Y
OH
CC
CC
t
su
t
su
t
h
t
h
1/f
max
V
I
V
I
Dn
INPUT
V
M
V
V
V
M
M
M
CP INPUT
GND
GND
t
w
V
OH
t
PHL
t
PLH
Qn
OUTPUT
V
OH
V
M
V
V
Qn OUTPUT
M
M
V
OL
V
NOTE: The shaded areas indicate when the input is permitted to change
OL
for predictable output performance.
SA00394
SW00229
Figure 3. Data setup and hold times for the D input to the CP
Figure 1. Clock (CP) to output (Q ) propagation delays, the
n
n
input.
clock pulse width and the maximum clock pulse frequency.
TEST CIRCUIT
V
I
S
1
2 x V
Open
CC
V
CC
V
OE INPUT
GND
M
GND
500Ω
500Ω
V
V
O
I
PULSE
GENERATOR
D.U.T.
t
t
PZL
50pF
PLZ
C
L
R
T
V
CC
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
M
Test
/t
S
1
V
X
V
OL
V
V
CC
I
t
Open
PLH PHL
t 2.7V
2.7V – 3.6V
V
t
/t
2 x V
CC
CC
PLZ PZL
t
t
PZH
PHZ
2.7V
t
/t
GND
PHZ PZH
V
OH
SY00003
OUTPUT
V
Y
HIGH-to-OFF
OFF-to-HIGH
V
M
Figure 4. Load circuitry for switching times.
GND
outputs
enabled
outputs
enabled
outputs
disabled
SA00412
Figure 2. 3-State enable and disable times.
7
1998 Sep 25
Philips Semiconductors
Product specification
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
74LVC821A
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
8
1998 Sep 25
Philips Semiconductors
Product specification
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
74LVC821A
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
9
1998 Sep 25
Philips Semiconductors
Product specification
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
74LVC821A
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
10
1998 Sep 25
Philips Semiconductors
Product specification
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
74LVC821A
NOTES
11
1998 Sep 25
Philips Semiconductors
Product specification
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
74LVC821A
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 08-98
9397–750–04584
Document order number:
Philips
Semiconductors
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