74LVCH162374ADL,11 [NXP]
74LVCH162374A - 16-bit edge-triggered D-type flip-flop SSOP 48-Pin;
| 型号： | 74LVCH162374ADL,11 |
| 厂家： | 
NXP |
| 描述： | 74LVCH162374A - 16-bit edge-triggered D-type flip-flop SSOP 48-Pin 驱动 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总17页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVCH162374A
16-bit edge triggered D-type
flip-flop with 30 Ω series termination
resistors; 5 V input/output tolerant;
3-state
Product specification
2004 May 19
Supersedes data of 2004 Mar 25
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVCH162374A
FEATURES
3-state outputs for bus oriented applications. The
74LVCH162374A consists of 2 sections of eight
• 5 V tolerant inputs/outputs for interfacing with 5 V logic
• Wide supply voltage range from 1.2 V to 3.6 V
• CMOS low power consumption
edge-triggered flip-flops. A clock (CP) input and an output
enable (OE) are provided for each octal. Inputs can be
driven from either 3.3 V or 5 V devices. In 3-state
operation, outputs can handle 5 V. These features allow
the use of these devices in a mixed 3.3 V and 5 V
environment.
• MULTIBYTE flow-through standard pin-out architecture
• Low inductance multiple power and ground pins for
minimum noise and ground bounce
The flip-flops will store the state of their individual D-inputs
that meet the set-up and hold time requirements on the
LOW-to-HIGH CP transition.
• Direct interface with TTL levels
• All data inputs have bushold
• High-impedance outputs when VCC = 0 V
• Complies with JEDEC standard JESD8-B/JESD36
• ESD protection:
When OE is LOW, the contents of the flip-flops are
available at the outputs. When OE is HIGH, the outputs go
to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the flip-flops.
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 °C to +85 °C and −40 °C to +125 °C.
The 74LVCH162374A bushold data inputs eliminates the
need for external pull-up resistors to hold unused inputs.
The 74LVCH162374A is designed with 30 Ω series
termination resistors in both high and low output stages to
reduce line noise.
DESCRIPTION
The 74LVCH162374A is a 16-bit edge triggered flip-flop
featuring separate D-type inputs for each flip-flop and
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
tPHL/tPLH
PARAMETER
CONDITIONS
TYPICAL
3.7
UNIT
propagation delay nCP to nQn
CL = 50 pF; VCC = 3.3 V
ns
ns
ns
tPZH/tPZL
tPHZ/tPLZ
fmax
3-state output enable time nOE to nQn CL = 50 pF; VCC = 3.3 V
3-state output disable time nOE to nQn CL = 50 pF; VCC = 3.3 V
maximum clock frequency
3.4
3.1
330
5.0
MHz
pF
CI
input capacitance
CPD
power dissipation capacitance per
flip-flop
VCC = 3.3 V; notes 1 and 2
outputs enabled
pF
13.5
10
pF
outputs disabled
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC
.
2004 May 19
2
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVCH162374A
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
INTERNAL
FLIP-FLOP
OPERATION MODES
nOE
nCP
nD0 to nD7
nQ0 to nQ7
L
L
↑
↑
↑
↑
l
L
H
L
L
H
Z
Z
Load and read register
h
l
H
H
Latch register and disable outputs
h
H
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH CP transition.
ORDERING INFORMATION
PACKAGE
TEMPERATURE
TYPE NUMBER
RANGE
PINS
48
PACKAGE MATERIAL
CODE
74LVCH162374ADGG
74LVCH162374ADL
−40 °C to +125 °C
−40 °C to +125 °C
TSSOP48
SSOP48
plastic
plastic
SOT362-1
SOT370-1
48
2004 May 19
3
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVCH162374A
PINNING
PIN
SYMBOL
DESCRIPTION
PIN
SYMBOL
DESCRIPTION
39
40
41
42
43
44
45
46
47
48
GND
1D5
1D4
VCC
1D3
1D2
GND
1D1
1D0
1CP
ground (0 V)
1
1OE
output enable input (active
LOW)
data input
data input
supply voltage
data input
data input
ground (0 V)
data input
data input
clock input
2
1Q0
1Q1
GND
1Q2
1Q3
VCC
data output
data output
ground (0 V)
data output
data output
supply voltage
data output
data output
ground (0 V)
data output
data output
data output
data output
ground (0 V)
data output
data output
supply voltage
data output
data output
ground (0 V)
data output
data output
3
4
5
6
7
8
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
VCC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1CP
1D0
1
2
3
4
5
6
7
8
9
48
47
1OE
1Q0
1Q1
GND
1Q2
1Q3
46 1D1
45 GND
44 1D2
43 1D3
V
V
CC
42
41
40
39
38
CC
1D4
1D5
GND
1D6
1Q4
1Q5
2Q4
2Q5
GND
2Q6
2Q7
2OE
GND 10
1Q6 11
1Q7 12
2Q0 13
2Q1 14
GND 15
2Q2 16
2Q3 17
37 1D7
36 2D0
35 2D1
34 GND
33 2D2
32 2D3
162374A
output enable input (active
LOW)
25
26
27
28
29
30
31
32
33
34
35
36
37
38
2CP
2D7
2D6
GND
2D5
2D4
VCC
2D3
2D2
GND
2D1
2D0
1D7
1D6
clock input
data input
data input
ground (0 V)
data input
data input
supply voltage
data input
data input
ground (0 V)
data input
data input
data input
data input
V
CC
18
31 V
CC
2Q4 19
2Q5 20
30
29
2D4
2D5
21
22
23
24
28 GND
27 2D6
26 2D7
GND
2Q6
2Q7
2OE
25
2CP
001aab023
Fig.1 Pin configuration SSOP48 and TSSOP48.
2004 May 19
4
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVCH162374A
1D0
D
Q
1Q0
2D0
D
Q
2Q0
CP
CP
FF1
FF2
1CP
1OE
2CP
2OE
to 7 other channels
to 7 other channels
001aaa255
Fig.2 Logic diagram.
1
1EN
C3
1OE
1CP
2OE
2CP
1
24
48
24
25
2EN
C4
1OE
2OE
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2
3
3
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
3D
1
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
5
5
6
6
8
8
9
11
12
13
14
16
17
19
20
22
23
9
11
12
13
14
16
17
19
20
22
23
4D
2
1CP
48
2CP
25
001aaa253
001aaa254
Fig.3 Logic symbol.
Fig.4 Logic symbol (IEEE/IEC).
2004 May 19
5
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVCH162374A
V
handbook, halfpage
CC
data input
to internal circuit
MGU771
Fig.5 Bushold circuit.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
MAX.
3.6
UNIT
VCC
for maximum speed performance 2.7
V
for low voltage applications
1.2
0
3.6
V
VI
input voltage
5.5
V
VO
output voltage
output HIGH or LOW state
output 3-state
0
VCC
5.5
V
0
V
Tamb
tr, tf
operating ambient
temperature
in free air
−40
+125
°C
input rise and fall times
VCC = 1.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
0
0
20
10
ns/V
ns/V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+6.5
UNIT
VCC
IIK
V
input diode current
input voltage
VI < 0 V
note 1
−
−50
mA
V
VI
−0.5
−
+6.5
±50
IOK
VO
output diode current
output voltage
VO > VCC or VO < 0 V
mA
V
output HIGH or LOW state; note 1 −0.5
VCC + 0.5
+6.5
±50
output 3-state; note 1
VO = 0 V to VCC
−0.5
−
V
IO
output source or sink current
mA
mA
°C
mW
ICC, IGND VCC or GND current
−
±100
+150
500
Tstg
Ptot
storage temperature
power dissipation
−65
−
Tamb = −40 °C to +125 °C; note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
2004 May 19
6
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVCH162374A
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 °C to +85 °C; note 1
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
1.2
VCC
−
−
−
−
−
−
V
2.7 to 3.6
1.2
2.0
−
V
V
V
GND
0.8
2.7 to 3.6
−
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −6 mA
IO = −100 µA
IO = −12 mA
2.7
3.0
3.0
V
V
V
CC − 0.5
−
−
−
−
V
V
V
CC − 0.2
CC − 0.8
VCC
−
VOL
LOW-level output voltage
input leakage current
VI = VIH or VIL
IO = 6 mA
2.7
3.0
3.0
3.6
−
−
−
−
−
0.40
0.20
0.55
±5
V
IO = 100 µA
IO = 12 mA
GND
−
V
V
ILI
VI = 5.5 V or GND;
note 2
±0.1
µA
IOZ
3-state output OFF-state
current
VI = VIH or VIL;
VO = 5.5 V or GND;
note 2
3.6
−
±0.1
±5
µA
Ioff
power-off leakage supply
current
VI or VO = 5.5 V
0.0
−
−
−
±0.1
0.1
5
±10
20
500
−
µA
µA
µA
µA
µA
µA
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0 A
3.6
∆ICC
IBHL
IBHH
IBHLO
IBHHO
additional quiescent supply VI = VCC − 0.6 V;
current per input pin
2.7 to 3.6
3.0
IO = 0 A
bushold LOW sustaining
current
VI = 0.8 V;
notes 3 and 4
75
−
bushold HIGH sustaining
current
VI = 2.0 V;
notes 3 and 4
3.0
−75
500
−500
−
−
bushold LOW overdrive
current
notes 3 and 5
3.6
−
−
bushold HIGH overdrive
current
notes 3 and 5
3.6
−
−
2004 May 19
7
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVCH162374A
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 °C to +125 °C
VIH
HIGH-level input voltage
LOW-level input voltage
1.2
VCC
−
−
−
−
−
−
V
2.7 to 3.6
1.2
2.0
−
V
V
V
VIL
GND
0.8
2.7 to 3.6
−
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −6 mA
IO = −100 µA
IO = −12 mA
2.7
3.0
3.0
V
V
V
CC − 0.5
−
−
−
−
−
−
V
V
V
CC − 0.2
CC − 0.8
VOL
LOW-level output voltage
input leakage current
VI = VIH or VIL
IO = 6 mA
2.7
3.0
3.0
3.6
−
−
−
−
−
−
−
−
0.40
0.20
0.55
±20
V
IO = 100 µA
IO = 12 mA
V
V
ILI
VI = 5.5 V or GND;
note 2
µA
IOZ
3-state output OFF-state
current
VI = VIH or VIL;
VO = 5.5 V or GND;
note 2
3.6
−
−
±20
µA
Ioff
power-off leakage supply
current
VI or VO = 5.5 V
0.0
−
−
−
−
−
−
−
−
−
−
±20
80
5000
−
µA
µA
µA
µA
µA
µA
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0 A
3.6
∆ICC
IBHL
IBHH
IBHLO
IBHHO
additional quiescent supply VI = VCC − 0.6 V;
current per input pin
2.7 to 3.6
3.0
IO = 0 A
bushold LOW sustaining
current
VI = 0.8 V;
notes 3 and 4
60
bushold HIGH sustaining
current
VI = 2.0 V;
notes 3 and 4
3.0
−60
500
−500
−
bushold LOW overdrive
current
notes 3 and 5
3.6
−
bushold HIGH overdrive
current
notes 3 and 5
3.6
−
Notes
1. All typical values are measured at Tamb = 25 °C.
2. The bushold circuit is switched off when VI > VCC allowing 5.5 V on the input pin.
3. For data inputs only, control inputs do not have a bushold circuit.
4. The specified sustaining current at the data inputs do not have a bushold circuit.
5. The specified overdrive current at the data input forces the data input to the opposite logic input state.
2004 May 19
8
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVCH162374A
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω.
CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP. MAX. UNIT
WAVEFORMS
VCC (V)
Tamb = −40 °C to +85 °C; note1
tPHL/tPLH propagation delay nCP to nQn
see Figs. 6 and 9 1.2
2.7
−
14
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
1.5
−
7.8
3.0 to 3.6 1.5
3.7(2) 6.8
tPZH/tPZL 3-state output enable time nOE to nQn see Figs. 8 and 9 1.2
2.7
−
20
−
1.5
−
8.3
3.0 to 3.6 1.5
3.4(2) 6.6
tPHZ/tPLZ 3-state output disable time nOE to nQn see Figs. 8 and 9 1.2
2.7
−
12
−
1.5
−
4.6
3.0 to 3.6 1.5
3.1(2) 4.4
tW
tsu
th
nCP pulse width HIGH
set-up time nDn to nCP
hold time nDn to nCP
see Fig.6
see Fig.7
see Fig.7
1.2
2.7
−
−
−
3.0
−
−
3.0 to 3.6 3.0
1.5(2)
−
1.2
2.7
−
−
−
1.9
−
−
3.0 to 3.6 1.9
0.3(2)
−
1.2
2.7
−
−
−
1.5
−
−
3.0 to 3.6 1.5
−0.3(2)
−
tsk(0)
fmax
skew
note 3
3.0 to 3.6
2.7
−
−
1.0
−
maximum clock pulse frequency
see Fig.6
150
−
3.0 to 3.6 150
330(2)
−
2004 May 19
9
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVCH162374A
CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP. MAX. UNIT
WAVEFORMS
VCC (V)
Tamb = −40 °C to +125 °C
tPHL/tPLH propagation delay nCP to nQn
see Figs. 6 and 9 1.2
2.7
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
1.5
10.0
8.5
−
3.0 to 3.6 1.5
tPZH/tPZL
3-state output enable time nOE to nQn see Figs. 8 and 9 1.2
2.7
−
1.5
10.5
8.5
−
3.0 to 3.6 1.5
tPHZ/tPLZ
3-state output disable time nOE to nQn see Figs. 8 and 9 1.2
2.7
−
1.5
6.0
5.5
−
3.0 to 3.6 1.5
tW
tsu
th
nCP pulse width HIGH
set-up time nDn to nCP
hold time nDn to nCP
see Fig.6
see Fig.7
see Fig.7
1.2
2.7
−
3.0
−
3.0 to 3.6 3.0
−
1.2
2.7
−
−
1.9
−
3.0 to 3.6 1.9
−
1.2
2.7
−
−
1.5
−
3.0 to 3.6 1.5
−
tsk(0)
fmax
skew
note 3
3.0 to 3.6
2.7
−
1.5
−
maximum clock pulse frequency
see Fig.6
150
3.0 to 3.6 150
−
Notes
1. All typical values are measured at Tamb = 25 °C.
2. These typical values are measured at VCC = 3.3 V.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed
by design.
2004 May 19
10
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVCH162374A
AC WAVEFORMS
1/f
max
V
I
nCP input
V
t
V
M
M
GND
t
W
t
PHL
PLH
V
OH
V
M
nQn output
001aaa256
V
OL
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.6 Clock input (nCP) to output (nQn) propagation delay, the clock pulse width and the maximum clock pulse
frequency.
V
I
V
M
nCP input
GND
t
t
su
su
t
t
h
h
V
I
V
M
nDn input
GND
V
OH
V
M
nQn output
V
OL
001aaa257
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.7 Data set-up and hold times for the nDn input to the nCP input.
11
2004 May 19
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVCH162374A
V
I
nOE input
GND
V
M
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna362
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V;
VX = VOL + 0.3 V at VCC ≥ 2.7 V;
VX = VOL + 0.1 V at VCC < 2.7 V;
VY = VOH − 0.3 V at VCC ≥ 2.7 V;
VY = VOH − 0.1 V at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.8 3-state enable and disable times.
2004 May 19
12
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVCH162374A
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
R
R
L
L
T
MNA616
VEXT
tPLH/tPHL tPZH/tPHZ tPZL/tPLZ
VCC
VI
VCC
CL
RL
1.2 V
50 pF
50 pF
50 pF
500 Ω(1) open
GND
GND
GND
2 × VCC
2 × VCC
2 × VCC
2.7 V
2.7 V
2.7 V
500 Ω
500 Ω
open
open
3.0 V to 3.6 V
Note
1. The circuit performs better when RL = 1000 Ω.
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.9 Load circuitry for switching times.
2004 May 19
13
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVCH162374A
PACKAGE OUTLINES
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
D
E
A
X
c
y
H
v
M
A
E
Z
25
48
Q
A
2
A
A
(A )
3
1
θ
pin 1 index
L
p
L
24
1
detail X
w
M
b
p
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.
8o
0o
0.4
0.2
2.35
2.20
0.3
0.2
0.22 16.00
0.13 15.75
7.6
7.4
10.4
10.1
1.0
0.6
1.2
1.0
0.85
0.40
mm
2.8
0.25
0.635
1.4
0.25
0.18
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT370-1
MO-118
2004 May 19
14
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVCH162374A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
H
v
M
A
y
E
Z
48
25
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
24
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.8
0.4
mm
1.2
0.5
1
0.25
0.25
0.08
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT362-1
MO-153
2004 May 19
15
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVCH162374A
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2004 May 19
16
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R20/03/pp17
Date of release: 2004 May 19
Document order number: 9397 750 13233
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