74LVCH32374AEC/G,5_技术文档

74LVCH32374A

32-bit edge-triggered D-type flip-flop with 5 V tolerant

inputs/outputs; 3-state

Rev. 3 — 18 December 2012

Product data sheet

1. General description

The 74LVCH32374A is a 32-bit edge-triggered flip-flop featuring separate D-type inputs

for each flip-flop and 3-state outputs for bus oriented applications. The device consists of

4 sections of 8 edge-triggered flip-flops. A clock (pin nCP) input and an output enable

input (pin nOE) are provided per 8-bit section. The flip-flops will store the state of their

individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH

nCP transition. When pin nOE is LOW, the contents of the flip-flops are available at the

outputs. When pin nOE is HIGH, the outputs go to the high-impedance OFF-state.

Operation of pin nOE does not affect the state of the flip-flops. The inputs can be driven

from either 3.3 V or 5 V devices. In 3-state operation, the outputs can handle 5 V. These

features allow the use of these devices in a mixed 3.3 V or 5 V environment.

Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused

inputs.

2. Features and benefits

 5 V tolerant inputs/outputs for interfacing with 5 V logic

 Wide supply voltage range from 1.2 V to 3.6 V

 CMOS low power consumption

 Multibyte flow-through standard pin-out architecture

 Multiple low inductance supply pins for minimum noise and ground bounce

 Direct interface with TTL levels

 All data inputs have bus hold

 High impedance when V_CC= 0 V

 Latch-up performance exceeds 500 mA per JESD 78 Class II

 Complies with JEDEC standard:

 JESD8-7A (1.65 V to 1.95 V)

 JESD8-5A (2.3 V to 2.7 V)

 JESD8-C/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-B exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Specified from 40 C to +85 C and 40 C to +125 C

 Packaged in plastic fine-pitch ball grid array package

74LVCH32374A

NXP Semiconductors

32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVCH32374AEC 40 C to +125 C

LFBGA96 plastic low profile fine-pitch ball grid array package;

SOT536-1

96 balls; body 13.5  5.5  1.05 mm

4. Functional diagram

1D0

2D0

1Q0

2Q0

D

Q

D

Q

CP

FF 1

CP

FF 9

1CP

1OE

2CP

2OE

to 7 other channels

3D0

4D0

3Q0

4Q0

D

Q

D

Q

CP

FF 17

FF 25

3CP

3OE

4CP

4OE

to 7 other channels

coa012

Fig 1. Logic symbol

V

CC

data

input

to internal circuit

mna473

Fig 2. Bus hold circuit

74LVCH32374A

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Product data sheet

Rev. 3 — 18 December 2012

2 of 15

74LVCH32374A

NXP Semiconductors

32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

5. Pinning information

5.1 Pinning

001aah180

6

5

4

3

2

1

1D1 1D3 1D5 1D7 2D1 2D3 2D5 2D6 3D1 3D3 3D5 3D7 4D1 4D3 4D5 4D6

1D0 1D2 1D4 1D6 2D0 2D2 2D4 2D7 3D0 3D2 3D4 3D6 4D0 4D2 4D4 4D7

V

1CP GND

1OE GND

GND GND

GND 2CP 3CP GND

GND 2OE 3OE GND

GND GND

GND 4CP

GND 4OE

CC

1Q0 1Q2 1Q4 1Q6 2Q0 2Q2 2Q4 2Q7 3Q0 3Q2 3Q4 3Q6 4Q0 4Q2 4Q4 4Q7

1Q1 1Q3 1Q5 1Q7 2Q1 2Q3 2Q5 2Q6 3Q1 3Q3 3Q5 3Q7 4Q1 4Q3 4Q5 4Q6

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

Fig 3. Pin configuration

5.2 Pin description

Table 2.

Symbol

nOE (n = 1 to 4)

nCP (n = 1 to 4)

1D[0:7]

Pin description

Ball

Description

A3, H3, J3, T3

A4, H4, J4, T4

output enable input (active LOW)

clock input

A5, A6, B5, B6, C5, C6, D5, D6

E5, E6, F5, F6, G5, G6, H6, H5

J5, J6, K5, K6, L5, L6, M5, M6

N5, N6, P5, P6, R5, R6, T6, T5

A2, A1, B2, B1, C2, C1, D2, D1

E2, E1, F2, F1, G2, G1, H1, H2

J2, J1, K2, K1, L2, L1, M2, M1

N2, N1, P2, P1, R2, R1, T1, T2

data input

2D[0:7]

data input

3D[0:7]

data input

4D[0:7]

data input

1Q[0:7]

data output

2Q[0:7]

data output

3Q[0:7]

data output

4Q[0:7]

data output

GND

B3, B4, D3, D4, E3, E4, G3, G4, K3, K4, M3, ground (0 V)

M4, N3, N4, R3, R4

V_CC

C3, C4, F3, F4, L3, L4, P3, P4

supply voltage

74LVCH32374A

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Product data sheet

Rev. 3 — 18 December 2012

3 of 15

74LVCH32374A

NXP Semiconductors

32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

6. Functional description

Table 3.

Function table^[1]

Operating mode Input

nOE

Internal flip-flop

Output

nCP



nDn

nQn

L

Load and read

register

L

l

L



h

l

H

L

H

Load register and

disable outputs

H



Z



h

H

Z

[1] H = HIGH voltage level

L = LOW voltage level

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition

l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition

Z = high-impedance OFF-state

 = LOW-to-HIGH CP transition

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)^[1]

Symbol

V_CC

I_IK

Parameter

Conditions

Min

0.5

50

0.5

-

Max

+6.5

-

Unit

V

supply voltage

input clamping current

input voltage

V_I< 0

mA

V

[2]

V_I

+6.5

50

I_OK

output clamping current

output voltage

V_O> V_CCor V_O< 0

output HIGH or LOW state

output 3-state

mA

V

[3]

V_O

0.5

-

V_CC+ 0.5

+6.5

50

V

I_O

output current

V_O= 0 V to V_CC

mA

C

I_CC

I_GND

T_stg

P_tot

supply current

-

200

ground current

200

65

-

storage temperature

total power dissipation

+150

1000

[4]

T_amb= 40 C to +125 C

mW

[1] All supply and ground pins connected externally to one voltage source.

[2] The minimum input voltage ratings may be exceeded if the input current ratings are observed.

[3] The output voltage ratings may be exceeded if the output current ratings are observed.

[4] Above 70 C the value of P_totderate linearly with 1.8 mW/K.

74LVCH32374A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 December 2012

4 of 15

74LVCH32374A

NXP Semiconductors

32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

8. Recommended operating conditions

Table 5.

Symbol

V_CC

Recommended operating conditions

Parameter

Conditions

Min

1.65

1.2

0

Typ

Max

3.6

5.5

V_CC

5.5

Unit

V

supply voltage

-

functional

V

V_I

input voltage

V

V_O

output voltage

output HIGH or LOW state

output 3-state

0

V

0

V

T_amb

ambient temperature

in free air

40

-

+125

20

C

ns/V

t/V

input transition rise and fall rate V_CC= 1.65 V to 2.7 V

V_CC= 2.7 V to 3.6 V

-

10

9. Static characteristics

Table 6.

Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

40 C to +85 C

Min Max

Typ^[1]

1.08

40 C to +125 C

Min Max

1.08

Unit

V_IH

HIGH-level

V_CC= 1.2 V

-

V

input voltage

V_CC= 1.65 V to 1.95 V

0.65  V_CC

-

0.65  V_CC

V_CC= 2.3 V to 2.7 V

1.7

-

1.7

V_CC= 2.7 V to 3.6 V

V_CC= 1.2 V

2.0

-

2.0

V_IL

LOW-level

-

0.12

-

0.12

input voltage

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_I= V_IHor V_IL

0.35  V_CC

0.7

0.35  V_CC

0.7

0.8

V_OH

HIGH-level

output voltage

I_O= 100 A;

V_CC 0.2

-

V_CC 0.3

-

V

V_CC= 1.65 V to 3.6 V

I_O= 4 mA; V_CC= 1.65 V 1.2

I_O= 8 mA; V_CC= 2.3 V 1.8

-

1.05

1.65

2.05

2.25

2.0

-

V

I_O= 12 mA; V_CC= 2.7 V 2.2

I_O= 18 mA; V_CC= 3.0 V 2.4

I_O= 24 mA; V_CC= 3.0 V 2.2

V_I= V_IHor V_IL

V_OL

LOW-level

output voltage

I_O= 100 A;

_CC= 1.65 V to 3.6 V

-

0.2

-

0.3

V

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

-

0.45

0.6

-

0.65

0.8

V

-

V

-

0.4

0.6

V

-

0.55

5

0.8

V

I_I

input leakage

current

V_CC= 3.6 V;

V_I= 5.5 V or GND^[2]

0.1

20

A

74LVCH32374A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 December 2012

5 of 15

74LVCH32374A

NXP Semiconductors

32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

Table 6.

Static characteristics ...continued

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C

Unit

Min

Typ^[1]

Max

Min

Max

20

I_OZ

OFF-state

output current

V_I= V_IHor V_IL; V_CC= 3.6 V;

V_O= 5.5 V or GND^[2]

-

0.1

5

-

A

I_OFF

I_CC

power-off

leakage current

V_CC= 0 V; V_Ior V_O= 5.5 V

0.1

0.1

5

10

40

20

supply current V_CC= 3.6 V;

V_I= V_CCor GND; I_O= 0 A

160

I_CC

additional

supply current

per input pin;

V_CC= 2.7 V to 3.6 V;

500

5000

V_I= V_CC 0.6 V; I_O= 0 A

C_I

input

capacitance

V_CC= 0 V to 3.6 V;

V_I= GND to V_CC

-

5.0

-

pF

I_BHL

bus hold LOW V_CC= 1.65; V_I= 0.58 V^[3][4]

10

30

-

10

25

-

A

current

V_CC= 2.3; V_I= 0.7 V

V_CC= 3.0; V_I= 0.8 V

bus hold HIGH V_CC= 1.65; V_I= 1.07 V^[3][4]

75

60

I_BHH

10

30

75

200

300

500

200

300

500

10

25

60

200

300

500

200

300

500

current

V_CC= 2.3; V_I= 1.7 V

V_CC= 3.0; V_I= 2.0 V

bus hold LOW V_CC= 1.95 V^[3][5]

I_BHLO

overdrive

current

V_CC= 2.7 V

V_CC= 3.6 V

I_BHHO

bus hold HIGH V_CC= 1.95 V^[3][5]

overdrive

current

V_CC= 2.7 V

V_CC= 3.6 V

[1] All typical values are measured at V_CC= 3.3 V and T_amb= 25 C.

[2] The bus hold circuit is switched off when V_I> V_CCallowing 5.5 V on the input pin.

[3] Valid for data inputs only. Control inputs do not have a bus hold circuit.

[4] The specified sustaining current at the data input holds the input below the specified V_Ilevel.

[5] The specified overdrive current at the data input forces the data input to the opposite logic input state.

74LVCH32374A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 December 2012

6 of 15

74LVCH32374A

NXP Semiconductors

32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

10. Dynamic characteristics

Table 7.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C Unit

Min

Typ^[1]

Max

Min

Max

[2]

t_pd

t_en

t_dis

propagation

delay

nCP to nQn; see Figure 4

V_CC= 1.2 V

-

14

6.9

3.7

3.4

3.1

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

2.1

1.5

13.5

6.7

6.0

5.4

2.1

1.5

15.6

7.7

7.5

7.0

V_CC= 3.0 V to 3.6 V

nOE to nQn; see Figure 6

V_CC= 1.2 V

enable time

-

20

5.9

3.4

3.6

2.7

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.5

1.0

13.1

6.9

6.0

5.2

1.5

1.0

15.1

8.0

7.5

6.5

V_CC= 3.0 V to 3.6 V

nOE to nQn; see Figure 4

V_CC= 1.2 V

disable time

-

12

4.6

2.5

3.4

3.1

-

ns

V_CC= 1.65 V to 1.95 V

2.8

1.0

1.5

9.1

4.9

5.1

4.9

2.8

1.0

1.5

10.5

5.7

6.5

V

_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

nCP HIGH; see Figure 4

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

t_W

t_su

t_h

pulse width

set-up time

hold time

5.0

4.0

3.0

-

5.0

4.0

3.0

-

ns

-

V_CC= 3.0 V to 3.6 V

nDn to nCP; see Figure 5

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.5

4.0

3.0

1.9

-

4.0

3.0

1.9

-

ns

-

V_CC= 3.0 V to 3.6 V

nDn to nCP; see Figure 5

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

0.3

3.0

2.5

1.1

1.5

-

3.0

2.5

1.1

1.5

-

ns

-

V_CC= 3.0 V to 3.6 V

0.3

74LVCH32374A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 December 2012

7 of 15

74LVCH32374A

NXP Semiconductors

32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

Table 7.

Dynamic characteristics ...continued

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C Unit

Min

Typ^[1]

Max

Min

Max

f_max

maximum

frequency

see Figure 4

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

100

125

150

-

80

100

120

-

ns

-

ns

-

300

-

MHz

ns

V_CC= 3.0 V to 3.6 V

-

[3]

[4]

t_sk(o)

C_PD

output skew

time

1.0

1.5

power

dissipation

capacitance

per input; V_I= GND to V_CC

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

-

14.1

16.4

18.5

-

pF

V_CC= 3.0 V to 3.6 V

[1] Typical values are measured at T_amb= 25 C and V_CC= 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.

[2] t_pdis the same as t_PLHand t_PHL

t_enis the same as t_PZLand t_PZH

t_disis the same as t_PLZand t_PHZ

[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[4] _PDis used to determine the dynamic power dissipation (P_Din W).

.

C

P_D= C_PD V_CC² f_i N + (C_L V_CC² f_o) where:

f_i= input frequency in MHz; f_o= output frequency in MHz

C_L= output load capacitance in pF

V_CC= supply voltage in Volts

N = number of inputs switching

(C_L V_CC² f_o) = sum of the outputs

11. Waveforms

1/f

max

V

I

nCP input

V

t

V

M

GND

t

W

t

PHL

PLH

V

OH

V

nQn output

M

001aaa256

V

OL

Measurement points are given in Table 8.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 4. Clock (nCP) to output (nQn) propagation delays, the clock pulse width and the maximum clock frequency

74LVCH32374A

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Product data sheet

Rev. 3 — 18 December 2012

8 of 15

74LVCH32374A

NXP Semiconductors

32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

V

I

V

nCP input

M

GND

t

su

t

h

V

I

V

nDn input

M

GND

V

OH

V

nQn output

M

V

OL

001aaa257

Measurement points are given in Table 8.

_OLand V_OHare typical output voltage levels that occur with the output load.

V

Fig 5. Set-up and hold times for inputs (nDn) to inputs (nCP)

V

I

nOE input

V

M

GND

t

PZL

PLZ

V

CC

output

LOW-to-OFF

OFF-to-LOW

V

M

V

X

V

OL

t

PZH

PHZ

V

OH

V

Y

output

HIGH-to-OFF

OFF-to-HIGH

V

M

GND

outputs

enabled

outputs

enabled

outputs

disabled

mna478

Measurement points are given in Table 8.

_OLand V_OHare typical output voltage levels that occur with the output load.

V

Fig 6. 3-state output enable and disable times

74LVCH32374A

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Product data sheet

Rev. 3 — 18 December 2012

9 of 15

74LVCH32374A

NXP Semiconductors

32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

Table 8.

Measurement points

Supply voltage

V_CC

Input

V_I

Output

V_M

V_X

V_Y

1.2 V

V_CC

2.7 V

0.5  V_CC

1.5 V

0.5  V_CC

1.5 V

V_OL+ 0.15 V

V_OL+ 0.3 V

V_OH 0.15 V

V_OH 0.3 V

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

3.0 V to 3.6 V

1.5 V

V

EXT

V

CC

R

L

V

O

I

G

DUT

R

T

C

L

R

mna616

Test data is given in Table 9. Definitions for test circuit:

R_L= Load resistance

C_L= Load capacitance including jig and probe capacitance

R_T= Termination resistance should be equal to the output impedance Z_oof the pulse generator

Fig 7. Load circuitry for switching times

Table 9.

Test data

Supply voltage

Input

V_I

Load

C_L

V_EXT

t_r, t_f

R_L

t_PLH, t_PHL

open

t_PLZ, t_PZL

t_PHZ, t_PZH

1.2 V

V_CC

2.7 V

 2 ns

 2.5 ns

30 pF

50 pF

1 k

500 

2  V_CC

GND

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

open

3.0 V to 3.6 V

open

74LVCH32374A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 December 2012

10 of 15

74LVCH32374A

NXP Semiconductors

32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

12. Package outline

LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1

B

A

D

ball A1

index area

A

2

A

E

A

1

detail X

e

1

C

1/2 e

y

∅ v M

∅ w M

C

A B

C

1

e

b

T

R

P

N

e

M

L

K

J

H

G

F

e

2

1/2 e

E

D

C

B

A

ball A1

index area

1

2

3

4

5

6

X

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

b

e

v

w

y

1

D

E

1

2

1

2

max.

0.41

0.31

1.2

0.9

0.51

0.41

5.6

5.4

13.6

13.4

mm

1.5

4

12

0.1

0.2

0.8

0.15

0.1

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

00-03-04

03-02-05

SOT536-1

Fig 8. Package outline SOT536-1 (LFBGA96)

74LVCH32374A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 December 2012

11 of 15

74LVCH32374A

NXP Semiconductors

32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

13. Abbreviations

Table 10. Abbreviations

Acronym

CDM

DUT

Description

Charged Device Model

Device Under Test

ESD

ElectroStatic Discharge

Human Body Model

Machine Model

HBM

MM

TTL

Transistor-Transistor Logic

14. Revision history

Table 11. Revision history

Document ID

Release date

20121218

Data sheet status

Change notice

Supersedes

74LVCH32374A v.3

Modifications:

Product data sheet

-

74LVCH32374A v.2

• The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Table 4, Table 5, Table 6 , Table 7, Table 8 and Table 9: values added for lower voltage

ranges.

74LVCH32374A v.2

74LVCH32374A v.1

20040519

19991124

Product specification

-

74LVCH32374A v.1

-

74LVCH32374A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 December 2012

12 of 15

74LVCH32374A

NXP Semiconductors

32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

15.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

74LVCH32374A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 December 2012

13 of 15

74LVCH32374A

NXP Semiconductors

32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

74LVCH32374A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 December 2012

14 of 15

74LVCH32374A

NXP Semiconductors

32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

17. Contents

1

2

3

4

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6

Functional description . . . . . . . . . . . . . . . . . . . 4

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

Recommended operating conditions. . . . . . . . 5

Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12

7

8

9

10

11

12

13

14

15

Legal information. . . . . . . . . . . . . . . . . . . . . . . 13

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

15.1

15.2

15.3

15.4

16

17

Contact information. . . . . . . . . . . . . . . . . . . . . 14

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 18 December 2012

Document identifier: 74LVCH32374A


型号：	74LVCH32374AEC/G,5
厂家：	NXP
描述：	74LVCH32374A - 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state BGA 96-Pin 驱动逻辑集成电路触发器
文件：	总15页 (文件大小：120K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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