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74LVT02DB,118 [NXP]

74LVT02 - 3.3 V Quad 2-input NOR gate SSOP1 14-Pin;
74LVT02DB,118
型号： 74LVT02DB,118
厂家： NXP    NXP
描述：

74LVT02 - 3.3 V Quad 2-input NOR gate SSOP1 14-Pin

PC 信息通信管理 光电二极管 逻辑集成电路
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INTEGRATED CIRCUITS  
74LVT02  
3.3V Quad 2-input NOR gate  
Product specification  
IC24 Data Handbook  
1996 Aug 15  
Philips  
Semiconductors  
Philips Semiconductors  
Product specification  
3.3V Quad 2-input NOR gate  
74LVT02  
QUICK REFERENCE DATA  
CONDITIONS  
= 25°C;  
T
SYMBOL  
PARAMETER  
TYPICAL  
UNIT  
amb  
GND = 0V  
Propagation delay  
An or Bn  
to Yn  
t
t
C = 50pF;  
2.8  
2.6  
PLH  
PHL  
L
ns  
V
CC  
= 3.3V  
C
Input capacitance  
V = 0V or 3.0V  
3
1
pF  
IN  
I
I
Total supply current  
Outputs Low; V = 3.6V  
mA  
CCL  
CC  
ORDERING INFORMATION  
PACKAGES  
TEMPERATURE RANGE OUTSIDE NORTH AMERICA  
NORTH AMERICA  
74LVT02 D  
DWG NUMBER  
SOT108-1  
14-Pin Plastic SO  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
74LVT02 D  
74LVT02 DB  
74LVT02 PW  
14-Pin Plastic SSOP  
14-Pin Plastic TSSOP  
74LVT02 DB  
SOT337-1  
74LVT02PW DH  
SOT402-1  
LOGIC SYMBOL  
PIN CONFIGURATION  
2
A0  
1
4
Y0  
A0  
B0  
Y1  
A1  
1
2
3
4
5
14  
V
CC  
Y0  
Y1  
3
B0  
13 Y3  
12 B3  
11 A3  
10 Y2  
5
A1  
B1  
6
8
A2  
B2  
10  
13  
Y2  
Y3  
9
11  
12  
A3  
B3  
B1  
6
7
9
8
B2  
A2  
V
= Pin 14  
CC  
GND = Pin 7  
GND  
SA00335  
SA00337  
LOGIC SYMBOL (IEEE/IEC)  
PIN DESCRIPTION  
1
2
3
PIN  
NUMBER  
SYMBOL  
NAME AND FUNCTION  
1
2, 3, 5, 6, 8,  
9, 11, 12  
An-Bn  
Data inputs  
5
6
4
1, 4, 10, 13  
Yn  
Data outputs  
7
GND  
Ground (0V)  
8
9
10  
14  
V
CC  
Positive supply voltage  
11  
12  
13  
SF00010  
2
1996 Aug 15  
853-1859 17184  
Philips Semiconductors  
Product specification  
3.3V Quad 2-input NOR gate  
74LVT02  
LOGIC DIAGRAM  
FUNCTION TABLE  
INPUTS  
OUTPUT  
2
3
5
6
8
9
11 12  
Dna  
L
Dnb  
Qn  
H
L
L
H
L
A0 B0 A1 A2 B1 B2 A3 B3  
L
H
L
Y0 Y1 Y2 Y3  
H
H
L
NOTES:  
H
L
= High voltage level  
= Low voltage level  
1
4
10 13  
V
= Pin 14  
CC  
GND = Pin 7  
SA00362  
1, 2  
ABSOLUTE MAXIMUM RATINGS  
SYMBOL  
PARAMETER  
CONDITIONS  
RATING  
–0.5 to +4.6  
–50  
UNIT  
V
V
CC  
I
IK  
DC supply voltage  
DC input diode current  
V < 0  
I
mA  
V
3
V
I
DC input voltage  
–0.5 to +7.0  
–50  
I
DC output diode current  
V
O
< 0  
mA  
V
OK  
3
V
OUT  
DC output voltage  
Output in Off or High state  
Output in High state  
Output in Low state  
–0.5 to +7.0  
–32  
I
DC output current  
mA  
OUT  
64  
T
stg  
Storage temperature range  
–65 to 150  
°C  
NOTES:  
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the  
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to  
absolute-maximum-rated conditions for extended periods may affect device reliability.  
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction  
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.  
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.  
RECOMMENDED OPERATING CONDITIONS  
LIMITS  
SYMBOL  
PARAMETER  
UNIT  
MIN  
2.7  
0
MAX  
3.6  
V
CC  
DC supply voltage  
V
V
V
I
Input voltage  
5.5  
V
High-level input voltage  
Low-level Input voltage  
High-level output current  
Low-level output current  
2.0  
V
IH  
V
0.8  
–20  
32  
V
IL  
I
mA  
mA  
ns/V  
°C  
OH  
I
OL  
∆t/∆v  
Input transition rise or fall rate; Outputs enabled  
Operating free-air temperature range  
10  
T
amb  
–40  
+85  
3
1996 Aug 15  
Philips Semiconductors  
Product specification  
3.3V Quad 2-input NOR gate  
74LVT02  
DC ELECTRICAL CHARACTERISTICS  
Over recommended operating conditions  
Voltages are referenced to GND (ground = 0V)  
LIMITS  
SYMBOL  
PARAMETER  
TEST CONDITIONS  
Temp = -40°C to +85°C  
UNIT  
V
1
MIN  
TYP  
MAX  
V
IK  
Input clamp voltage  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 2.7V; I = –18mA  
–1.2  
IK  
= 2.7 to 3.6V; I = –100µA  
V
CC  
–0.2  
OH  
V
OH  
High-level output voltage  
Low-level output voltage  
= 2.7V; I = –6mA  
2.4  
2.0  
V
OH  
= 3.0V; I = –20mA  
OH  
= 2.7V; I = 100µA  
0.2  
0.5  
0.5  
OL  
V
OL  
= 2.7V; I = 24mA  
V
OL  
= 3.0V; I = 32mA  
OL  
V
CC  
V
CC  
V
CC  
= 0 or 3.6V; V = 5.5V  
10  
±1  
I
I
Input leakage current  
Output off current  
µA  
µA  
I
= 3.6V; V = V or GND  
I
CC  
I
= 0V; V or V = 0 to 4.5V  
±100  
OFF  
I
O
V
V
= 3.6V; Outputs High, V = GND or  
I
CC  
I
0.02  
2
CCH  
I
0
CC, O =  
Quiescent supply current  
mA  
V
CC  
= 3.6V; Outputs Low, V = GND or V  
I CC,  
0
I
1
3
CCL  
I
O =  
V
CC  
= 3V to 3.6V; One input at V –0.6V,  
CC  
2
∆I  
Additional supply current per input pin  
0.2  
µA  
CC  
Other inputs at V or GND  
CC  
C
Input capacitance  
V = 3V or 0  
I
pF  
I
NOTES:  
1. All typical values are at V = 3.3V and T  
= 25°C.  
amb  
CC  
2. This is the increase in supply current for each input at the specificed voltage level other than V or GND.  
CC  
AC CHARACTERISTICS  
GND = 0V; t = t = 2.5ns; C = 50pF, R = 500Ω; T = –40°C to +85°C.  
amb  
R
F
L
L
LIMITS  
= 3.3V ± 0.3V  
SYMBOL  
PARAMETER  
WAVEFORM  
V
CC  
V
CC  
= 2.7V  
UNIT  
1
MIN  
TYP  
MAX  
MAX  
t
t
Propagation delay  
An or Bn to Yn  
1.0  
1.0  
2.8  
2.6  
4.4  
3.6  
5.2  
3.4  
PLH  
PHL  
1
ns  
NOTE:  
1. All typical values are at V = 3.3V and T  
= 25°C.  
amb  
CC  
AC WAVEFORMS  
V
M
= 1.5V, V = GND to 2.7V  
IN  
A , B  
n
n
V
V
M
t
M
t
PHL  
PLH  
V
V
M
M
Yn  
SF01395  
Waveform 1. Propagation delay for inverting outputs  
4
1996 Aug 15  
Philips Semiconductors  
Product specification  
3.3V Quad 2-input NOR gate  
74LVT02  
TEST CIRCUIT AND WAVEFORMS  
t
W
AMP (V)  
90%  
V
CC  
90%  
NEGATIVE  
PULSE  
V
V
M
M
10%  
10%  
90%  
V
V
OUT  
IN  
0V  
PULSE  
GENERATOR  
t
t
(t  
(t  
)
t
t
(t  
)
R
D.U.T.  
THL  
F
TLH  
)
(t  
)
F
R
T
TLH  
R
THL  
R
C
L
L
AMP (V)  
90%  
M
POSITIVE  
PULSE  
V
V
M
Test Circuit for Outputs  
10%  
10%  
t
W
0V  
V
M
= 1.5V  
Input Pulse Definition  
INPUT PULSE REQUIREMENTS  
DEFINITIONS  
R = Load resistor; see AC CHARACTERISTICS for value.  
L
FAMILY  
Amplitude  
Rep. Rate  
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance;  
L
74LVT  
2.7V  
≤10MHz  
500ns ≤2.5ns ≤2.5ns  
see AC CHARACTERISTICS for value.  
R = Termination resistance should be equal to Z  
T
of  
OUT  
pulse generators.  
SV00022  
5
1996 Aug 15  
Philips Semiconductors  
Product specification  
3.3V Quad 2-input NOR gate  
74LVT02  
SO14: plastic small outline package; 14 leads; body width 3.9 mm  
SOT108-1  
6
1996 Aug 15  
Philips Semiconductors  
Product specification  
3.3V Quad 2-input NOR gate  
74LVT02  
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm  
SOT337-1  
7
1996 Aug 15  
Philips Semiconductors  
Product specification  
3.3V Quad 2-input NOR gate  
74LVT02  
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm  
SOT402-1  
8
1996 Aug 15  
Philips Semiconductors  
Product specification  
3.3V Quad 2-input NOR gate  
74LVT02  
NOTES  
9
1996 Aug 15  
Philips Semiconductors  
Product specification  
3.3V Quad 2-input NOR gate  
74LVT02  
DEFINITIONS  
Data Sheet Identification  
Product Status  
Definition  
This data sheet contains the design target or goal specifications for product development. Specifications  
may change in any manner without notice.  
Objective Specification  
Formative or in Design  
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips  
Semiconductors reserves the right to make changes at any time without notice in order to improve design  
and supply the best possible product.  
Preliminary Specification  
Product Specification  
Preproduction Product  
Full Production  
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes  
at any time without notice, in order to improve design and supply the best possible product.  
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,  
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips  
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,  
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask  
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes  
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting  
or modification.  
LIFE SUPPORT APPLICATIONS  
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,  
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected  
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips  
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully  
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.  
Philips Semiconductors  
811 East Arques Avenue  
P.O. Box 3409  
Sunnyvale, California 94088–3409  
Telephone 800-234-7381  
Philips Semiconductors and Philips Electronics North America Corporation  
register eligible circuits under the Semiconductor Chip Protection Act.  
Copyright Philips Electronics North America Corporation 1996  
All rights reserved. Printed in U.S.A.  
(print code)  
Date of release: July 1994  
9397-750-04846  
Document order number:  

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