74LVT16244BDL,118 [NXP]
74LVT16244B - 3.3 V 16-bit buffer/driver; 3-state@en-us SSOP 48-Pin;
| 型号： | 74LVT16244BDL,118 |
| 厂家： | 
NXP |
| 描述： | 74LVT16244B - 3.3 V 16-bit buffer/driver; 3-state@en-us SSOP 48-Pin |
| 文件： | 总18页 (文件大小：253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
Rev. 11 — 1 March 2012
Product data sheet
1. General description
The 74LVT16244B; 74LVTH16244B is a high-performance BiCMOS product designed for
CC operation at 3.3 V.
V
This device is a 16-bit buffer and line driver featuring non-inverting 3-state bus outputs.
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer.
2. Features and benefits
16-bit bus interface
3-state buffers
Output capability: +64 mA and 32 mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Power-up 3-state
Live insertion and extraction permitted
No bus current loading when output is tied to 5 V bus
Latch-up protection
JESD78B Class II exceeds 500 mA
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVT16244BDL
74LVTH16244BDL
74LVT16244BDGG
74LVTH16244BDGG
74LVT16244BEV
40 C to +85 C
SSOP48
plastic shrink small outline package; 48 leads; SOT370-1
body width 7.5 mm
40 C to +85 C
TSSOP48
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
SOT362-1
40 C to +85 C
40 C to +125 C
VFBGA56
HXQFN60
plastic very thin fine-pitch ball grid array
SOT702-1
package; 56 balls; body 4.5 7 0.65 mm
74LVT16244BBX
74LVTH16244BBX
plastic compatible thermal enhanced extremely SOT1134-2
thin quad flat package; no leads; 60 terminals;
body 4 6 0.5 mm
74LVT16244B; 74LVTH16244B
NXP Semiconductors
3.3 V 16-bit buffer/driver; 3-state
4. Functional diagram
1
1A0
1A1
1A2
1A3
1OE
2A0
2A1
2A2
2A3
2OE
1Y0
1Y1
1Y2
1Y3
3A0
3A1
3A2
3A3
3OE
4A0
4A1
4A2
4A3
4OE
3Y0
3Y1
3Y2
3Y3
1OE
2OE
3OE
4OE
EN1
EN2
EN3
EN4
47
46
44
43
1
2
3
5
6
36
35
33
32
25
30
29
27
26
24
13
14
16
17
48
25
24
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2
3
1A0
1A1
1A2
1A3
2A0
2A1
2A2
2A3
3A0
3A1
3A2
3A3
4A0
4A1
4A2
4A3
1
1
1
1
1
2
3
4
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
3Y0
3Y1
3Y2
3Y3
4Y0
4Y1
4Y2
4Y3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
2Y0
2Y1
2Y2
2Y3
4Y0
4Y1
4Y2
4Y3
41
40
38
37
48
8
9
19
20
22
23
11
12
001aae506
001aae231
Pin numbers are shown for SSOP48 and TSSOP48
packages only.
Pin numbers are shown for SSOP48 and TSSOP48
packages only.
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74LVT_LVTH16244B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 11 — 1 March 2012
2 of 18
74LVT16244B; 74LVTH16244B
NXP Semiconductors
3.3 V 16-bit buffer/driver; 3-state
5. Pinning information
5.1 Pinning
74LVT16244B
74LVTH16244B
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Y0
1Y1
GND
1Y2
1Y3
2OE
1A0
1A1
GND
1A2
1A3
3
4
5
6
7
V
V
CC
CC
8
2Y0
2Y1
GND
2Y2
2Y3
3Y0
3Y1
GND
3Y2
3Y3
2A0
2A1
GND
2A2
2A3
3A0
3A1
GND
3A2
3A3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
74LVT16244B
74LVTH16244B
ball A1
index area
1
2 3 4 5 6
A
B
C
D
E
F
G
H
J
V
V
CC
CC
4Y0
4Y1
4A0
4A1
GND
4A2
4A3
3OE
GND
4Y2
4Y3
K
4OE
001aaj057
Transparent top view
001aae507
Fig 3. Pin configuration SOT370-1 (SSOP48) and
SOT362-1 (TSSOP48)
Fig 4. Pin configuration SOT702-1 (VFBGA56)
74LVT_LVTH16244B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 11 — 1 March 2012
3 of 18
74LVT16244B; 74LVTH16244B
NXP Semiconductors
3.3 V 16-bit buffer/driver; 3-state
terminal 1
index area
D1
A32
D5
A31
A30
A29
A28
A27
D8
D4
B20
B19
B18
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
B1
B2
B3
B4
B5
B6
B7
B17
B16
B15
B14
B13
B12
B11
74LVT16244B
74LVTH16244B
(1)
GND
D6
B8
B9
B10
D7
D2
A11
A12
A13
A14
A15
A16
D3
001aaj056
Transparent top view
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.
Fig 5. Pin configuration SOT1134-2 (HXQFN60)
74LVT_LVTH16244B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 11 — 1 March 2012
4 of 18
74LVT16244B; 74LVTH16244B
NXP Semiconductors
3.3 V 16-bit buffer/driver; 3-state
5.2 Pin description
Table 2.
Symbol
Pin description
Pin
Description
SOT1134-2
SOT370-1 and
SOT362-1
SOT702-1
1OE, 2OE, 1, 48, 25, 24
3OE, 4OE
A1, A6, K6, K1
A30, A29, A14, A13
output enable input (active LOW)
1Y0 to 1Y3 2, 3, 5, 6
B2, B1, C2, C1
D2, D1, E2, E1
F1, F2, G1, G2
H1, H2, J1, J2
B20, A31, D5, D1
A2, B2, B3, A5
A6, B5, B6, A9
D2, D6, A12, B8
data output
data output
data output
data output
ground (0 V)
2Y0 to 2Y3 8, 9, 11, 12
3Y0 to 3Y3 13, 14, 16, 17
4Y0 to 4Y3 19, 20, 22, 23
GND
4, 10, 15, 21, 28,
34, 39, 45
B3, B4, D3, D4, G3, G4, A32, A3, A8, A11, A16,
J3, J4
A19, A24, A27
VCC
7, 18, 31, 42
C3, C4, H3, H4
B5, B6, C5, C6
D5, D6, E5, E6
F6, F5, G6, G5
H6, H5, J6, J5
A1, A10, A17, A26
B18, A28, D8, D4
A25, B16, B15, A22
A21, B13, B12, A18
D3, D7, A15, B10
supply voltage
data input
1A0 to 1A3 47, 46, 44, 43
2A0 to 2A3 41, 40, 38, 37
3A0 to 3A3 36, 35, 33, 32
4A0 to 4A3 30, 29, 27, 26
data input
data input
data input
n.c.
-
A2, A3, A4, A5, K2, K3, A4, A7, A20, A23, B1,
not connected
K4, K5
B4, B7, B9, B11, B14,
B17, B19
6. Functional description
Table 3.
Function table[1]
Control
Input
nAn
L
Output
nOE
L
nYn
L
L
H
H
H
X
Z
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
0.5
0.5
0.5
Max
+4.6
+7.0
+7.0
Unit
V
supply voltage
input voltage
output voltage
[1]
[1]
V
VO
output in OFF-state or
HIGH-state
V
IIK
input clamping current
output clamping current
VI < 0 V
50
50
-
-
mA
mA
IOK
VO < 0 V
74LVT_LVTH16244B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 11 — 1 March 2012
5 of 18
74LVT16244B; 74LVTH16244B
NXP Semiconductors
3.3 V 16-bit buffer/driver; 3-state
Table 4.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
-
Max
128
-
Unit
mA
mA
C
IO
output current
output in LOW-state
output in HIGH-state
64
65
-
Tstg
Tj
storage temperature
junction temperature
total power dissipation
+150
150
[2]
C
Ptot
Tamb = 40 C to +85 C;
(T)SSOP48 package
VFBGA56 package
HXQFN60 package
[3]
[4]
[4]
-
-
-
500
mW
mW
mW
1000
1000
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
[3] Above 60 C the value of Ptot derates linearly with 5.5 mW/K.
[4] Above 70 C the value of Ptot derates linearly with 1.8 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
VCC
VI
Recommended operating conditions
Parameter
Conditions
Min
2.7
0
Typ
Max
3.6
5.5
-
Unit
V
supply voltage
-
-
-
-
-
-
-
input voltage
V
VIH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
2.0
-
V
VIL
0.8
-
V
IOH
32
-
mA
mA
mA
IOL
none
32
64
current duty cycle 50 %;
fi 1 kHz
-
Tamb
ambient temperature
in free-air
40
-
-
+85
10
C
t/V
input transition rise and fall rate outputs enabled
-
ns/V
74LVT_LVTH16244B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 11 — 1 March 2012
6 of 18
74LVT16244B; 74LVTH16244B
NXP Semiconductors
3.3 V 16-bit buffer/driver; 3-state
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 40 C to +85 C[1]
VIK
input clamping voltage
VCC = 2.7 V; IIK = 18 mA
1.2
0.85
-
-
-
-
V
V
V
V
VOH
HIGH-level output voltage IOH = 100 A; VCC = 2.7 V to 3.6 V
VCC 0.2 VCC
IOH = 8 mA; VCC = 2.7 V
2.4
2.0
2.5
2.3
IOH = 32 mA; VCC = 3.0 V
VOL
LOW-level output voltage VCC = 2.7 V
IOL = 100 A
-
-
0.07
0.3
0.2
0.5
V
V
IOL = 24 mA
VCC = 3.0 V
IOL = 16 mA
-
-
-
-
-
0.25
0.3
0.4
0.1
0.1
0.4
V
IOL = 32 mA
0.5
V
IOL = 64 mA
0.55
10
V
II
input leakage current
all input pins; VCC = 0 V or 3.6 V; VI = 5.5 V
control pins; VCC = 3.6 V; VI = VCC or GND
data pins; VCC = 3.6 V
A
A
1.0
[2]
[3]
VI = VCC
-
0.1
0.1
0.1
135
135
-
1
A
A
A
A
A
A
VI = 0 V
5
-
-
IOFF
IBHL
IBHH
IBHLO
power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V
100
bus hold LOW current
bus hold HIGH current
VCC = 3 V; VI = 0.8 V
75
-
-
VCC = 3 V; VI = 2.0 V
75
bus hold LOW
nAn input; VCC = 0 V to 3.6 V; VI = 3.6 V
500
-
overdrive current
IBHHO
ILO
bus hold HIGH
overdrive current
nAn input; VCC = 0 V to 3.6 V; VI = 3.6 V
-
-
-
-
500
125
A
A
A
output leakage current
output in HIGH-state when VO > VCC; VO =
5.5 V; VCC = 3.0 V
50
1
[4]
IO(pu/pd) power-up/power-down
output current
VCC 1.2 V; VO = 0.5 V to VCC; VI = GND or
VCC; nOE = don’t care
100
IOZ
OFF-state output current VCC = 3.6 V; VI = VIH or VIL
output HIGH: VO = 3.0 V
output LOW: VO = 0.5 V
VCC = 3.6 V; VI = GND or VCC; IO = 0 A
output HIGH
-
0.5
5
-
A
A
5
+0.5
ICC
supply current
-
-
-
-
0.07
4.0
0.12
6.0
mA
mA
mA
mA
output LOW
[5]
[6]
outputs disabled
0.07
0.1
0.12
0.2
ICC
additional supply current per input pin; VCC = 3.0 V to 3.6 V; one input
at VCC 0.6 V other inputs at VCC or GND
74LVT_LVTH16244B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 11 — 1 March 2012
7 of 18
74LVT16244B; 74LVTH16244B
NXP Semiconductors
3.3 V 16-bit buffer/driver; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
3
Max
Unit
pF
CI
input capacitance
output capacitance
VI = 0 V or 3.0 V
-
-
-
-
CO
outputs disabled; VO = 0 V or 3.0 V
9
pF
[1] Typical values are measured at VCC = 3.3 V and at Tamb = 25 C.
[2] Unused pins at VCC or GND.
[3] This is the bus hold overdrive current required to force the input to the opposite logic state.
[4] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V 0.3 V
a transition time of 100 s is permitted. This parameter is valid for Tamb = 25 C only.
[5]
ICC is measured with outputs pulled to VCC or GND.
[6] This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 40 C to +85 C[1]
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
LOW to HIGH
propagation delay
nAn to nYn; see Figure 6
VCC = 2.7 V
-
-
4.0
3.2
ns
ns
VCC = 3.0 V to 3.6 V
nAn to nYn; see Figure 6
VCC = 2.7 V
0.5
1.8
HIGH to LOW
propagation delay
-
-
4.0
3.2
ns
ns
VCC = 3.0 V to 3.6 V
nOE to nYn; see Figure 7
VCC = 2.7 V
0.5
1.7
OFF-state to HIGH
propagation delay
-
-
5.0
4.0
ns
ns
VCC = 3.0 V to 3.6 V
nOE to nYn; see Figure 7
VCC = 2.7 V
1.0
2.3
OFF-state to LOW
propagation delay
-
-
5.3
4.0
ns
ns
VCC = 3.0 V to 3.6 V
nOE to nYn; see Figure 7
VCC = 2.7 V
1.0
2.1
HIGH to OFF-state
propagation delay
-
-
5.0
4.5
ns
ns
VCC = 3.0 V to 3.6 V
nOE to nYn; see Figure 7
VCC = 2.7 V
1.0
3.2
LOW to OFF-state
propagation delay
-
-
4.4
4.0
ns
ns
VCC = 3.0 V to 3.6 V
1.0
2.9
[1] Typical values are measured at VCC = 3.3 V and Tamb = 25 C.
74LVT_LVTH16244B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 11 — 1 March 2012
8 of 18
74LVT16244B; 74LVTH16244B
NXP Semiconductors
3.3 V 16-bit buffer/driver; 3-state
11. Waveforms
V
I
nAn input
GND
V
V
M
M
t
t
PLH
PHL
V
OH
V
V
M
nYn output
M
V
OL
mna171
Measurements points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Propagation delay input (nAn) to output (nYn)
V
I
nOE input
nYn output
nYn output
V
M
t
GND
3.0 V
t
PZL
PLZ
V
V
M
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
0 V
001aae464
Measurements points are given in Table 8.
OL and VOH are typical voltage output levels that occur with the output load.
V
Fig 7. 3-state output enable and disable times
Table 8.
Input
VM
Measurement points
Output
VM
VX
VY
VOH 0.3 V
1.5 V
1.5 V
VOL + 0.3 V
74LVT_LVTH16244B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 11 — 1 March 2012
9 of 18
74LVT16244B; 74LVTH16244B
NXP Semiconductors
3.3 V 16-bit buffer/driver; 3-state
t
W
V
I
90 %
negative
pulse
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
V
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
DUT
R
T
C
L
R
L
001aae235
Test data is given in Table 9.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8. Test circuit for measuring switching times
Table 9.
Input
VI
Test data
Load
CL
VEXT
fi
tW
tr, tf
RL
tPHZ, tPZH
GND
tPLZ, tPZL
tPLH, tPHL
2.7 V
10 MHz
500 ns
2.5 ns
50 pF
500
6 V
open
74LVT_LVTH16244B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 11 — 1 March 2012
10 of 18
74LVT16244B; 74LVTH16244B
NXP Semiconductors
3.3 V 16-bit buffer/driver; 3-state
12. Package outline
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
D
E
A
X
c
y
H
v
M
A
E
Z
25
48
Q
A
2
A
A
(A )
3
1
θ
pin 1 index
L
p
L
24
1
detail X
w
M
b
p
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.
8o
0o
0.4
0.2
2.35
2.20
0.3
0.2
0.22 16.00
0.13 15.75
7.6
7.4
10.4
10.1
1.0
0.6
1.2
1.0
0.85
0.40
mm
2.8
0.25
0.635
1.4
0.25
0.18
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT370-1
MO-118
Fig 9. Package outline SOT370-1 (SSOP48)
74LVT_LVTH16244B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 11 — 1 March 2012
11 of 18
74LVT16244B; 74LVTH16244B
NXP Semiconductors
3.3 V 16-bit buffer/driver; 3-state
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
H
v
M
A
y
E
Z
48
25
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
24
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.8
0.4
mm
1.2
0.5
1
0.25
0.25
0.08
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT362-1
MO-153
Fig 10. Package outline SOT362-1 (TSSOP48)
74LVT_LVTH16244B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 11 — 1 March 2012
12 of 18
74LVT16244B; 74LVTH16244B
NXP Semiconductors
3.3 V 16-bit buffer/driver; 3-state
VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm
SOT702-1
B
A
D
ball A1
index area
A
2
A
E
A
1
detail X
e
1
C
∅ v M
∅ w M
C
C
A B
b
e
y
y
C
1
1/2 e
K
J
H
G
F
e
e
2
E
D
C
B
A
1/2 e
X
ball A1
index area
1
2
3
4
5
6
DIMENSIONS (mm are the original dimensions)
A
A
A
b
e
y
UNIT
D
E
e
e
v
w
y
1
1
2
0
2.5
5 mm
1
2
max.
0.3
0.2
0.7
0.6
0.45
0.35
4.6
4.4
7.1
6.9
scale
mm
1
3.25 5.85
0.08
0.1
0.65
0.15 0.08
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
02-08-08
03-07-01
SOT702-1
MO-225
Fig 11. Package outline SOT702-1 (VFBGA56)
74LVT_LVTH16244B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 11 — 1 March 2012
13 of 18
74LVT16244B; 74LVTH16244B
NXP Semiconductors
3.3 V 16-bit buffer/driver; 3-state
HXQFN60: plastic compatible thermal enhanced extremely thin quad flat package; no leads;
60 terminals; body 4 x 6 x 0.5 mm
SOT1134-2
D
B
A
terminal 1
index area
A
A
2
E
A
1
detail X
e
2
b
v
C
C
A
B
w
e
1
eR
C
C
A
B
e
v
C
eT
1/2 e
B8 B10
w
y
y
C
1
L
1
D2
A11
A16
D3
D7
D6
L
A17
B11
A10
B7
e
eR
eT
E
h
e
3
e
4
1/2 e
B1
A1
B17
A26
terminal 1
index area
D5
D1
B20 B18
D8
D4
eT
eR
A32
A27
X
D
h
K
eT
eR
0
5 mm
Dimensions
Unit
A
A
1
A
2
b
D
D
h
E
E
e
e
e
2
e
3
e
eR eT
K
L
L
v
w
y
y
1
h
1
4
1
max 0.50 0.08 0.42 0.28 4.1 1.95 6.1 3.95
0.25 0.28 0.195
mm nom
min
0.05 0.40 0.23 4.0 1.85 6.0 3.85 0.5 1.0 2.5 3.0 4.5 0.5 0.49 0.20 0.23 0.145 0.1 0.05 0.08 0.1
0.02 0.38 0.18 3.9 1.75 5.9 3.75
0.15 0.18 0.095
sot1134-2_po
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
- - -
JEITA
- - -
SOT1134-2
11-08-15
Fig 12. Package outline SOT1134-2 (HXQFN60)
74LVT_LVTH16244B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 11 — 1 March 2012
14 of 18
74LVT16244B; 74LVTH16244B
NXP Semiconductors
3.3 V 16-bit buffer/driver; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
BiCMOS
DUT
Description
Bipolar Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVT_LVTH16244B v.11 20120301
Product data sheet
-
74LVT_LVTH16244B v.10
Modifications:
• For type number 74LVT16244BBX and 74LVTH16244BBX the sot code has changed to
SOT1134-2.
74LVT_LVTH16244B v.10 20111122
Product data sheet
-
74LVT_LVTH16244B v.9
Modifications:
• Legal pages updated.
74LVT_LVTH16244B v.9 20110620
74LVT_LVTH16244B v.8 20100322
74LVT_LVTH16244B v.7 20090326
74LVT_LVTH16244B v.6 20081113
74LVT_LVTH16244B v.5 20060321
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product specification
Product specification
Product specification
-
-
-
-
-
-
-
-
74LVT_LVTH16244B v.8
74LVT_LVTH16244B v.7
74LVT_LVTH16244B v.6
74LVT_LVTH16244B v.5
74LVT16244B v.4
74LVT16244B v.3
74LVT16244B v.2
-
74LVT16244B v.4
74LVT16244B v.3
74LVT16244B v.2
20021031
19981007
19980219
74LVT_LVTH16244B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 11 — 1 March 2012
15 of 18
74LVT16244B; 74LVTH16244B
NXP Semiconductors
3.3 V 16-bit buffer/driver; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
15.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74LVT_LVTH16244B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 11 — 1 March 2012
16 of 18
74LVT16244B; 74LVTH16244B
NXP Semiconductors
3.3 V 16-bit buffer/driver; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVT_LVTH16244B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 11 — 1 March 2012
17 of 18
74LVT16244B; 74LVTH16244B
NXP Semiconductors
3.3 V 16-bit buffer/driver; 3-state
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
6
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 1 March 2012
Document identifier: 74LVT_LVTH16244B
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