74LVT273BQ,115 [NXP]
74LVT273 - 3.3 V octal D-type flip-flop QFN 20-Pin;
| 型号： | 74LVT273BQ,115 |
| 厂家： | 
NXP |
| 描述： | 74LVT273 - 3.3 V octal D-type flip-flop QFN 20-Pin 信息通信管理 逻辑集成电路 触发器 |
| 文件： | 总17页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVT273
3.3 V octal D-type flip-flop
Rev. 03 — 10 September 2008
Product data sheet
1. General description
The 74LVT273 is a high-performance BiCMOS product designed for VCC operation at
3.3 V.
This device has eight edge-triggered D-type flip-flops with individual D inputs and Q
outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time before the
LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independent of the clock or data inputs by a LOW voltage
level on the MR input. The device is useful for applications where only the true output is
required and the CP and MR are common elements.
2. Features
I Eight edge-triggered D-type flip-flops
I Buffered common clock and asynchronous master reset
I Input and output interface capability to systems at 5 V supply
I TTL input and output switching levels
I Input and output interface capability to systems at 5 V supply
I Output capability: +64 mA/−32 mA
I Latch-up protection
N JESD78 Class II exceeds 500 mA
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Bus-hold data inputs eliminate the need for external pull-up resistors for unused inputs
I Live insertion/extraction permitted
I Power-up reset
I No bus current loading when output is tied to 5 V bus
74LVT273
NXP Semiconductors
3.3 V octal D-type flip-flop
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVT273D
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74LVT273DB
74LVT273PW
74LVT273BQ
SSOP20
TSSOP20
plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
SOT360-1
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1
thin quad flat package; no leads; 20 terminals;
body 2.5 × 4.5 × 0.85 mm
4. Functional diagram
11
CP
C1
1
R
MR
11
3
2
1D
CP
D0
Q0
3
2
5
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
4
7
8
5
6
9
D1
D2
D3
D4
D5
D6
D7
Q1
Q2
Q3
Q4
Q5
Q6
Q7
4
7
6
8
9
13
14
17
18
12
15
16
19
13
14
17
18
12
15
16
19
MR
1
mna763
mna764
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74LVT273_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 10 September 2008
2 of 17
74LVT273
NXP Semiconductors
3.3 V octal D-type flip-flop
D0
D1
D2
D3
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
FF1
FF2
FF3
FF4
R
R
R
D
R
D
D
D
CP
MR
Q0
Q1
Q2
Q3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
CP
FF5
CP
FF6
CP
FF7
CP
FF8
R
R
R
D
R
D
D
D
Q4
Q5
Q6
Q7
001aae056
Fig 3. Logic diagram
74LVT273_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 10 September 2008
3 of 17
74LVT273
NXP Semiconductors
3.3 V octal D-type flip-flop
5. Pinning information
5.1 Pinning
74LVT273
terminal 1
index area
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
Q0
Q7
D7
D6
Q6
Q5
D5
D4
Q4
74LVT273
D0
D1
Q1
Q2
D2
D3
Q3
1
2
20
19
18
17
16
15
14
13
12
11
MR
Q0
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
3
D0
4
D1
5
Q1
6
Q2
(1)
GND
7
D2
8
D3
9
Q3
001aai738
10
GND
Transparent top view
001aai737
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 4. Pin configuration for SO20 and (T)SSOP20
Fig 5. Pin configuration for DHVQFN20
5.2 Pin description
Table 2.
Symbol
MR
Pin description
Pin
Description
1
master reset input (active LOW)
data output
Q0 to Q7
D0 to D7
GND
2, 5, 6, 9, 12, 15, 16, 19
3, 4, 7, 8, 13, 14, 17, 18
data input
10
11
20
ground (0 V)
CP
clock pulse input (active on rising edge)
positive supply voltage
VCC
74LVT273_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 10 September 2008
4 of 17
74LVT273
NXP Semiconductors
3.3 V octal D-type flip-flop
6. Functional description
Table 3.
Function selection
Inputs
Outputs
Operating mode
MR
L
CP
X
↑
Dn
X
h
Qn
L
Reset (clear)
Load 1
H
H
H
↑
l
L
Load 0
H
L
X
Q0
Retain state
[1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the prior to the LOW-to-HIGH clock transition;
L = LOW voltage level; l = LOW voltage level one set-up time prior to the prior to the LOW-to-HIGH clock transition;
X = Don’t care; ↑ = LOW-to-HIGH clock transition; Q0 = output as it was.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
−0.5
−0.5
−0.5
−50
−50
-
Max
+4.6
+7.0
+7.0
-
Unit
V
supply voltage
[1]
[1]
input voltage
V
VO
output voltage
Output in OFF or HIGH state
VI < 0 V
V
IIK
input clamping current
output clamping current
output current
mA
mA
mA
mA
°C
IOK
VO < 0 V
-
IO
output in LOW state
output in HIGH state
128
-
−64
−65
-
Tstg
Tj
storage temperature
junction temperature
total power dissipation
+150
150
500
[2]
[3]
°C
Ptot
Tamb = −40 °C to +85 °C
mW
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
[3] For SO20 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol Parameter
Conditions
Min
2.7
0
Typ
Max
3.6
5.5
-
Unit
V
VCC
VI
supply voltage
-
-
-
input voltage
V
IOH
HIGH-level output current
−32
mA
74LVT273_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 10 September 2008
5 of 17
74LVT273
NXP Semiconductors
3.3 V octal D-type flip-flop
Table 5.
Recommended operating conditions …continued
Symbol Parameter
Conditions
Min
Typ
Max
64
Unit
mA
°C
IOL
LOW-level output current
-
-
-
-
Tamb
∆t/∆V
ambient temperature
in free air
−40
+85
10
input transition rise and fall rate;
output enabled
-
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
Unit
Min
Typ[1]
Max
VIK
VIH
VIL
input clamping voltage
VCC = 2.7V; IIK = –18 mA
−1.2
2.0
-
−0.9
-
-
V
V
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
-
-
0.8
-
VOH
VCC = 2.7 V to 3.6V; IOH = −100 µA
VCC = 2.7 V; IOH = −8 mA
V
CC − 0.2 VCC − 0.1
V
V
V
V
V
V
V
V
V
2.4
2.0
2.5
2.2
-
VCC = 3.0 V; IOH = −32 mA
VCC = 2.7 V; IOL = 100 µA
VCC = 2.7 V; IOL = 24 mA
-
VOL
LOW-level output voltage
0.1
0.2
0.5
0.4
0.5
0.55
0.55
-
-
-
-
-
0.3
VCC = 3.0 V; IOL = 16 mA
0.25
0.3
VCC = 3.0 V; IOL = 32 mA
VCC = 3.0 V; IOL = 64 mA
0.4
[2]
VOL(pu) power-up LOW-level
output voltage
VCC = 3.6 V; IO = 1 mA; VI = GND or VCC
0.13
II
input leakage current
input pins
VCC = 0 V or 3.6 V; VI = 5.5 V
control pins
-
-
1
10
µA
µA
VCC = 3.6 V; VI = VCC or GND
data pins
±0.1
±1
[3]
VCC = 3.6 V; VI = VCC
VCC = 3.6 V; VI = 0 V
-
−5
-
0.1
−1
1
µA
µA
−
IOFF
ILO
power-off leakage current
output leakage current
bus hold LOW current
bus hold HIGH current
VCC = 0 V; VI or VO = 0 V to 4.5 V
VCC = 3.0 V; VO = 5.5 V; output HIGH
VCC = 3.0 V; VI = 0.8 V
VCC = 3.0 V; VI = 2.0 V
VCC = 3.6 V; VI = 0 V to 3.6 V
1
±100 µA
125 µA
-
60
[4]
IBHL
IBHH
IBHHO
75
-
150
−150
-
-
µA
−75 µA
500 µA
bus hold HIGH overdrive
current
-
IBHLO
bus hold LOW overdrive
current
VCC = 3.6 V; VI = 0 V to 3.6 V
−500
-
-
µA
74LVT273_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 10 September 2008
6 of 17
74LVT273
NXP Semiconductors
3.3 V octal D-type flip-flop
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
Unit
Min
Typ[1]
Max
ICC
supply current
VCC = 3.6 V; VI = VCC or GND; IO = 0 A
outputs HIGH
-
-
-
0.13
3
0.19 mA
outputs LOW
12
mA
mA
[5]
∆ICC
additional supply current
input capacitance
per input pin; VCC = 3.0 V to 3.6 V;
one input = VCC − 0.6 V
other inputs at VCC or GND
0.1
0.2
CI
VI = 0 V or 3.0 V
-
4
-
pF
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.
[2] For valid test results data must not be loaded into the flip-flops (or latches) after applying the power.
[3] Unused pins at VCC or GND.
[4] This is the bus hold overdrive current required to force the input to the opposite logic state.
[5] Increase in supply current for each input at the specified voltage level other than VCC or GND
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.
Symbol Parameter
Conditions
−40 °C to +85 °C
Unit
Min
Typ[1]
Max
tPLH
LOW to HIGH propagation delay
CP to Qn; Figure 6
VCC = 2.7 V
-
-
6.3
5.5
ns
ns
VCC = 3.3 V ± 0.3 V
CP to Qn; Figure 6
VCC = 2.7 V
1.7
3.5
tPHL
HIGH to LOW propagation delay
-
-
5.9
5.5
ns
ns
VCC = 3.3 V ± 0.3 V
MR to Qn; see Figure 7
VCC = 2.7 V
1.9
3.5
-
-
6.2
6.2
ns
ns
VCC = 3.3 V ± 0.3 V
Dn to CP HIGH; see Figure 7
VCC = 2.7 V
1.3
3.2
[2]
tsu
set-up time
2.7
2.3
-
-
-
ns
ns
VCC = 3.3 V ± 0.3 V
Dn to CP LOW; see Figure 7
VCC = 2.7 V
1.0
2.7
2.3
-
-
-
ns
ns
VCC = 3.3 V ± 0.3 V
Dn to CP HIGH; see Figure 8
VCC = 2.7 V
1.0
[3]
th
hold time
0
0
-
-
-
ns
ns
VCC = 3.3 V ± 0.3 V
Dn to CP LOW; see Figure 8
VCC = 2.7 V
−0.6
0
0
-
-
-
ns
ns
VCC = 3.3 V ± 0.3 V
−0.6
74LVT273_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 10 September 2008
7 of 17
74LVT273
NXP Semiconductors
3.3 V octal D-type flip-flop
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.
Symbol Parameter
Conditions
−40 °C to +85 °C
Unit
Min
Typ[1]
Max
[4]
tW
pulse width
CP input HIGH or LOW; see Figure 6
VCC = 2.7 V
3.3
3.3
-
-
-
ns
ns
VCC = 3.3 V ± 0.3 V
MR input LOW; see Figure 7
VCC = 2.7 V
1.5
3.3
3.3
-
-
-
ns
ns
VCC = 3.3 V ± 0.3 V
see Figure 7
1.5
trec
recovery time
VCC = 2.7 V
3.2
2.7
-
1.0
-
-
-
-
ns
VCC = 3.3 V ± 0.3 V
CP input; see Figure 7
ns
fmax
maximum frequency
150
MHz
[1] Typical values are measured at Tamb = 25 °C and VCC = 3.3 V
[2] tsu is the same as tsu(L) and tsu(H)
[3] th is the same as th(L) and th(H)
[4] tW is the same as tWL and tWH
11. Waveforms
1/f
max
V
I
CP input
V
M
GND
t
t
WL
WH
t
t
PLH
PHL
V
OH
V
Qn output
M
V
OL
001aai739
see Table 8 for measurement points.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. CP Input to Qn output propagation delays and clock pulse width and maximum frequency
Table 8.
Input
VI
Measurement points
Output
VM
VM
2.7 V
1.5 V
1.5 V
74LVT273_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 10 September 2008
8 of 17
74LVT273
NXP Semiconductors
3.3 V octal D-type flip-flop
V
I
V
MR input
M
GND
t
t
rec
WL
V
I
CP input
V
M
GND
t
PHL
V
OH
V
Qn output
M
V
OL
001aai740
see Table 8 for measurement points.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. MR pulse width, MR to CP recovery time and MR to Qn delay
V
I
V
M
CP input
GND
t
t
su(L)
su(H)
t
t
h(L)
h(H)
V
I
V
Dn input
M
GND
V
OH
V
Qn output
M
V
OL
001aai741
see Table 8 for measurement points.
VOL and VOH are typical output voltage levels that occur with the output load.
The shaded areas indicate when the input is permitted to change for predicable output performance.
Fig 8. Data set-up and hold times
74LVT273_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 10 September 2008
9 of 17
74LVT273
NXP Semiconductors
3.3 V octal D-type flip-flop
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
CC
V
V
O
I
PULSE
GENERATOR
DUT
R
T
C
L
R
L
001aaf615
Test data is given in given in Table 9.
Definitions for test circuit:
RL = Load resistance;
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 9. Load circuitry for switching times
Table 9.
Input
VI
Test data
Load
RL
Repetition rate
≤ 10 MHz
tW
tr, tf
CL
2.7 V
500 ns
≤ 2.5 ns
500 Ω
50 pF
74LVT273_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 10 September 2008
10 of 17
74LVT273
NXP Semiconductors
3.3 V octal D-type flip-flop
12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.01
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 10. Package outline SOT163-1 (SO20)
74LVT273_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 10 September 2008
11 of 17
74LVT273
NXP Semiconductors
3.3 V octal D-type flip-flop
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
D
E
A
X
c
H
v
M
A
y
E
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.9
0.5
mm
2
0.65
0.25
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT339-1
MO-150
Fig 11. Package outline SOT339-1 (SSOP20)
74LVT273_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 10 September 2008
12 of 17
74LVT273
NXP Semiconductors
3.3 V octal D-type flip-flop
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig 12. Package outline SOT360-1 (TSSOP20)
74LVT273_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 10 September 2008
13 of 17
74LVT273
NXP Semiconductors
3.3 V octal D-type flip-flop
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
SOT764-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
9
L
1
10
E
h
e
20
11
19
12
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
4.6
4.4
3.15
2.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
3.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT764-1
- - -
MO-241
- - -
Fig 13. Package outline SOT764-1 (DHVQFN20)
74LVT273_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 10 September 2008
14 of 17
74LVT273
NXP Semiconductors
3.3 V octal D-type flip-flop
13. Abbreviations
Table 10. Abbreviations
Acronym
BiCMOS
CDM
Description
Integrated Bipolar junction transistors and CMOS
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
74LVT273_3
Modifications:
Release date
20080910
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LVT273_2
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Title changed to 3.3 V octal D-type flip-flop
• Section 3 “Ordering information” and Section 12 “Package outline” DHVQFN20 package
added.
• Table 4 “Limiting values” Tj and Ptot values added.
74LVT273_2
19980219
Product specification
-
-
74LVT273_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 10 September 2008
15 of 17
74LVT273
NXP Semiconductors
3.3 V octal D-type flip-flop
15. Legal information
16. Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
16.1 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.2 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
16.3 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVT273_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 10 September 2008
16 of 17
74LVT273
NXP Semiconductors
3.3 V octal D-type flip-flop
18. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 10 September 2008
Document identifier: 74LVT273_3
相关型号：
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