74LVT373 [NXP]
3.3 Volt ABT octal transparent latch 3-State; 3.3伏ABT八路透明锁存器三态
| 型号： | 74LVT373 |
| 厂家： | 
NXP |
| 描述： | 3.3 Volt ABT octal transparent latch 3-State |
| 文件： | 总6页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors Low Voltage Products
Objective specification
3.3 Volt ABT octal transparent latch (3–State)
74LVT373
independently by Enable (E) and Output
Enable (OE) control gates.
FEATURES
• Latch–up protection exceeds 500mA per
JEDEC JC40.2 Std 17
• Designed for use in the 3.3V
The data on the D inputs are transferred to
the latch outputs when the Latch Enable (E)
input is High. The latch remains transparent
to the data inputs while E is High, and stores
the data that is present one setup time before
the High-to-Low enable transition.
high–performance market
• ESD protection exceeds 2000 V per MIL
STD 883 Method 3015 and 200 V per
• Supports mixed–mode signal operation; 5V
Machine Model
input and output voltages with 3.3V V
CC
• Bus–hold inputs eliminate the need for
external pull-up resistors to hold unused
pins
DESCRIPTION
The 74LVT373 device is designed specifically
The 3-State output buffers are designed to
drive heavily loaded 3-State buses, MOS
memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all
eight 3-State buffers independent of the latch
operation.
for low–voltage (3.3V) V operation, but can
CC
• Live insertion/extraction permitted
provide a TTL interface to a 5V system
environment.
• No bus current loading when output is tied
to 5V bus
The 74LVT373 high-performance BiCMOS
device combines zero static and low dynamic
power dissipation with high speed and high
output drive.
• 8–bit transparent latch
When OE is Low, the latched or transparent
data appears at the outputs. When OE is
High, the outputs are in the High-impedance
”OFF” state, which means they will neither
drive nor load the bus.
• 3-State output buffers
The 74LVT373 device is an octal transparent
latch coupled to eight 3-State output buffers.
The two sections of the device are controlled
• Zero-static power dissipation
• Pin and function compatibility with ABT
• AC and DC performance compatibility with
ABT
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
t
t
Propagation delay
Dn to Qn
PLH
PHL
C = 50pF; V = 5V
4.2
ns
L
CC
C
Input capacitance
Output capacitance
Total supply current
V = 0V or V
CC
4
7
pF
pF
µA
IN
I
C
V = 0V or V
I CC
OUT
CCZ
I
Outputs disabled; V =5.5V
50
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
74LVT373D
DRAWING NUMBER
20–Pin Plastic SOL
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
0172D
1640B
TBD
20–Pin Plastic SSOP
20–Pin Plastic TSSOP
74LVT373DB
74LVT373PW
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1
OE
D0-D7
Q0-Q7
E
Output enable input (active-Low)
3, 4, 7, 8, 13, 14, 17, 18
Data inputs
2, 5, 6, 9, 12, 15, 16, 19
Data outputs
11
10
20
Enable input (active-High)
Ground (0V)
GND
V
CC
Positive supply voltage
2
July 1993
Philips Semiconductors Low Voltage Products
Objective specification
3.3 Volt ABT octal transparent latch (3–State)
74LVT373
FUNCTION TABLE
INPUTS
E
INTERNAL
REGISTER
OUTPUTS
Q0 – Q7
OPERATING MODE
OE
Dn
L
L
H
H
L
H
L
H
L
H
Enable and read register
L
L
↓
↓
i
h
L
H
L
H
Latch and read register
Hold
L
L
X
NC
NC
H
H
L
H
X
Dn
NC
Dn
Z
Z
Disable outputs
H
h
L
l
=
=
=
=
High voltage level
High voltage level one set-up time prior to the High-to-Low E transition
Low voltage level
Low voltage level one set-up time prior to the High-to-Low E transition
NC= No change
X
Z
↓
=
=
=
Don’t care
High impedance “off” state
High-to-Low E transition
LOGIC DIAGRAM
D0
3
D1
D2
D3
D4
13
D5
14
D6
17
D7
18
4
7
8
D
D
E
D
E
D
E
D
E
D
E
D
E
D
E
Q
Q
Q
Q
Q
Q
Q
E
Q
11
1
E
OE
2
5
6
9
12
Q4
15
Q5
16
Q6
19
Q7
Q0
Q1
Q2
Q3
3
July 1993
Philips Semiconductors Low Voltage Products
Objective specification
3.3 Volt ABT octal transparent latch (3–State)
74LVT373
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +4.6
–18
UNIT
V
V
CC
I
IK
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–1.2 to +5.5
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
DC output voltage
output in Off or High state
output in Low state
–0.5 to +5.5
64
OUT
OUT
I
DC output current
mA
°C
T
stg
Storage temperature range
–65 to 150
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to abso-
lute–maximum–rated conditions for extended periods may affect device reliability.
2. The performance capability of a high–performance integrated circuit in conjunction with its thermal environment can create junction tempera-
tures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
Min
2.7
0
Max
V
DC supply voltage
3.6
V
V
CC
V
Input voltage
V
CC
I
V
High-level input voltage
Input voltage
2.0
V
IH
V
0.8
–32
64
V
IL
I
High-level output current
Low-level output current
Input transition rise or fall rate
mA
mA
ns/V
°C
OH
I
OL
∆t/∆v
0
0
10
T
amb
Operating free-air temperature range
+70
4
July 1993
Philips Semiconductors Low Voltage Products
Objective specification
3.3 Volt ABT octal transparent latch (3–State)
74LVT373
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
V
1
MIN
TYP
MAX
V
IK
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.7V; I = –18mA
–1.2
IK
= 2.7 to 3.6V; I = –100µA
V
CC
-0.2
OH
V
OH
High-level output voltage
Low-level output voltage
= 2.7V; I = –8mA
2.4
V
OH
= 3.0V; I = –32mA
2.0
OH
= 2.7V; I = 100µA
0.2
0.5
OL
= 2.7V; I = 24mA
OL
V
OL
= 3.0V; I = 16mA
0.4
V
OL
= 3.0V; I = 32mA
0.5
OL
= 3.0V; I = 64mA
0.55
OL
V
V
V
= 3.6V; V = V or GND
Control pins
±1
10
20
CC
CC
CC
I
CC
= 0 or 3.6V; V = 5.5V
I
I
Input leakage current
Output off current
= 3.6V; V = 5.5V
µA
µA
I
I
4
V
CC
V
CC
V
CC
= 3.6V; V = V
CC
Data pins
1
-5
I
= 3.6V; V = 0
I
I
= 0V; V or V = 0 to 4.5V
±100
OFF
I
O
I
Bus Hold current A
or B ports
V
V
= 3V; V = 0.8V
75
µA
µA
HOLD
CC
I
= 3V; V = 2.0V
–75
CC
I
Current into an ouptut in the
I
EX
V
O
= 5.5V; V = 3.0V
100
µA
CC
High state when V > V
O
CC
I
V
V
V
V
= 3.6V; Outputs High, V = GND or V I 0
CC, O =
0.13
3
0.19
12
CCH
CC
CC
CC
CC
I
I
Quiescent supply current
= 3.6V; Outputs Low, V = GND or V I 0
CC, O =
mA
CCL
I
I
= 3.6V; Outputs Disabled; V = GND or V
I 0
CC, O =
0.13
0.19
CCZ
I
Additional supply current per
= 3V to 3.6V; One input at V -0.6V,
CC
∆I
0.2
mA
CC
2
input pin
Other inputs at V or GND
CC
Power up/down 3-State output
current
V
≤ 1.2V; V = 0.5V to V ; V = GND or V
;
CC
O
CC
I
CC
I
±100
µA
PU/PD
3
OE/OE = X
C
Input capacitance
Output capacitance
V = 3V or 0
4
pF
pF
I
I
C
V
O
= 3V or 0
11
O
NOTES:
1. All typical values are at V = 3.3V and T
= 25°C.
amb
CC
2. This is the increase in supply current for each input at the specificed voltage level other than V or GND
CC
3. This parameter is valid for any V between 0V and 1.3V with a transition time of up to 10msec. From V = 1.3V to V = 3.3V ± 0.3V a
CC
CC
CC
transition time of 100µsec is permitted. X = Don’t care.
4. Unused pins at V or GND.
CC
5
July 1993
Philips Semiconductors Low Voltage Products
Objective specification
3.3 Volt ABT octal transparent latch (3–State)
74LVT373
AC CHARACTERISTICS
GND = 0V; t = t = 6ns; C = 50pF; R = 500Ω, T = –40°C to +85°C.
R
F
L
L
amb
LIMITS
= 3.3V ±0.3V
SYMBOL
PARAMETER
WAVEFORM
V
CC
V
CC
= 2.7V
UNIT
1
MIN
TYP
MAX
MAX
t
t
Propagation delay
An to Yn
2.7
2.9
PLH
PHL
NO TAG
NO TAG
NO TAG
ns
ns
ns
t
Output enable time
OEn to Yn
3.4
3.4
PZH
t
PZL
t
Output disable time
OEn to Yn
3.7
2.6
PHZ
t
PLZ
NOTE:
1. All typical values are at V = 3.3V and T
= 25°C.
amb
CC
AC WAVEFORMS
V
M
= 1.5V, V = GND to 3.0V
IN
V
V
M
E
V
V
V
t
M
t
Dn
M
M
M
t
(H)
t
w
PLH
PHL
t
PHL
PLH
Qn
V
V
M
M
Qn
V
V
M
M
Waveform 1. Propagation Delay, Enable to
Output, and Enable Pulse Width
Waveform 2. Propagation Delay for Data
to Outputs
V
V
V
V
Dn
E
M
M
M
M
t (H)
t (L)
s
t
(H)
t (L)
h
s
h
V
V
M
M
Waveform 3. Data Setup and Hold Times
OE
V
V
V
V
M
OE
Qn
M
t
M
M
t
t
t
PLZ
PZH
PHZ
PZL
V
–0.3V
0V
OH
V
V
M
M
Qn
V
+0.3V
0V
OL
Waveform 4. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
Waveform 5. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
6
July 1993
Philips Semiconductors Low Voltage Products
Objective specification
3.3 Volt ABT octal transparent latch (3–State)
74LVT373
TEST CIRCUIT AND WAVEFORM
V
t
W
6V
AMP (V)
90%
CC
90%
NEGATIVE
PULSE
V
V
M
OPEN
GND
M
10%
10%
90%
V
V
OUT
IN
R
R
L
L
0V
PULSE
GENERATOR
D.U.T
t
t
(t
(t
)
t
t
(t )
R
THL
F
TLH
)
(t )
F
R
C
TLH
R
THL
T
L
AMP (V)
90%
M
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
0V
SWITCH POSITION
V
= 1.5V
M
TEST
/t
SWITCH
GND
6V
Input Pulse Definition
t
PHZ PZH
t
/t
PLZ PZL
t
/t
open
PLH PHL
INPUT PULSE REQUIREMENTS
DEFINITIONS
R = Load resistor; see AC CHARACTERISTICS for value.
L
FAMILY
Amplitude
(Min)
Rep. Rate
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance;
L
74LVT
V
CC
≤1MHz
500ns ≤2.5ns ≤2.5ns
see AC CHARACTERISTICS for value.
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
7
July 1993
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TI
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