74LVTN16245BDGG [NXP]
3.3 V 16-bit transceiver; 3-state; 3.3 V 16位收发器;三态
| 型号： | 74LVTN16245BDGG |
| 厂家： | 
NXP |
| 描述： | 3.3 V 16-bit transceiver; 3-state |
| 文件： | 总16页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVTN16245B
3.3 V 16-bit transceiver; 3-state
Rev. 01 — 29 July 2009
Product data sheet
1. General description
The 74LVTN16245B is a high-performance BiCMOS product designed for VCC operation
at 3.3 V.
This device is a 16-bit transceiver featuring non-inverting 3-state bus compatible outputs
in both send and receive directions. The control function implementation minimizes
external timing requirements. The device features an output enable input (nOE) for easy
cascading and a direction input (nDIR) for direction control.
2. Features
I 16-bit bus interface
I 3-state buffers
I Output capability: +64 mA and −32 mA
I TTL input and output switching levels
I Input and output interface capability to systems at 5 V supply
I Power-up 3-state
I Live insertion and extraction permitted
I No bus current loading when output is tied to 5 V bus
I Latch-up protection
N JESD78 Class II exceeds 500 mA
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVTN16245BDGG −40 °C to +85 °C
TSSOP48
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
SOT362-1
74LVTN16245BBQ −40 °C to +85 °C
HUQFN60U plastic thermal enhanced ultra thin quad flat
package; no leads; 60 terminals; UTLP based;
body 4 x 6 x 0.55 mm
SOT1025-1
74LVTN16245B
NXP Semiconductors
3.3 V 16-bit transceiver; 3-state
4. Functional diagram
2DIR
1DIR
2OE
2B0
2B1
2B2
2B3
2B4
2B5
2B6
1OE
1B0
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B7
001aaa789
Fig 1. Logic symbol
74LVTN16245B_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 29 July 2009
2 of 16
74LVTN16245B
NXP Semiconductors
3.3 V 16-bit transceiver; 3-state
1OE
G3
1DIR
3EN1[BA]
3EN2[AB]
G6
2OE
2DIR
6EN4[BA]
6EN5[AB]
1A0
1
1B0
2
1A1
1A2
1A3
1A4
1A5
1A6
1A7
2A0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
4
5
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2B1
2B2
2B3
2B4
2B5
2B6
2B7
001aak306
Fig 2. IEC logic symbol
74LVTN16245B_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 29 July 2009
3 of 16
74LVTN16245B
NXP Semiconductors
3.3 V 16-bit transceiver; 3-state
5. Pinning information
5.1 Pinning
74LVTN16245B
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1OE
1A0
1A1
GND
1A2
1A3
1B0
1B1
GND
1B2
1B3
3
4
5
6
7
V
CC
V
CC
8
1B4
1B5
GND
1B6
1B7
2B0
2B1
GND
2B2
2B3
1A4
1A5
GND
1A6
1A7
2A0
2A1
GND
2A2
2A3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V
CC
V
CC
2B4
2B5
2A4
2A5
GND
2A6
2A7
2OE
GND
2B6
2B7
2DIR
001aak307
Fig 3. Pin configuration SOT362-1 (TSSOP48)
74LVTN16245B_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 29 July 2009
4 of 16
74LVTN16245B
NXP Semiconductors
3.3 V 16-bit transceiver; 3-state
terminal 1
index area
D1
A32
D5
A31
A30
A29
A28
A27
D8
D4
B20
B19
B18
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
B1
B2
B3
B4
B5
B6
B7
B17
B16
B15
B14
B13
B12
B11
74LVTN16245B
(1)
GND
D6
B8
B9
B10
D7
D2
A11
A12
A13
A14
A15
A16
D3
001aak308
Transparent top view
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig 4. Pin configuration SOT1025-1 (HUQFN60U)
74LVTN16245B_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 29 July 2009
5 of 16
74LVTN16245B
NXP Semiconductors
3.3 V 16-bit transceiver; 3-state
5.2 Pin description
Table 2.
Symbol
Pin description
Pin
Description
SOT362-1
SOT1025-1
1DIR, 2DIR
1B0 to 1B7
1, 24
A30, A13
direction control input
data input/output
2, 3, 5, 6, 8, 9, 11, 12
B20, A31, D5, D1, A2, B2, B3,
A5
2B0 to 2B7
GND
13, 14, 16, 17, 19, 20, 22, 23
4, 10, 15, 21, 28, 34, 39, 45
A6, B5, B6, A9, D2, D6, A12, B8 data input/output
A32, A3, A8, A11, A16, A19,
A24, A27
ground (0 V)
VCC
7, 18, 31, 42
A1, A10, A17, A26
A29, A14
supply voltage
1OE, 2OE
2A0 to 2A7
48, 25
output enable input (active LOW)
data input/output
36, 35, 33, 32, 30, 29, 27, 26
A21, B13, B12, A18, D3, D7,
A15, B10
1A0, to 1A7
n.c.
47, 46, 44, 43, 41, 40, 38, 37
-
B18, A28, D8, D4, A25, B16,
B15, A22
data input/output
not connected
A4, A7, A20, A23, B1, B4, B7,
B9, B11, B14, B17, B19
6. Functional description
Table 3.
Function table [1]
Control
Input/output
nOE
L
nDIR
nAn
nBn
L
output nAn = nBn
input
L
H
X
input
Z
output nBx = nAx
Z
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
−0.5
−0.5
−0.5
Max
+4.6
+7.0
+7.0
Unit
V
supply voltage
input voltage
output voltage
[1]
[1]
V
VO
output in OFF-state or
HIGH-state
V
IIK
IOK
IO
input clamping current
output clamping current
output current
VI < 0 V
−50
−50
-
-
mA
mA
mA
mA
°C
VO < 0 V
-
output in LOW-state
output in HIGH-state
128
-
−64
−65
-
Tstg
Tj
storage temperature
junction temperature
+150
150
[2]
°C
74LVTN16245B_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 29 July 2009
6 of 16
74LVTN16245B
NXP Semiconductors
3.3 V 16-bit transceiver; 3-state
Table 4.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
Ptot
total power dissipation
Tamb = −40 °C to +85 °C
TSSOP48 package
HUQFN60U package
[3]
[4]
-
-
500
mW
mW
1000
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
[3] Above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
[4] Above 70 °C the value of Ptot derates linearly with 1.8 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
VCC
VI
Recommended operating conditions
Parameter
Conditions
Min
2.7
0
Typ
Max
3.6
5.5
-
Unit
V
supply voltage
-
-
-
-
-
-
-
input voltage
V
VIH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
2.0
-
V
VIL
0.8
-
V
IOH
−32
-
mA
mA
mA
IOL
none
32
64
current duty cycle ≤ 50 %;
fi ≥ 1 kHz
-
Tamb
ambient temperature
in free-air
−40
-
-
+85
10
°C
∆t/∆V
input transition rise and fall rate outputs enabled
-
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
Tamb = −40 °C to +85 °C
VIK
input clamping voltage
VCC = 2.7 V; IIK = −18 mA
−1.2
−0.85
-
-
-
-
V
V
V
V
VOH
HIGH-level output voltage IOH = −100 µA; VCC = 2.7 V to 3.6 V
VCC − 0.2 VCC
IOH = −8 mA; VCC = 2.7 V
2.4
2.0
2.5
2.3
IOH = −32 mA; VCC = 3.0 V
VOL
LOW-level output voltage VCC = 2.7 V
IOL = 100 µA
-
-
0.07
0.3
0.2
0.5
V
V
IOL = 24 mA
VCC = 3.0 V
IOL = 16 mA
-
-
-
0.25
0.3
0.4
V
V
V
IOL = 32 mA
0.5
IOL = 64 mA
0.4
0.55
74LVTN16245B_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 29 July 2009
7 of 16
74LVTN16245B
NXP Semiconductors
3.3 V 16-bit transceiver; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
II
input leakage current
control pins
VCC = 3.6 V; VI = VCC or GND
VCC = 0 V or 3.6 V; VI = 5.5 V
input/output data pins; VCC = 3.6 V
VI = 5.5 V
-
-
0.1
0.1
±1
µA
µA
10
[2]
-
0.1
0.5
−0.1
0.1
75
20
µA
µA
µA
µA
µA
VI = VCC
-
10
VI = 0 V
−5
-
-
IOFF
ILO
power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V
±100
125
output leakage current
output in HIGH-state when VO > VCC
VO = 5.5 V; VCC = 3.0 V
;
-
[3]
IO(pu/pd) power-up/power-down
output current
V
CC ≤ 1.2 V; VO = 0.5 V to VCC
;
-
40
±100
µA
VI = GND or VCC; nOE = don’t care
ICC
supply current
VCC = 3.6 V; VI = GND or VCC; IO = 0 A
output HIGH
-
-
-
-
0.07
4.0
0.12
6.0
mA
mA
mA
mA
output LOW
[4]
[5]
outputs disabled
0.07
0.1
0.12
0.2
∆ICC
additional supply current per input pin; VCC = 3.0 V to 3.6 V; one input
at VCC − 0.6 V other inputs at VCC or GND
CI
input capacitance
pins nDIR and nOE, VO = 0 V or 3.0 V
-
-
3
9
-
-
pF
pF
Cio(off)
off-state input/output
capacitance
pins nAn and nBn, outputs disabled;
VO = GND or VCC
[1] Typical values are measured at VCC = 3.3 V and at Tamb = 25 °C.
[2] Unused pins at VCC or GND.
[3] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V
a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only.
[4] ICC is measured with outputs pulled to VCC or GND.
[5] This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
74LVTN16245B_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 29 July 2009
8 of 16
74LVTN16245B
NXP Semiconductors
3.3 V 16-bit transceiver; 3-state
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
Tamb = −40 °C to +85 °C
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
LOW to HIGH
propagation delay
nAn to nBn or nBn to nAn;
see Figure 5
VCC = 2.7 V
-
-
3.5
3.3
ns
ns
VCC = 3.0 V to 3.6 V
1.0
1.9
HIGH to LOW
propagation delay
nAn to nBn or nBn to nAn;
see Figure 5
VCC = 2.7 V
-
-
3.5
3.3
ns
ns
VCC = 3.0 V to 3.6 V
1.0
1.7
OFF-state to HIGH
propagation delay
nOE to nAn or nBn;
see Figure 6
VCC = 2.7 V
-
-
5.3
4.5
ns
ns
VCC = 3.0 V to 3.6 V
1.0
2.8
OFF-state to LOW
propagation delay
nOE to nAn or nBn;
see Figure 6
VCC = 2.7 V
-
-
5.1
4.1
ns
ns
VCC = 3.0 V to 3.6 V
1.0
2.8
HIGH to OFF-state
propagation delay
nOE to nAn or nBn;
see Figure 6
VCC = 2.7 V
-
-
5.7
5.1
ns
ns
VCC = 3.0 V to 3.6 V
1.5
3.2
LOW to OFF-state
propagation delay
nOE to nAn or nBn;
see Figure 6
VCC = 2.7 V
-
-
4.6
4.6
ns
ns
VCC = 3.0 V to 3.6 V
1.5
3.0
[1] Typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
74LVTN16245B_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 29 July 2009
9 of 16
74LVTN16245B
NXP Semiconductors
3.3 V 16-bit transceiver; 3-state
11. Waveforms
V
I
nAn, nBn
input
V
M
GND
t
t
PHL
PLH
V
OH
nBn, nAn
output
V
M
mna477
V
OL
Measurements points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 5. Propagation delay input (nAn, nBn) to output (nBn, nAn)
V
I
nOE input
V
M
t
0 V
t
PZL
PLZ
3.0 V
nAn or nBn
output
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
nBn or nAn
output
V
M
0 V
001aaj658
Measurements points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Enable and disable times
Table 8.
Input
VM
Measurement points
Output
VM
VX
VY
1.5 V
1.5 V
VOL + 0.3 V
VOH − 0.3 V
74LVTN16245B_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 29 July 2009
10 of 16
74LVTN16245B
NXP Semiconductors
3.3 V 16-bit transceiver; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
DUT
R
T
C
L
R
L
001aae235
Test data is given in Table 9.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 7. Load circuit for measuring switching times
Table 9.
Input
VI
Test data
Load
CL
VEXT
fi
tW
tr, tf
RL
tPHZ, tPZH
GND
tPLZ, tPZL
tPLH, tPHL
2.7 V
≤ 10 MHz
500 ns
≤ 2.5 ns
50 pF
500 Ω
6 V
open
74LVTN16245B_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 29 July 2009
11 of 16
74LVTN16245B
NXP Semiconductors
3.3 V 16-bit transceiver; 3-state
12. Package outline
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
H
v
M
A
y
E
Z
48
25
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
24
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.8
0.4
mm
1.2
0.5
1
0.25
0.25
0.08
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT362-1
MO-153
Fig 8. Package outline SOT362-1 (TSSOP48)
74LVTN16245B_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 29 July 2009
12 of 16
74LVTN16245B
NXP Semiconductors
3.3 V 16-bit transceiver; 3-state
HUQFN60U: plastic thermal enhanced ultra thin quad flat package; no leads
60 terminals; UTLP based; body 4 x 6 x 0.55 mm
SOT1025-1
D
B
A
terminal 1
index area
E
A
A
1
detail X
e
2
M
M
v
C A
B
v
C A
C
B
e
1
b
M
M
w
C
w
C
1/2 e
e
y
y
C
1
L
1
D2
D6
D3
D7
A11
A16
B8
B10
L
eR
A10
B7
A17
e
B11
E
e
3
e
4
h
1/2 e
B1
A1
B17
A26
terminal 1
index area
D5
D1
D8
D4
B20
B18
A32
A27
D
h
X
k
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
b
D
D
h
E
E
e
e
1
e
2
e
3
e
4
eR
k
L
L
v
w
y
y
1
h
1
max
0.05 0.35 4.1
0.00 0.25
1.9
1.8
6.1
5.9
3.9
3.8
0.25 0.35 0.125
0.15 0.25 0.025
mm
0.6
0.5
1
2.5
3
4.5
0.5
0.07 0.05 0.08 0.1
3.9
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
- - -
JEDEC
JEITA
07-08-28
07-11-14
SOT1025-1
- - -
- - -
Fig 9. Package outline SOT1025-1 (HUQFN60U)
74LVTN16245B_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 29 July 2009
13 of 16
74LVTN16245B
NXP Semiconductors
3.3 V 16-bit transceiver; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
BiCMOS
DUT
Description
Bipolar Complementary Metal Oxide Semiconductor
Device Under Test
ESD
Electrostatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
20090729
Data sheet status
Change notice
Supersedes
74LVTN16245B_1
Product data sheet
-
-
74LVTN16245B_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 29 July 2009
14 of 16
74LVTN16245B
NXP Semiconductors
3.3 V 16-bit transceiver; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVTN16245B_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 29 July 2009
15 of 16
74LVTN16245B
NXP Semiconductors
3.3 V 16-bit transceiver; 3-state
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
6
Functional description . . . . . . . . . . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 29 July 2009
Document identifier: 74LVTN16245B_1
相关型号：
74LVU04BQ
IC LV/LV-A/LVX/H SERIES, HEX 1-INPUT INVERT GATE, PQCC14, 2.50 X 3 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT-762-1, DHVQFN-14, Gate
NXP
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