87C552 [NXP]
80C51 8-bit microcontroller 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O; 80C51的8位微控制器8K / 256 OTP ， 8通道10位A / D ， I2C ， PWM ，捕获/比较，高I / O
| 型号： | 87C552 |
| 厂家： | 
NXP |
| 描述： | 80C51 8-bit microcontroller 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O |
| 文件： | 总24页 (文件大小：193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
NOTICE
PLEASE SEE THE P87C552 DATA SHEET FOR NEW DESIGN-INS
87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM,
capture/compare, high I/O
Product specification
1998 May 01
Supersedes data of 1998 Jan 19
IC20 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I C, PWM, capture/compare, high I/O
87C552
2
DESCRIPTION
The 87C552 Single-Chip 8-Bit Microcontroller is manufactured in an
advanced CMOS process and is a derivative of the 80C51
microcontroller family. The 87C552 has the same instruction set as
the 80C51. Three versions of the derivative exist:
• 83C552—8k bytes mask programmable ROM
• 80C552—ROMless version of the 83C552
• 87C552—8k bytes EPROM
The 87C552 contains a 8k × 8 a volatile 256 × 8 read/write data
FEATURES
• 80C51 central processing unit
memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit
timer/event counters (identical to the timers of the 80C51), an
additional 16-bit timer coupled to capture and compare latches, a
15-source, two-priority-level, nested interrupt structure, an 8-input
ADC, a dual DAC pulse width modulated interface, two serial
• 8k × 8 EPROM expandable externally to 64k bytes
• An additional 16-bit timer/counter coupled to four capture registers
2
interfaces (UART and I C-bus), a “watchdog” timer and on-chip
and three compare registers
oscillator and timing circuits. For systems that require extra
capability, the 87C552 can be expanded using standard TTL
compatible memories and logic.
• Two standard 16-bit timer/counters
• 256 × 8 RAM, expandable externally to 64k bytes
• Capable of producing eight synchronized, timed outputs
• A 10-bit ADC with eight multiplexed analog inputs
• Two 8-bit resolution, pulse width modulation outputs
In addition, the 87C552 has two software selectable modes of power
reduction—idle mode and power-down mode. The idle mode freezes
the CPU while allowing the RAM, timers, serial ports, and interrupt
system to continue functioning. The power-down mode saves the
RAM contents but freezes the oscillator, causing all other chip
functions to be inoperative.
• Five 8-bit I/O ports plus one 8-bit input port shared with analog
inputs
The device also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic plus bit-handling
capabilities. The instruction set consists of over 100 instructions: 49
one-byte, 45 two-byte, and 17 three-byte. With a 16MHz crystal,
58% of the instructions are executed in 0.75µs and 40% in 1.5µs.
Multiply and divide instructions require 3µs.
2
• I C-bus serial I/O port with byte oriented master and slave
functions
• Full-duplex UART compatible with the standard 80C51
• On-chip watchdog timer
• 16MHz speed
• Extended temperature ranges
• OTP package available
ORDERING INFORMATION
FREQ
MHz
EPROM
TEMPERATURE °C AND PACKAGE
DRAWING NUMBER
S87C552-4A68
S87C552-4BA
S87C552-5A68
0 to +70, Plastic Leaded Chip Carrier
0 to +70, Plastic Quad Flat Pack
16
SOT188-3
SOT318-2
SOT188-3
16
–40 to +85, Plastic Leaded Chip Carrier
16
NOTE:
1. For ROM and ROMless see data sheet 80C552/83C552
2
1998 May 01
853-1690 19336
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I C, PWM, capture/compare, high I/O
87C552
2
BLOCK DIAGRAM
T0
T1
INT0
INT1
PWM0 PWM1
ADC0-7 SDA SCL
AV
AV
REF
SS
–
+
V
V
SS
5
1
1
DD
STADC
3
3
3
3
AV
DD
XTAL1
T0, T1
PROGRAM
MEMORY
8k x 8
DATA
MEMORY
256 x 8 RAM
DUAL
PWM
SERIAL
C PORT
TWO 16-BIT
TIMER/EVENT
COUNTERS
XTAL2
EA
ADC
2
CPU
I
EPROM
ALE
80C51 CORE
EXCLUDING
ROM/RAM
PSEN
3
WR
RD
8-BIT INTERNAL BUS
3
0
16
AD0-7
T2
T2
16-BIT
TIMER/
EVENT
FOUR
16-BIT
CAPTURE
16-BIT
COMPARA-
TORS
WITH
REGISTERS
COMPARA-
TOR
OUTPUT
T3
16
PARALLEL I/O
PORTS AND
EXTERNAL BUS
SERIAL
UART
PORT
8-BIT
PORT
WATCHDOG
TIMER
2
LATCHES
SELECTION
COUNTERS
A8-15
3
3
1
1
1
4
P0
P1
P2
P3
TxD
RxD
P5
P4
CT0I-CT3I
T2
RT2
CMSR0-CMSR5 RST EW
CMT0, CMT1
3
4
5
0
1
2
ALTERNATE FUNCTION OF PORT 3
ALTERNATE FUNCTION OF PORT 4
ALTERNATE FUNCTION OF PORT 5
ALTERNATE FUNCTION OF PORT 0
ALTERNATE FUNCTION OF PORT 1
ALTERNATE FUNCTION OF PORT 2
SU00211
3
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I C, PWM, capture/compare, high I/O
87C552
2
LOGIC SYMBOL
PIN CONFIGURATIONS
V
V
9
1
61
SS
DD
XTAL1
XTAL2
10
60
44
EA/V
ALE/PROG
PSEN
PLASTIC
LEADED
CHIP CARRIER
PP
LOW ORDER
ADDRESS AND
DATA BUS
AV
AV
AVref+
AVref–
STADC
SS
DD
26
CT0I
CT1I
CT2I
CT3I
T2
RT2
SCL
SDA
27
43
PWM0
PWM1
Pin Function
Pin Function
Pin Function
1
2
P5.0/ADC0
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
NC
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
PSEN
V
ALE/PROG
DD
ADC0-7
3
STADC
EA/V
PP
4
PWM0
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
AVref–
5
PWM1
6
EW
HIGH ORDER
ADDRESS AND
DATA BUS
7
8
9
P4.0/CMSR0
P4.1/CMSR1
P4.2/CMSR2
P4.3/CMSR3
P4.4/CMSR4
P4.5/CMSR5
P4.6/CMT0
P4.7/CMT1
RST
P1.0/CT0I
P1.1/CT1I
P1.2/CT2I
P1.3/CT3I
P1.4/T2
CMSR0-5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
NC
XTAL2
XTAL1
RxD/DATA
TxD/CLOCK
INT0
V
SS
AVref+
V
INT1
T0
T1
WR
RD
SS
CMT0
CMT1
AV
AV
SS
NC
DD
P2.0/A08
P2.1/A09
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
RST
EW
P5.7/ADC7
P5.6/ADC6
P5.5/ADC5
P5.4/ADC4
P5.3/ADC3
P5.2/ADC2
P5.1/ADC1
SU00210
P1.5/RT2
P1.6/SCL
P1.7/SDA
SU00208
PLASTIC QUAD FLAT PACK PIN FUNCTIONS
Pin Function
Pin Function
Pin Function
Pin Function
AV
1
2
3
P4.1/CMSR1
P4.2/CMSR2
NC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
NC
NC
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
P2.3/A11
P2.4/A12
NC
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
SS
NC
AV
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
NC
NC
NC
XTAL2
XTAL1
IC
DD
80
65
4
5
6
P4.3/CMSR3
P4.4/CMSR4
P4.5/CMSR5
NC
P5.7/ADC7
P5.6/ADC6
P5.5/ADC5
P5.4/ADC4
P5.3/ADC3
P5.2/ADC2
P5.1/ADC1
P5.0/ADC0
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE/PROG
EA/V
PP
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
7
8
P4.6/CMT0
P4.7/CMT1
1
64
41
9
RST
10
11
12
13
14
15
16
17
18
19
20
P1.0/CT0I
P1.1/CT1I
P1.2/CT2I
PQFP
V
DD
24
IC
P1.3/CT3I
P1.4/T2
V
V
V
STADC
PWM0
PWM1
EW
NC
NC
SS
SS
SS
P1.5/RT2
P1.6/SCL
P1.7/SDA
P3.0/RxD
P3.1/TxD
P3.2/INT0
25
40
NC
P0.1/AD1
P0.0/AD0
AVref–
AVref+
P2.0/A08
P2.1/A09
P2.2/A10
P4.0/CMSR0
NC = Not Connected
IC = Internally Connected (do not use)
SU00209
4
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I C, PWM, capture/compare, high I/O
87C552
2
PIN DESCRIPTION
PIN NO.
MNEMONIC
PLCC
QFP
TYPE
NAME AND FUNCTION
V
DD
2
72
I
Digital Power Supply: +5V power supply pin during normal operation, idle and
power-down mode.
STADC
3
74
I
Start ADC Operation: Input starting analog to digital conversion (ADC operation can also
be started by software).
PWM0
PWM1
EW
4
5
75
76
O
O
Pulse Width Modulation: Output 0.
Pulse Width Modulation: Output 1.
6
77
I
Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode.
P0.0-P0.7
57-50
58-51
I/O
Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written
to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application it uses strong internal pull-ups when emitting 1s. Port 0 is also used to input
the code byte during programming and to output the code byte during verification.
P1.0-P1.7
16-23
16-21
22-23
16-19
20
10-17
10-15
16-17
10-13
14
I/O
I/O
I/O
I
Port 1: 8-bit I/O port. Alternate functions include:
(P1.0-P1.5): Quasi-bidirectional port pins.
(P1.6, P1.7): Open drain port pins.
CT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2.
T2 (P1.4): T2 event input.
I
21
22
23
15
16
17
I
RT2 (P1.5): T2 timer reset signal. Rising edge triggered.
2
I/O
I/O
SCL (P1.6): Serial port clock line I C-bus.
2
SDA (P1.7): Serial port data line I C-bus.
Port 1 is also used to input the lower order address byte during EPROM programming and
verification. A0 is on P1.0, etc.
P2.0-P2.7
P3.0-P3.7
39-46
38-42,
45-47
I/O
I/O
Port 2: 8-bit quasi-bidirectional I/O port.
Alternate function: High-order address byte for external memory (A08-A15). Port 2 is also
used to input the upper order address during EPROM programming and verification. A8 is
on P2.0, A9 on P2.1, through A12 on P2.4.
24-31
18-20,
23-27
Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include:
24
25
26
27
28
29
30
31
18
19
20
23
24
25
26
27
RxD(P3.0): Serial input port.
TxD (P3.1): Serial output port.
INT0 (P3.2): External interrupt.
INT1 (P3.3): External interrupt.
T0 (P3.4): Timer 0 external input.
T1 (P3.5): Timer 1 external input.
WR (P3.6): External data memory write strobe.
RD (P3.7): External data memory read strobe.
P4.0-P4.7
P5.0-P5.7
7-14
7-12
80, 1-2
4-8
I/O
O
Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include:
80, 1-2
4-6
CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with
timer T2.
13, 14
7, 8
O
I
CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2.
68-62,
1
71-64,
Port 5: 8-bit input port.
ADC0-ADC7 (P5.0-P5.7): Alternate function: Eight input channels to ADC.
RST
15
9
I/O
I
Reset: Input to reset the 87C552. It also provides a reset pulse as output when timer T3
overflows.
XTAL1
35
32
Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the
internal clock generator. Receives the external clock signal when an external oscillator is
used.
XTAL2
34
31
O
Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit
when an external clock is used.
V
36, 37
47
34-36
48
I
Digital ground.
SS
PSEN
O
Program Store Enable: Active-low read strobe to external program memory.
5
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I C, PWM, capture/compare, high I/O
87C552
2
PIN DESCRIPTION (Continued)
PIN NO.
MNEMONIC
PLCC
QFP
TYPE
NAME AND FUNCTION
ALE/PROG
48
49
O
Address Latch Enable: Latches the low byte of the address during accesses to external
memory. It is activated every six oscillator periods. During an external data memory
access, one ALE pulse is skipped. ALE can drive up to eight LS TTL inputs and handles
CMOS inputs without an external pull-up. This pin is also the program pulse input (PROG)
during EPROM programming.
EA/V
49
50
I
External Access: When EA is held at TTL level high, the CPU executes out of the internal
program ROM provided the program counter is less than 8192. When EA is held at TTL
low level, the CPU executes out of external program memory. EA is not allowed to float.
PP
This pin also receives the 12.75V programming supply voltage (V ) during EPROM
PP
programming.
AV
AV
AV
AV
58
59
60
61
59
60
61
63
I
I
I
I
Analog to Digital Conversion Reference Resistor: Low-end.
Analog to Digital Conversion Reference Resistor: High-end.
Analog Ground
REF–
REF+
SS
Analog Power Supply
DD
NOTE:
1. To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than V + 0.5V or V – 0.5V,
DD
SS
respectively.
OSCILLATOR CHARACTERISTICS
IDLE MODE
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol.
In the idle mode, the CPU puts itself to sleep while some of the
on-chip peripherals stay active. The instruction to invoke the idle
mode is the last instruction executed in the normal operating mode
before the idle mode is activated. The CPU contents, the on-chip
RAM, and all of the special function registers remain intact during
this mode. The idle mode can be terminated either by any enabled
interrupt (at which time the process is picked up at the interrupt
service routine and continued), or by a hardware reset which starts
the processor in the same manner as a power-on reset.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
POWER-DOWN MODE
RESET
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. The control
bits for the reduced power modes are in the special function register
PCON. Table 1 shows the state of the I/O ports during low current
operating modes.
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
V
DD
and RST must come up at the same time for a proper start-up.
Table 1. External Pin Status During Idle and Power-Down Modes
PROGRAM
MEMORY
PWM0/
PWM1
MODE
Idle
ALE
PSEN
PORT 0
Data
PORT 1
Data
PORT 2
Data
PORT 3
Data
PORT 4
Data
Internal
1
1
0
0
1
1
0
0
High
High
High
High
Idle
External
Internal
Float
Data
Address
Data
Data
Data
Power-down
Power-down
Data
Data
Data
Data
External
Float
Data
Data
Data
Data
6
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I C, PWM, capture/compare, high I/O
87C552
2
Serial Control Register (S1CON) – See Table 2
S1CON (D8H)
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.
Table 2. Serial Clock Rates
BIT FREQUENCY (kHz) AT f
OSC
CR2
CR1
CR0
6MHz
12MHz
16MHz
f
DIVIDED BY
OSC
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
23
27
31.25
37
6.25
50
47
54
62.5
75
12.5
62.5
71
83.3
100
17
256
224
192
160
960
120
60
1
100
200
0.5 < 62.5
0 to 224
133
267
1
100
0.25 < 62.5
0 to 225
0.67 < 56
0 to 223
96 × (256 – (reload value Timer 1))
Timer 1 in Mode 2.
NOTE:
2
2
1. These frequencies exceed the upper limit of 100kHz of the I C-bus specification and cannot be used in an I C-bus application.
1, 2, 3
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
–65 to +150
–0.5 to +13
–0.5 to +6.5
5.0
UNIT
°C
V
Storage temperature range
Voltage on EA/V to V
PP
SS
Voltage on any other pin to V
V
SS
Input, output DC current on any single I/O pin
mA
W
Power dissipation (based on package heat transfer limitations, not device power
consumption)
1.0
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise
SS
noted.
DEVICE SPECIFICATIONS
SUPPLY VOLTAGE (V)
FREQUENCY (MHz)
TYPE
MIN
4.5
MAX
5.5
MIN
3.5
MAX
16
TEMPERATURE RANGE (°C)
0 to +70
P87C552-4
P87C552-5
4.5
5.5
3.5
16
–40 to +85
7
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I C, PWM, capture/compare, high I/O
87C552
2
DC ELECTRICAL CHARACTERISTICS
V
SS
, AV = 0V
SS
TEST
LIMITS
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
40
UNIT
mA
I
I
I
Supply current operating:
PCA8XC552-5-16
See notes 1 and 2
DD
f
= 16MHz
OSC
Idle mode:
87C552
See notes 1 and 3
= 16MHz
ID
f
7
mA
OSC
Power-down current:
87C552
See notes 1 and 4;
2V < V < V max
PD
PD
DD
50
µA
Inputs
V
V
V
V
V
V
Input low voltage, except EA, P1.6, P1.7
Input low voltage to EA
–0.5
–0.5
–0.5
0.2V –0.1
V
V
IL
DD
0.2V –0.3
IL1
IL2
IH
DD
5
Input low voltage to P1.6/SCL, P1.7/SDA
Input high voltage, except XTAL1, RST
Input high voltage, XTAL1, RST
0.3V
V
DD
0.2V +0.9
V
DD
V
DD
+0.5
+0.5
V
DD
0.7V
0.7V
V
IH1
IH2
DD
DD
5
Input high voltage, P1.6/SCL, P1.7/SDA
6.0
V
I
I
Logical 0 input current, ports 1, 2, 3, 4, except P1.6, P1.7
Logical 1-to-0 transition current, ports 1, 2, 3, 4, except P1.6, P1.7
Input leakage current, port 0, EA, STADC, EW
V
= 0.45V
–50
–650
10
µA
µA
µA
IL
TL
IN
See note 6
0.45V < V < V
DD
±I
±I
±I
IL1
IL2
IL3
I
0V < V < 6V
0V < V < 5.5V
I
Input leakage current, P1.6/SCL, P1.7/SDA
Input leakage current, port 5
10
1
µA
µA
DD
0.45V < V < V
I
DD
Outputs
7
V
V
Output low voltage, ports 1, 2, 3, 4, except P1.6, P1.7
I
I
= 1.6mA
= 3.2mA
0.45
0.45
V
V
OL
OL
7
Output low voltage, port 0, ALE, PSEN, PWM0,
PWM1
OL1
OL
7
V
V
Output low voltage, P1.6/SCL, P1.7/SDA
I
OL
= 3.0mA
0.4
V
OL2
Output high voltage, ports 1, 2, 3, 4, except P1.6/SCL, P1.7/SDA
OH
–I = 60µA
2.4
V
V
V
OH
–I = 25µA
0.75V
OH
DD
DD
–I = 10µA
OH
0.9V
V
V
Output high voltage (port 0 in external bus mode, ALE,
PSEN, PWM0, PWM1)
OH1
8
–I = 400µA
2.4
V
V
V
OH
–I = 150µA
0.75V
OH
DD
DD
–I = 40µA
OH
0.9V
Output high voltage (RST)
–I = 400µA
2.4
0.8V
V
V
OH2
OH
–I = 120µA
OH
DD
R
C
Internal reset pull-down resistor
Pin capacitance
50
150
10
kΩ
RST
IO
Test freq = 1MHz,
pF
T
= 25°C
amb
Analog Inputs
AV
Analog supply voltage:
DD
9
87C552
AV = V ±0.2V
4.5
5.5
1.2
V
DD
DD
AI
AI
Analog supply current: operating:
Port 5 = 0 to AV
mA
DD
DD
Idle mode:
87C552
ID
50
50
µA
µA
AI
PD
Power-down mode:
87C552
2V < AV < AV max
PD DD
8
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I C, PWM, capture/compare, high I/O
87C552
2
DC ELECTRICAL CHARACTERISTICS (Continued)
TEST
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
Analog Inputs (Continued)
AV
AV
Analog input voltage
Reference voltage:
AV –0.2
AV +0.2
V
IN
SS
DD
REF
AV
AV
AV –0.2
V
V
REF–
REF+
SS
AV +0.2
DD
R
C
Resistance between AV
and AV
REF–
10
50
15
kΩ
pF
REF
REF+
Analog input capacitance
Sampling time
IA
t
t
8t
CY
µs
ADS
ADC
Conversion time (including sampling time)
50t
µs
CY
10, 11, 12
DL
Differential non-linearity
±1
LSB
LSB
LSB
%
e
10, 13
IL
e
Integral non-linearity
±2
±2
10, 14
OS
Offset error
e
10, 15
G
Gain error
±0.4
±3
e
10, 16
A
e
Absolute voltage error
LSB
LSB
dB
M
CTC
Channel to channel matching
±1
17
C
Crosstalk between inputs of port 5
0–100kHz
–60
t
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1. See Figures 10 through 15 for I test conditions.
DD
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 10ns; V = V + 0.5V;
r
f
IL
SS
V
IH
= V – 0.5V; XTAL2 not connected; EA = RST = Port 0 = EW = V ; STADC = V
.
DD
DD
SS
3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 10ns; V = V + 0.5V;
r
f
IL
SS
V
IH
= V – 0.5V; XTAL2 not connected; Port 0 = EW = V ; EA = RST = STADC = V
.
DD
DD
SS
4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = V
;
DD
EA = RST = STADC = XTAL1 = V
.
SS
2
5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I C specification, so an input voltage below 1.5V will be recognized as a logic
0 while an input voltage above 3.0V will be recognized as a logic 1.
6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition
current reaches its maximum value when V is approximately 2V.
IN
7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due
OL
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no
OL
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
8. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the 0.9V specification when the
OH
DD
address bits are stabilizing.
9. The following condition must not be exceeded: V – 0.2V < AV < V + 0.2V.
DD
DD
DD
10.Conditions: AV
= 0V; AV = 5.0V. Measurement by continuous conversion of AV = –20mV to 5.12V in steps of 0.5mV, derivating
REF–
DD
IN
parameters from collected conversion results of ADC. AV
(87C552) = 4.977V. ADC is monotonic with no missing codes.
REF+
11. The differential non-linearity (DL ) is the difference between the actual step width and the ideal step width. (See Figure 1.)
e
12.The ADC is monotonic; there are no missing codes.
13.The integral non-linearity (IL ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
e
appropriate adjustment of gain and offset error. (See Figure 1.)
14.The offset error (OS ) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and
e
a straight line which fits the ideal transfer curve. (See Figure 1.)
15.The gain error (G ) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),
e
and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 1.)
16.The absolute voltage error (A ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
e
ADC and the ideal transfer curve.
17.This should be considered when both analog and digital signals are simultaneously input to port 5.
9
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I C, PWM, capture/compare, high I/O
87C552
2
Offset
error
Gain
error
OS
e
G
e
1023
1022
1021
1020
1019
1018
(2)
7
(1)
Code
Out
6
5
(5)
4
(4)
3
(3)
2
1
1 LSB
(ideal)
0
1
2
3
4
5
6
7
1018
1019
1020
1021
1022
)
1023
1024
AV (LSB
IN
ideal
Offset
error
OS
e
AV
– AV
REF–
REF+
1024
1 LSB =
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential non-linearity (DL ).
e
(4) Integral non-linearity (IL ).
e
(5) Center of a step of the actual transfer curve.
SU00212
Figure 1. ADC Conversion Characteristic
10
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I C, PWM, capture/compare, high I/O
87C552
2
1, 2
AC ELECTRICAL CHARACTERISTICS
12MHz CLOCK 16MHz CLOCK
VARIABLE CLOCK
SYMBOL
1/t
FIGURE
PARAMETER
Oscillator frequency
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
MHz
ns
2
2
2
2
2
2
2
2
2
2
2
2
3.5
16
CLCL
t
t
t
t
t
t
t
t
t
t
t
ALE pulse width
127
28
85
8
2t
–40
LHLL
CLCL
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
t
–55
ns
AVLL
LLAX
LLIV
CLCL
CLCL
48
28
t
–35
ns
234
145
150
83
4t
3t
–100
ns
CLCL
43
23
t
–40
ns
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLCL
PSEN pulse width
205
143
3t
–45
ns
CLCL
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
–105
ns
CLCL
0
0
0
ns
59
312
10
38
208
10
t
–25
ns
CLCL
5t
–105
ns
CLCL
10
ns
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
3, 4
3
Address valid to ALE low
RD pulse width
43
23
t
6t
6t
–40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVLL
CLCL
CLCL
CLCL
400
400
275
275
–100
–100
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
QVWX
DW
3
WR pulse width
3
RD low to valid data in
Data hold after RD
252
148
5t
–165
CLCL
3
0
0
0
3
Data float after RD
97
55
2t
–70
CLCL
3
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data before WR
517
585
300
350
398
238
8t
–150
–165
CLCL
CLCL
3
9t
3, 4
3, 4
4
200
203
23
138
120
3
3t
–50
3t
+50
CLCL
CLCL
4t
t
–130
–60
CLCL
CLCL
CLCL
CLCL
4
433
33
288
13
7t
t
–150
–50
4
Data hold after WR
WHQX
RLAZ
WHLH
4
RD low to address float
RD or WR high to ALE high
0
0
0
3, 4
43
123
23
103
t
–40
t
+40
CLCL
CLCL
External Clock
3
t
t
t
t
5
5
5
5
High time
20
20
20
20
20
20
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
3
Low time
3
Rise time
20
20
20
20
20
20
3
Fall time
4
Serial Timing – Shift Register Mode (Test Conditions: T
= 0°C to +70°C; V = 0V; Load Capaciatnce = 80pF)
SS
amb
t
t
t
t
t
6
6
6
6
6
Serial port clock cycle time
1.0
700
50
0
0.75
492
8
12t
µs
ns
ns
ns
ns
XLXL
CLCL
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
10t
–133
QVXH
XHQX
XHDX
XHDV
CLCL
2t
CLCL
–117
0
0
700
492
10t
–133
CLCL
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. t
= 1/f
= 83.3ns at f
= 62.5ns at f
= one oscillator clock period.
CLCL
CLCL
CLCL
OSC
t
t
= 12MHz.
= 16MHz.
OSC
OSC
4. These values are characterized but not 100% production tested.
11
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I C, PWM, capture/compare, high I/O
87C552
2
AC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
INPUT
OUTPUT
2
5
I C Interface (Refer to Figure 9)
1
1
1
t
t
t
t
t
t
t
t
t
t
t
t
t
t
START condition hold time
≥ 14 t
> 4.0µs
> 4.7µs
> 4.0µs
HD;STA
LOW
CLCL
CLCL
CLCL
SCL low time
≥ 16 t
≥ 14 t
SCL high time
HIGH
2
SCL rise time
≤ 1µs
–
RC
3
SCL fall time
≤ 0.3µs
≥ 250ns
≥ 250ns
≥ 250ns
≥ 0ns
< 0.3µs
FC
Data set-up time
> 20 t
– t
SU;DAT1
SU;DAT2
SU;DAT3
HD;DAT
SU;STA
SU;STO
BUF
CLCL
RD
1
SDA set-up time (before rep. START cond.)
SDA set-up time (before STOP cond.)
Data hold time
> 1µs
> 8 t
CLCL
> 8 t
– t
CLCL
FC
1
Repeated START set-up time
STOP condition set-up time
Bus free time
≥ 14 t
≥ 14 t
≥ 14 t
> 4.7µs
> 4.0µs
> 4.7µs
CLCL
CLCL
CLCL
1
1
2
SDA rise time
≤ 1µs
≤ 0.3µs
–
RD
3
SDA fall time
< 0.3µs
FD
NOTES:
1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1µs.
3. Spikes on the SDA and SCL lines with a duration of less than 3 t
SCL = 400pF.
will be filtered out. Maximum capacitance on bus-lines SDA and
CLCL
4. t
= 1/f
= one oscillator clock period at pin XTAL1. For 62ns (42s) < t
< 285ns (16MHz (24Hz) > f
> 3.5MHz) the SI01
OSC
CLCL
OSC
CLCL
2
interface meets the I C-bus specification for bit-rates up to 100 kbit/s.
5. These values are guaranteed but not 100% production tested.
12
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I C, PWM, capture/compare, high I/O
87C552
2
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always
P – PSEN
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
Q – Output data
R – RD signal
designations are:
A – Address
t – Time
V – Valid
C – Clock
W – WR signal
D – Input data
H – Logic level high
X – No longer a valid logic level
Z – Float
I
– Instruction (program memory contents)
Examples: t
= Time for address valid to ALE low.
= Time for ALE low to PSEN low.
AVLL
LLPL
L – Logic level low, or ALE
t
t
LHLL
ALE
t
t
LLPL
AVLL
t
PLPH
t
LLIV
t
PLIV
PSEN
t
LLAX
t
PXIZ
t
PLAZ
t
PXIX
A0–A7
INSTR IN
A0–A7
PORT 0
PORT 2
t
AVIV
A0–A15
A8–A15
SU00006
Figure 2. External Program Memory Read Cycle
ALE
PSEN
RD
t
WHLH
t
LLDV
t
t
LLWL
RLRH
t
RHDZ
t
LLAX
t
t
RLDV
AVLL
t
RLAZ
t
RHDX
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA IN
A0–A7 FROM PCL
INSTR IN
t
AVWL
t
AVDV
P2.0–P2.7 OR A8–A15 FROM DPH
A0–A15 FROM PCH
SU00007
Figure 3. External Data Memory Read Cycle
13
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I C, PWM, capture/compare, high I/O
87C552
2
ALE
t
WHLH
PSEN
t
t
WLWH
LLWL
WR
t
t
t
LLAX
WHQX
t
AVLL
QVWX
t
DW
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA OUT
A0–A7 FROM PCL
INSTR IN
t
AVWL
P2.0–P2.7 OR A8–A15 FROM DPH
A8–A15 FROM PCH
SU00213
Figure 4. External Data Memory Write Cycle
t
r
t
f
t
HIGH
V
0.8V
V
IH1
0.8V
V
V
IH1
IH1
IH1
0.8V
0.8V
t
LOW
t
CLCL
SU00214
Figure 5. External Clock Drive XTAL1
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
t
XLXL
CLOCK
t
XHQX
t
QVXH
OUTPUT DATA
0
1
2
3
4
5
6
7
WRITE TO SBUF
t
XHDX
t
SET TI
XHDV
INPUT DATA
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
SU00027
Figure 6. Shift Register Mode Timing
14
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I C, PWM, capture/compare, high I/O
87C552
2
2.4V
2.0V
0.8V
2.0V
0.8V
Test Points
0.45V
NOTE:
AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at 2.0V for a logic ‘1’ and 0.8V for a logic ‘0’.
SU00215
Figure 7. AC Testing Input/Output
Float
2.4V
2.4V
2.0V
0.8V
2.0V
0.8V
0.45V
0.45V
NOTE:
The float state is defined as the point at which a port 0 pin sinks 3.2mA or sources 400µA at the voltage test levels.
SU00216
Figure 8. AC Testing Input, Float Waveform
repeated START condition
START or repeated START condition
START condition
t
SU;STA
STOP condition
t
RD
0.7 V
CC
SDA
(INPUT/OUTPUT)
0.3 V
CC
t
BUF
t
t
t
FC
FD
RC
t
SU;STO
0.7 V
CC
SCL
(INPUT/OUTPUT)
0.3 V
CC
t
SU;DAT3
t
t
t
HIGH
t
SU;DAT1
t
t
SU;DAT2
HD;STA
LOW
HD;DAT
SU00107A
2
Figure 9. Timing SIO1 (I C) Interface
15
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I C, PWM, capture/compare, high I/O
87C552
2
50
40
30
(1)
(2)
I
mA
DD
20
10
0
(3)
(4)
(1) Maximum operating mode; V
= 6V
= 4V
DD
DD
(2) Maximum operating mode; V
NOTE:
0
4
8
12
16
(3) Maximum idle mode; V
(4) Maximum idle mode; V
= 6V
DD
DD
These values are valid only within the frequency
specifications of the device under test.
f (MHz)
= 4V
SU00217
Figure 10. 16MHz Version Supply Current (I ) as a Function of Frequency at XTAL1 (f
)
DD
OSC
V
V
DD
DD
I
DD
P1.6
P1.7
V
DD
P0
V
V
DD
DD
RST
EA
STADC
EW
(NC)
XTAL2
XTAL1
CLOCK SIGNAL
AV
SS
V
SS
AV
ref–
SU00218
Figure 11. I Test Condition, Active Mode
DD
1
All other pins are disconnected
1. Active Mode:
a. The following pins must be forced to V : EA, RST, Port 0, and EW.
DD
b. The following pins must be forced to V : STADC, AV , and AV .
ref–
SS
ss
c. Ports 1.6 and 1.7 should be connected to V through resistors of sufficiently high value such that the sink current into these pins cannot
DD
exceed the I
spec of these pins.
OL1
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
16
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I C, PWM, capture/compare, high I/O
87C552
2
V
V
DD
DD
I
DD
P1.6
P1.7
V
DD
P0
RST
V
DD
STADC
EW
EA
(NC)
XTAL2
XTAL1
CLOCK SIGNAL
AV
SS
V
SS
AV
ref–
SU00219
Figure 12. I Test Condition, Idle Mode
DD
2
All other pins are disconnected
2. Idle Mode:
a. The following pins must be forced to V : Port 0 and EW.
DD
b. The following pins must be forced to V : RST, STADC, AV ,, AV , and EA.
SS
ss
ref–
c. Ports 1.6 and 1.7 should be connected to V through resistors of sufficiently high value such that the sink current into these pins cannot
DD
exceed the I
spec of these pins. These pins must not have logic 0 written to them prior to this measurement.
OL1
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
V
–0.5
DD
0.7V
DD
0.5V
0.2V
–0.1
DD
t
CHCX
t
t
CHCL
t
CLCX
CLCH
t
CLCL
SU00220
Figure 13. Clock Signal Waveform for I Tests in Active and Idle Modes
DD
t
= t
= 5ns
CHCL
CLCH
V
V
DD
DD
I
DD
P1.6
P1.7
V
DD
V
RST
DD
STADC
P0
EW
EA
(NC)
XTAL2
XTAL1
AV
SS
V
SS
AV
ref–
SU00221
Figure 14. I Test Condition, Power Down Mode
DD
3
All other pins are disconnected. V = 2V to 5.5V
DD
3. Power Down Mode:
a. The following pins must be forced to V : Port 0 and EW.
DD
b. The following pins must be forced to V : RST, STADC, XTAL1, AV ,, AV , and EA.
SS
ss
ref–
c. Ports 1.6 and 1.7 should be connected to V through resistors of sufficiently high value such that the sink current into these pins cannot
DD
exceed the I
spec of these pins. These pins must not have logic 0 written to them prior to this measurement.
OL1
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
17
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I C, PWM, capture/compare, high I/O
87C552
2
programmed, further programming of the code memory and
encryption table is disabled. However, the other lock bit can still be
programmed.
EPROM CHARACTERISTICS
The 87C552 is programmed by using a modified Quick-Pulse
Programming algorithm. It differs from older methods in the value
used for V (programming supply voltage) and in the width and
number of the ALE/PROG pulses.
PP
Note that the EA/V pin must not be allowed to go above the
PP
maximum specified V level for any amount of time. Even a narrow
PP
glitch above that voltage can cause permanent damage to the
The 87C552 contains two signature bytes that can be read and used
by an EPROM programming system to identify the device. The
signature bytes identify the device as an 87C552 manufactured by
Philips.
device. The V source should be well regulated and free of glitches
PP
and overshoot.
Program Verification
Table 3 shows the logic levels for reading the signature byte, and for
programming the program memory, the encryption table, and the
lock bits. The circuit configuration and waveforms for quick-pulse
programming are shown in Figures 15 and 16. Figure 17 shows the
circuit configuration for normal program memory verification.
If lock bit 2 has not been programmed, the on-chip program memory
can be read out for program verification. The address of the program
memory locations to be red is applied to ports 1 and 2 as shown in
Figure 17. The other pins are held at the “Verify Code Data” levels
indicated in Table 3. The contents of the address location will be
emitted on port 0. External pull-ups are required on port 0 for this
operation.
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in
Figure 15. Note that the 87C552 is running with a 4 to 6MHz
oscillator. The reason the oscillator needs to be running is that the
device is executing internal address and program data transfers.
If the encryption table has been programmed, the data presented at
port 0 will be the exclusive NOR of the program byte with one of the
encryption bytes. The user will have to know the encryption table
contents in order to correctly decode the verification data. The
encryption table itself cannot be read out.
The address of the EPROM location to be programmed is applied to
ports 1 and 2, as shown in Figure 15. The code byte to be
programmed into that location is applied to port 0. RST, PSEN, and
pins of ports 2 and 3 specified in Table 3 are held at the “Program
Code Data” levels indicated in Table 3. The ALE/PROG is pulsed
low 25 times as shown in Figure 16.
Reading the Signature Bytes
The signature bytes are read by the same procedure as a normal
verification of locations 030H and 031H, except that P3.6 and P3.7
need to be pulled to a logic low. The values are:
To program the encryption table, repeat the 25-pulse programming
sequence for addresses 0 through 1FH, using the “Pgm Encryption
Table” levels. Do not forget that after the encryption table is
programmed, verification cycles will produce only encrypted data.
(030H) = 15H indicates manufactured by Philips Components
(031H) = 94H indicates 87C552
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 3, and
which satisfies the timing specifications, is suitable.
To program the lock bits, repeat the 25-pulse programming
sequence using the “Pgm Lock Bit” levels. After one lock bit is
Table 3. EPROM Programming Modes
MODE
RST
PSEN
ALE/PROG
EA/V
P2.7
P2.6
P3.7
P3.6
PP
Read signature
Program code data
Verify code data
Pgm encryption table
Pgm lock bit 1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
0
1
1
0
1
1
1
1
0
0
1
1
0
1
0
0*
1
V
PP
1
0*
0*
0*
V
PP
PP
PP
V
V
Pgm lock bit 2
NOTES:
1. 0 = Valid low for that pin; 1 = valid high for that pin.
2. V = 12.75V ±0.25V.
PP
3. V = 5V ±10% during programming and verification.
DD
*
ALE/PROG receives 25 programming pulses while V is held at 12.75V. Each programming pulse is low for 100µs (±10µs) and high for a
PP
minimum of 10µs.
Trademark phrase of Intel Corporation.
18
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I C, PWM, capture/compare, high I/O
87C552
2
+5V
V
DD
P0
A0-A7
PGM DATA
+12.75V
P1
1
1
1
RST
P3.6
EA/V
PP
25 100µs PULSES TO GROUND
ALE/PROG
PSEN
0
1
87C552
P3.7
XTAL2
P2.7
0
P2.6
4-6MHz
XTAL1
A8-A12
P2.0-P2.4
V
SS
SU00222
Figure 15. Programming Configuration
25 PULSES
1
0
ALE/PROG:
ALE/PROG:
10µs MIN
100µs+10
1
0
SU00018
Figure 16. PROG Waveform
+5V
V
DD
P0
A0-A7
PGM DATA
P1
1
1
1
RST
P3.6
1
1
EA/V
PP
ALE/PROG
PSEN
0
87C552
P3.7
0 ENABLE
XTAL2
P2.7
0
P2.6
4-6MHz
XTAL1
A8-A12
P2.0-P2.4
V
SS
SU00223
Figure 17. Program Verification
19
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I C, PWM, capture/compare, high I/O
87C552
2
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
T
amb
= 21°C to +27°C, V = 5V±10%, V = 0V
DD SS
SYMBOL
PARAMETER
MIN
MAX
13.0
50
UNIT
V
V
PP
Programming supply voltage
Programming supply current
Oscillator frequency
12.5
I
PP
mA
MHz
1/t
CLCL
4
6
t
t
t
t
t
t
t
t
t
t
t
t
Address setup to PROG low
Address hold after PROG
Data setup to PROG low
Data hold after PROG
48t
AVGL
CLCL
CLCL
CLCL
CLCL
CLCL
48t
48t
48t
48t
GHAX
DVGL
GHDX
EHSH
SHGL
GHSL
GLGH
AVQV
ELQZ
EHQZ
GHGL
P2.7 (ENABLE) high to V
PP
V
setup to PROG low
hold after PROG
10
10
90
µs
µs
µs
PP
PP
V
PROG width
110
Address to data valid
48t
CLCL
CLCL
CLCL
ENABLE low to data valid
Data float after ENABLE
PROG high to PROG low
48t
48t
0
10
µs
PROGRAMMING*
ADDRESS
VERIFICATION*
ADDRESS
P1.0–P1.7
P2.0–P2.4
t
AVQV
PORT 0
DATA IN
DATA OUT
t
t
t
DVGL
GHDX
GHAX
t
AVGL
ALE/PROG
t
t
GLGH
GHGL
t
t
SHGL
GHSL
LOGIC 1
LOGIC 1
EA/V
PP
LOGIC 0
t
t
t
EHSH
ELQV
EHQZ
P2.7
ENABLE
SU00020
*
FOR PROGRAMMING VERIFICATION SEE FIGURE 17.
FOR VERIFICATION CONDITIONS SEE TABLE 3.
Figure 18. EPROM Programming and Verification
2
2
Purchase of Philips I C components conveys a license under the Philips’ I C patent
2
to use the components in the I C system provided the system conforms to the
I C specifications defined by Philips. This specification can be ordered using the
2
code 9398 393 40011.
20
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
PLCC68: plastic leaded chip carrier; 68 leads; pedestal
SOT188-3
21
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT318-2
22
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
NOTES
23
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 05-98
Document order number:
9397 750 05367
Philips
Semiconductors
相关型号：
87C554
80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
NXP
87C575
80C51 8-bit microcontroller family 8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
NXP
87C576
80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer
NXP
87C58
80C51 8-bit microcontroller family 8K.64K/256.1K OTP/ROM/ROMless, low voltage 2.7V.5.5V, low power, high speed 33 MHz
NXP
87C58X2
80C51 8-bit microcontroller family 4K/8K/16K/32K ROM/OTP 128B/256B RAM low voltage 2.7 to 5.5 V, low power, high speed 30/33 MHz
NXP
©2020 ICPDF网 联系我们和版权申明