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87C652 [NXP]

80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C; 80C51的8位微控制器8K / 16K ， 256 OTP ， I2C
87C652
型号： 87C652
厂家： NXP    NXP
描述：

80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C
80C51的8位微控制器8K / 16K ， 256 OTP ， I2C

微控制器
文件： 总24页 (文件大小：195K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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INTEGRATED CIRCUITS  
87C652/87C654  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
Product specification  
Replaces data sheets 87C652 of 1998 May 01 and 87C654 of 1998 May 01  
IC20 Data Handbook  
1999 Jul 23  
Philips  
Semiconductors  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
DESCRIPTION  
PIN CONFIGURATIONS  
The 87C652/87C654 single-chip 8-Bit  
microcontroller is manufactured in an  
advanced CMOS process and is a derivative  
of the 80C51 microcontroller family. The  
87C652/87C654 has the same instruction  
set as the 80C51. Three versions of the  
derivative exist:  
40  
V
CC  
P1.0  
P1.1  
P1.2  
1
2
3
39 P0.0/AD0  
38 P0.1/AD1  
37  
P1.3  
P1.4  
4
5
P0.2/AD2  
36 P0.3/AD3  
35  
P0.4/AD4  
80C652—ROMless  
83C652/83C654—8 Kbyte, 16 Kbyte ROM  
87C652/87C654—8 Kbyte, 16 Kbyte OTP  
P1.5  
SCL/P1.6  
SDA/P1.7  
RST  
6
7
8
9
FEATURES  
• 80C51 central processing unit  
34 P0.5/AD5  
33 P0.6/AD6  
32 P0.7/AD7  
The ROMless and ROM are in separate  
datasheets.  
• 16k × 8 EPROM or 8k x 8 EPROM  
expandable externally to 64k bytes  
PLASTIC  
DUAL  
IN-LINE  
This device provides architectural  
31 EA/V  
PP  
RxD/P3.0 10  
TxD/P3.1 11  
INT0/P3.2 12  
enhancements that make it applicable in a  
variety of applications for general control  
systems. The 87C654 contains a non-volatile  
16k × 8 EPROM and the 87C652 contains an  
8k x 8 EPROM. Both have a volatile 256 × 8  
read/write data memory, four 8-bit I/O ports,  
two 16-bit timer/event counters (identical to  
the timers of the 80C51), a multi-source,  
two-priority-level, nested interrupt structure,  
• 256 × 8 RAM, expandable externally to  
PACKAGE  
30 ALE/PROG  
29 PSEN  
64k bytes  
• Two standard 16-bit timer/counters  
• Four 8-bit I/O ports  
13  
28  
INT1/P3.3  
P2.7/A15  
27 P2.6/A14  
26 P2.5/A13  
25 P2.4/A12  
T0/P3.4 14  
T1/P3.5 15  
WR/P3.6 16  
RD/P3.7 17  
XTAL2 18  
XTAL1 19  
2
• I C-bus serial I/O port with byte oriented  
master and slave functions  
• Full-duplex UART facilities  
2
an I C interface, UART and on-chip oscillator  
24  
P2.3/A11  
23 P2.2/A10  
22  
and timing circuits. For systems that require  
extra capability, the 87C652/87C654 can be  
expanded using standard TTL compatible  
memories and logic.  
• Power control modes  
– Idle mode  
P2.1/A9  
21 P2.0/A8  
– Power-down mode  
V
20  
SS  
• Extended temperature range  
• OTP package available  
The device also functions as an arithmetic  
processor having facilities for both binary and  
BCD arithmetic plus bit-handling capabilities.  
The instruction set consists of over 100  
instructions: 49 one-byte, 45 two-byte and 17  
three-byte. With a 16 MHz crystal, 58% of the  
instructions are executed in 0.75 µs and 40%  
in 1.5 µs. Multiply and divide instructions  
require 3 µs.  
SU00259  
• Two speed ranges  
– 16 MHz  
– 20 MHz  
ORDERING INFORMATION  
FREQ  
MHz  
Drawing  
Number  
EPROM  
TEMPERATURE RANGE °C AND PACKAGE  
S87C654-4N40  
S87C654-4A44  
S87C654–4B44  
S87C654-5N40  
S87C654-5A44  
S87C654-5B44  
S87C654–7N40  
S87C654–7A44  
S87C652-4N40  
S87C652-4A44  
S87C652-4B44  
S87C652-5A44  
NOTES:  
0 to +70, Plastic Dual In-line Package  
0 to +70, Plastic Leaded Chip Carrier  
0 to +70, Plastic Quad Flat Pack  
16  
16  
16  
16  
16  
16  
20  
20  
16  
16  
16  
16  
SOT129-1  
SOT187-2  
SOT307-2  
SOT129-1  
SOT187-2  
SOT307-2  
SOT129-1  
SOT187-2  
SOT129-1  
SOT187-2  
SOT307-2  
SOT187-2  
–40 to +85, Plastic Dual In-line Package  
–40 to +85, Plastic Leaded Chip Carrier  
–40 to +85, Plastic Quad Flat Pack  
0 to +70, Plastic Dual In-line Package  
0 to +70, Plastic Leaded Chip Carrier  
0 to +70, Plastic Dual In-line Package  
0 to +70, Plastic Leaded Chip Carrier  
0 to +70, Plastic Quad Flat Pack  
–40 to +85, Plastic Leaded Chip Carrier  
1. For ROM see 83C654 data sheet and 83C652/80C652 data sheet  
2
1999 Jul 23  
853-1689 22042  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
BLOCK DIAGRAM  
FREQUENCY  
REFERENCE  
COUNTERS  
T0 T1  
XTAL2  
XTAL1  
OSCILLATOR  
PROGRAM  
MEMORY  
(16K x 8  
DATA  
TWO 16-BIT  
TIMER/EVENT  
COUNTERS  
AND  
MEMORY  
TIMING  
(256 x 8 RAM)  
EPROM)  
SDA  
SHARED  
2
I C SERIAL I/O  
CPU  
WITH  
PORT 1  
SCL  
INTERNAL  
INTERRUPTS  
64K BYTE BUS  
EXPANSION  
CONTRTOL  
PROG SERIAL PORT  
FULL DUPLEX UART  
SYNCHRONOUS SHIFT  
PROGRAMMABLE I/O  
SERIAL IN  
SERIAL OUT  
INT0  
INT1  
CONTROL  
PARALLEL PORTS,  
ADDRESS/DATA BUS  
AND I/O PINS  
SHARED WITH  
PORT 3  
EXTERNAL  
INTERRUPTS  
SU00271  
LOGIC SYMBOL  
V
V
CC SS  
RST  
XTAL1  
XTAL2  
V
/EA  
PP  
PSEN  
PROG/ALE  
SCL  
SDA  
RxD  
TxD  
INT0  
INT1  
T0  
T1  
WR  
RD  
SU00262  
3
1999 Jul 23  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
PLASTIC LEADED CHIP  
CARRIER PIN FUNCTIONS  
PLASTIC QUAD FLAT PACK  
PIN FUNCTIONS  
44  
34  
6
1
40  
7
39  
1
33  
23  
LCC  
PQFP  
11  
17  
29  
18  
28  
12  
22  
Pin  
1
Function  
NC*  
Pin  
Function  
NC*  
Pin  
1
Function  
P1.5  
Pin  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
Function  
P2.5/A13  
P2.6/A14  
P2.7/A15  
PSEN  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
2
P1.0  
P2.0/A8  
P2.1/A9  
P2.2/A10  
P2.3/A11  
P2.4/A12  
P2.5/A13  
P2.6/A14  
P2.7/A15  
PSEN  
2
P1.6/SCL  
P1.7/SDA  
RST  
3
P1.1  
3
4
P1.2  
4
5
P1.3  
5
P3.0/RxD  
NC*  
ALE/PROG  
NC*  
6
P1.4  
6
7
P1.5  
7
P3.1/TxD  
P3.2/INT0  
P3.3/INT1  
P3.4/T0  
P3.5/T1  
P3.6/WR  
P3.7/RD  
XTAL2  
EA/V  
PP  
8
P1.6/SCL  
P1.7/SDA  
RST  
8
P0.7/AD7  
P0.6/AD6  
P0.5/AD5  
P0.4/AD4  
P0.3/AD3  
P0.2/AD2  
P0.1/AD1  
P0.0/AD0  
9
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
P3.0/RxD  
NC*  
ALE/PROG  
NC*  
P3.1/TxD  
P3.2/INT0  
P3.3/INT1  
P3.4/T0  
P3.5/T1  
P3.6/WR  
P3.7/RD  
XTAL2  
XTAL1  
EA/V  
PP  
P0.7/AD7  
P0.6/AD6  
P0.5/AD5  
P0.4/AD4  
P0.3/AD3  
P0.2/AD2  
P0.1/AD1  
P0.0/AD0  
XTAL1  
V
V
CC  
SS  
NC*  
NC*  
P1.0  
P1.1  
P1.2  
P.13  
P1.4  
P2.0/A8  
P2.1/A9  
P2.2/A10  
P2.3/A11  
P2.4/A12  
V
V
CC  
SS  
SU00261  
* NO INTERNAL CONNECTION  
SU00260  
* NO INTERNAL CONNECTION  
4
1999 Jul 23  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
PIN DESCRIPTIONS  
PIN NUMBER  
MNEMONIC DIP  
LCC  
22  
QFP  
16  
TYPE NAME AND FUNCTION  
V
SS  
V
CC  
20  
40  
I
I
Ground: 0 V reference.  
44  
38  
Power Supply: This is the power supply voltage for normal, idle, and power-down operation.  
P0.0–0.7  
39–32 43–36 37–30  
I/O  
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them  
float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order  
address and data bus during accesses to external program and data memory. In this  
application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code  
bytes during program verification in the 87C654. External pull-ups are required during  
program verification.  
P1.0–P1.7  
1–8  
2–9  
40–44,  
1–3  
I/O  
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7  
which are open drain. Port 1 pins that have 1s written to them are pulled high by the internal  
pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will  
source current because of the internal pull-ups. (See DC Electrical Characteristics: I ).  
IL  
Port 1 also receives the low-order address byte during program memory verification.  
Alternate functions include:  
2
P1.6  
P1.7  
7
8
8
9
2
3
I/O  
I/O  
SCL: I C-bus serial port clock line.  
2
SDA: I C-bus serial port data line.  
P2.0–P2.7  
21–28 24–31 18–25  
I/O  
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s  
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,  
port 2 pins that are externally being pulled low will source current because of the internal  
pull-ups. (See DC Electrical Characteristics: I ). Port 2 emits the high-order address byte  
IL  
during fetches from external program memory and during accesses to external data memory  
that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal  
pull-ups when emitting 1s. During accesses to external data memory that use 8-bit  
addresses (MOV @Ri), port 2 emits the contents of the P2 special function register.  
P3.0–P3.7  
10–17  
11,  
5,  
I/O  
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s  
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,  
port 3 pins that are externally being pulled low will source current because of the pull-ups.  
13–19 7–13  
(See DC Electrical Characteristics: I ). Port 3 also serves the special features of the 80C51  
IL  
family, as listed below:  
10  
11  
12  
13  
14  
15  
16  
17  
11  
13  
14  
15  
16  
17  
18  
19  
5
7
8
I
O
I
I
I
I
O
O
RxD (P3.0): Serial input port  
TxD (P3.1): Serial output port  
INT0 (P3.2): External interrupt  
INT1 (P3.3): External interrupt  
T0 (P3.4): Timer 0 external input  
T1 (P3.5): Timer 1 external input  
WR (P3.6): External data memory write strobe  
RD (P3.7): External data memory read strobe  
9
10  
11  
12  
13  
RST  
9
10  
4
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the  
device. An internal diffused resistor to V permits a power-on reset using only an external  
SS  
capacitor to V  
.
CC  
ALE/PROG  
30  
33  
27  
I/O  
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the  
address during an access to external memory. In normal operation, ALE is emitted at a  
constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking.  
Note that one ALE pulse is skipped during each access to external data memory. This pin is  
also the program pulse input (PROG) during EPROM programming.  
PSEN  
29  
31  
32  
35  
26  
29  
O
I
Program Store Enable: The read strobe to external program memory. When the 87C654 is  
executing code from the external program memory, PSEN is activated twice each machine  
cycle, except that two PSEN activations are skipped during each access to external data  
memory. PSEN is not activated during fetches from internal program memory.  
EA/V  
External Access Enable/Programming Supply Voltage: EA must be externally held low to  
enable the device to fetch code from external program memory locations 0000H and 1FFFH  
for 87C652 and 3FFFH for 87C654. If EA is held high, the device executes from internal  
program memory unless the program counter contains an address greater than 3FFFH. This  
PP  
pin also receives the 12.75 V programming supply voltage (V ) during EPROM programming.  
PP  
XTAL1  
19  
18  
21  
20  
15  
14  
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator  
circuits.  
XTAL2  
O
Crystal 2: Output from the inverting oscillator amplifier.  
NOTE:  
To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V + 0.5 V or V – 0.5 V, respectively.  
CC  
SS  
5
1999 Jul 23  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
Table 1.  
8XC652/654 Special Function Registers  
DIRECT  
ADDRESS MSB  
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION  
RESET  
VALUE  
SYMBOL  
DESCRIPTION  
LSB  
E0  
ACC*  
B*  
Accumulator  
B register  
E0H  
F0H  
E7  
F7  
E6  
F6  
E5  
F5  
E4  
F4  
E3  
F3  
E2  
F2  
E1  
F1  
00H  
F0  
00H  
DPTR:  
Data pointer  
(2 bytes)  
DPH  
DPL  
Data pointer high  
Data pointer low  
83H  
82H  
00H  
00H  
AF  
EA  
AE  
BE  
AD  
ES1  
BD  
AC  
ES0  
BC  
AB  
ET1  
BB  
AA  
EX1  
BA  
A9  
ET0  
B9  
A8  
EX0  
B8  
IE*#  
IP*#  
P0*  
Interrupt enable  
Interrupt priority  
Port 0  
A8H  
B8H  
80H  
90H  
A0H  
0x000000B  
xx000000B  
FFH  
BF  
–
PS1  
85  
PS0  
84  
PT1  
83  
PX1  
82  
PT0  
81  
PX0  
80  
87  
86  
AD6  
96  
AD7  
97  
AD5  
95  
AD4  
94  
AD3  
93  
AD2  
92  
AD1  
91  
AD0  
90  
P1*#  
P2*  
Port 1  
SDA  
A7  
SCL  
A6  
FFH  
A5  
A13  
B5  
A4  
A12  
B4  
A3  
A11  
B3  
A2  
A10  
B2  
A1  
A9  
A0  
A8  
Port 2  
A15  
B7  
A14  
B6  
FFH  
B1  
B0  
P3*  
Port 3  
B0H  
87H  
RD  
SMOD  
9F  
WR  
–
T1  
T0  
INT1  
GF1  
9B  
INT0  
GF0  
9A  
TXD  
PD  
99  
RXD  
IDL  
98  
FFH  
PCON#  
Power control  
–
–
0xxx0000B  
9E  
9D  
SM2  
9C  
REN  
S0CON*# Serial 0 port control  
98H  
99H  
SM0  
SM1  
TB8  
RB8  
TI  
RI  
00H  
S0BUF#  
Serial 0 data buffer  
xxxxxxxxB  
D7  
CY  
D6  
AC  
D5  
F0  
D4  
D3  
D2  
D1  
F1  
D0  
P
PSW*  
S1DAT#  
SP  
Program status word  
Serial 1 data  
D0H  
DAH  
81H  
RS1  
RS0  
OV  
00H  
00H  
07H  
00H  
Stack pointer  
S1ADR#  
Serial 1 address  
DBH  
GC  
SLAVE ADDRESS  
S1STA#  
Serial 1 status  
D9H  
D8H  
SC4  
DF  
SC3  
DE  
SC2  
DD  
SC1  
DC  
SC0  
0
0
0
F8H  
DB  
SI  
DA  
AA  
8A  
IT1  
D9  
D8  
S1CON*# Serial 1 control  
CR2  
8F  
ENS1  
8E  
STA  
8D  
STO  
8C  
CR1  
89  
CR0  
88  
00000000B  
8B  
IE1  
TCON*  
TH1  
Timer control  
Timer high 1  
Timer high 0  
Timer low 1  
Timer low 0  
Timer mode  
88H  
8DH  
8CH  
8BH  
8AH  
89H  
TF1  
TR1  
TF0  
TR0  
IE0  
IT0  
00H  
00H  
00H  
00H  
00H  
00H  
TH0  
TL1  
TL0  
TMOD  
GATE  
C/T  
M1  
M0  
GATE  
C/T  
M1  
M0  
*
#
SFRs are bit addressable.  
SFRs are modified from or added to the 80C51 SFRs.  
6
1999 Jul 23  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
milliseconds) plus two machine cycles. At  
power-down is the last instruction executed.  
Only the contents of the on-chip RAM are  
preserved. A hardware reset is the only way  
to terminate the power-down mode. The  
control bits for the reduced power modes are  
in the special function register PCON. Table 2  
shows the state of the I/O ports during low  
current operating modes.  
OSCILLATOR  
CHARACTERISTICS  
XTAL1 and XTAL2 are the input and output,  
respectively, of an inverting amplifier. The  
pins can be configured for use as an on-chip  
oscillator, as shown in the Logic Symbol.  
power-on, the voltage on V and RST must  
CC  
come up at the same time for a proper  
start-up.  
Idle Mode  
In the idle mode, the CPU puts itself to sleep  
while all of the on-chip peripherals stay  
active. The instruction to invoke the idle  
mode is the last instruction executed in the  
normal operating mode before the idle mode  
is activated. The CPU contents, the on-chip  
RAM, and all of the special function registers  
remain intact during this mode. The idle  
mode can be terminated either by any  
enabled interrupt (at which time the process  
is picked up at the interrupt service routine  
and continued), or by a hardware reset which  
starts the processor in the same manner as a  
power-on reset.  
To drive the device from an external clock  
source, XTAL1 should be driven while XTAL2  
is left unconnected. There are no  
requirements on the duty cycle of the  
external clock signal, because the input to  
the internal clock circuitry is through a  
divide-by-two flip-flop. However, minimum  
and maximum high and low times specified in  
the data sheet must be observed.  
2
I C SERIAL  
COMMUNICATION—SIO1  
2
2
The I C serial port is identical to the I C  
serial port on the 8XC552. The operation of  
this subsystem is described in detail in the  
8XC552 section of this manual.  
Reset  
Note that in both the 8XC652/4 and the  
2
A reset is accomplished by holding the RST  
8XC552 the I C pins are alternate functions  
pin high for at least two machine cycles (24  
oscillator periods), while the oscillator is  
running. To insure a good power-on reset, the  
RST pin must be high long enough to allow  
the oscillator time to start up (normally a few  
to port pins P1.6 and P1.7. Because of this,  
P1.6 and P1.7 on these parts do not have a  
pull-up structure as found on the 80C51.  
Therefore P1.6 and P1.7 have open drain  
outputs on the 8XC652/4.  
Power-Down Mode  
In the power-down mode, the oscillator is  
stopped and the instruction to invoke  
Table 2. External Pin Status During Idle and Power-Down Mode  
PROGRAM  
MEMORY  
MODE  
ALE  
PSEN  
PORT 0  
PORT 1  
PORT 2  
PORT 3  
Idle  
Idle  
Internal  
1
1
0
0
1
1
0
0
Data  
Float  
Data  
Float  
Data  
Data  
Data  
Data  
Data  
Address  
Data  
Data  
Data  
Data  
Data  
External  
Internal  
Power-down  
Power-down  
External  
Data  
Serial Control Register (S1CON) – See Table 3  
S1CON (D8H)  
CR2  
ENS1  
STA  
STO  
SI  
AA  
CR1  
CR0  
Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.  
Table 3. Serial Clock Rates  
BIT FREQUENCY (kHz) AT fOSC  
6 MHZ  
12 MHz  
16 MHz  
20 MHz  
f
DIVIDED BY  
CR2  
CR1  
CR0  
OSC  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
23  
27  
31.25  
37  
6.25  
50  
100  
47  
54  
62.5  
75  
12.5  
100  
200  
62.5  
71  
83.3  
100  
17  
78  
89  
104  
125  
21  
166  
334  
256  
224  
192  
160  
960  
120  
60  
1
1
1
1
1
133  
1
1
1
267  
0.25 < 62.5  
0 to 255  
0.5 < 62.5  
0 to 254  
0.65 < 55.6  
0 to 253  
0.81 < 69.4  
0 to 253  
96 × (256 – (reload value Timer 1))  
(Reload value range: 0 – 254 in mode 2)  
NOTE:  
2
2
1. These frequencies exceed the upper limit of 100kHz of the I C-bus specification and cannot be used in an I C-bus application.  
7
1999 Jul 23  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
1, 2, 3  
ABSOLUTE MAXIMUM RATINGS  
PARAMETER  
RATING  
–65 to +150  
–0.5 to + 13  
–0.5 to + 6.5  
±5  
UNIT  
°C  
V
Storage temperature range  
Voltage on EA/V to V  
PP  
SS  
Voltage on any other pin to V  
V
SS  
Input, output current on any single pin  
mA  
W
Power dissipation (based on package heat transfer  
limitations, not device power consumption)  
1
NOTES:  
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent  
damage to the device. This is a stress rating only and functional operation of the device at  
these or any conditions other than those described in the AC and DC Electrical  
Characteristics section of this specification is not implied.  
2. This product includes circuitry specifically designed for the protection of its internal devices  
from the damaging effects of excessive static charge. Nonetheless, it is suggested that  
conventional precautions be taken to avoid applying greater than the rated maxima.  
3. Parameters are valid over operating temperature range unless otherwise specified. All  
voltages are with respect to V unless otherwise noted.  
SS  
DEVICE SPECIFICATIONS  
SUPPLY VOLTAGE  
(V)  
FREQUENCY  
(MHz)  
TEMPERATURE  
RANGE  
TYPE  
MIN.  
MAX.  
MIN.  
MAX.  
(°C)  
S87C652-4 and  
S87C654-4  
4.5  
5.5  
3.5  
16  
0 to +70  
S87C652-5 and  
S87C654-5  
4.5  
4.5  
5.5  
5.5  
3.5  
3.5  
16  
20  
–40 to +85  
0 to +70  
S87C654–7  
8
1999 Jul 23  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
DC ELECTRICAL CHARACTERISTICS  
V
SS  
= 0 V  
TEST  
LIMITS  
SYMBOL  
PARAMETER  
Input low voltage,  
PART TYPE  
CONDITIONS  
MIN.  
MAX.  
0.2V –0.1  
UNIT  
V
IL  
0 to +70°C  
–40 to +85°C  
–0.5  
–0.5  
V
V
CC  
except EA, P1.6/SCL, P1.7/SDA  
0.2V –0.15  
CC  
V
IL1  
Input low voltage to EA  
0 to +70°C  
–40 to +85°C  
–0.5  
–0.5  
0.2V –0.3  
V
V
CC  
0.2V –0.35  
CC  
1
V
V
Input low voltage to P1.6/SCL, P1.7/SDA  
–0.5  
0.3V  
V
IL2  
CC  
Input high voltage,  
0 to +70°C  
–40 to +85°C  
0.2V +0.9  
V
CC  
V
CC  
+0.5  
+0.5  
V
V
IH  
CC  
except XTAL1, RST, P1.6/SCL, P1.7/SDA  
Input high voltage, XTAL1, RST  
0.2V +1.0  
CC  
V
IH1  
0 to +70°C  
–40 to +85°C  
0.7V  
V
CC  
V
CC  
+0.5  
+0.5  
V
V
CC  
0.7V +0.1  
CC  
1
V
V
Input high voltage, P1.6/SCL, P1.7/SDA  
0.7V  
6.0  
V
V
IH2  
CC  
2, 3  
Output low voltage, ports 1, 2, 3,  
except P1.6/SCL, P1.7/SDA  
I
I
= 1.6mA  
0.45  
OL  
OL  
2, 3  
V
OL1  
V
OL2  
V
OH  
Output low voltage, port 0, ALE, PSEN  
Output low voltage, P1.6/SCL, P1.7/SDA  
Output high voltage, ports 1, 2, 3  
= 3.2mA  
0.45  
0.4  
V
V
OL  
I
= 3.0mA  
OL  
0 to +70°C  
–40 to +85°C  
I
I
= –60µA  
= –25µA  
2.4  
0.75V  
V
V
OH  
OH  
CC  
V
OH1  
Output high voltage; port 0 in external bus mode,  
ALE, PSEN, RST  
0 to +70°C  
–40 to +85°C  
I
I
= –400µA  
= –150µA  
2.4  
0.75V  
V
V
OH  
OH  
4
CC  
I
IL  
Logical 0 input current, ports 1, 2, 3, 4,  
except P1.6/SCL, P1.7/SDA  
0 to +70°C  
–40 to +85°C  
V
IN  
= 0.45V  
–50  
–75  
µA  
µA  
I
Logical 1-to-0 transition current, ports 1, 2, 3,  
except P1.6/SCL, P1.7/SDA  
0 to +70°C  
–40 to +85°C  
See note 5  
0.45V < V < V  
CC  
–650  
–750  
µA  
µA  
TL  
I
I
Input leakage current, port 0  
±10  
±10  
µA  
L1  
I
Input leakage current, P1.6/SCL, P1.7/SDA  
0V < V < 6.0V  
µA  
µA  
L2  
I
0V < V < 6.0V  
CC  
I
Power supply current:  
See note 6  
CC  
V
CC  
=6.0V  
7
Active mode @ 16 MHz  
Idle mode @ 16 MHz  
25  
6
50  
135  
mA  
mA  
µA  
8
9, 10  
Power down mode  
0 to +70°C  
–40 to +85°C  
9, 10  
Power down mode  
µA  
R
C
Internal reset pull-down resistor  
Pin capacitance  
50  
150  
10  
kΩ  
RST  
IO  
Freq.=1 MHz  
pF  
NOTES:  
2
1. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I C specification, so an input voltage below 0.3V will be recognized as a  
CC  
logic 0 while an input voltage above 0.7V will be recognized as a logic 1.  
CC  
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due  
OL  
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the  
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify  
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no  
OL  
single output sinks more than 5 mA and no more than two outputs exceed the test conditions.  
3. Under steady state (non-transient) conditions, I must be externally limited as follows: Maximum I = 10 mA per port pin; Maximum  
OL  
OL  
I
OL  
= 26 mA total for Port 0; Maximum I = 15 mA total for Ports 1, 2, and 3; Maximum I = 71 mA total for all output pins. If I exceeds  
OL OL OL  
the test conditions, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.  
OL  
4. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the 0.9V specification when the  
OH  
CC  
address bits are stabilizing.  
5. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its  
maximum value when V is approximately 2 V.  
IN  
6. See Figures 9 through 11 for I test conditions.  
CC  
7. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 10ns;  
r
f
V
IL  
= V + 0.5 V; V = V –0.5 V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = V ; f  
= 16 MHz. See Figure 9.  
SS  
IH  
CC  
CC CLK  
8. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 10 ns; V = V + 0.5 V;  
r
f
IL  
SS  
V
IH  
= V –0.5 V; XTAL2 not connected; Port 0 = P1.6 = P1.7 = V ; EA = RST = V ; f  
= 16 MHz. See Figure 10.  
CC  
CC  
SS CLK  
9. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = V  
;
CC  
EA = RST = V . See Figure 11.  
SS  
10.2V ≤ V ≤ V max.  
PD  
CC  
9
1999 Jul 23  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
1, 2  
AC ELECTRICAL CHARACTERISTICS  
16 MHz CLOCK  
VARIABLE CLOCK  
SYMBOL  
1/t  
FIGURE  
PARAMETER  
MIN  
MAX  
MIN  
MAX  
UNIT  
2
Oscillator frequency Speed Versions  
3.5  
16  
MHz  
CLCL  
87C654  
–4, –5  
t
t
t
t
t
t
t
t
t
t
t
2
2
2
2
2
2
2
2
2
2
2
ALE pulse width  
Address valid to ALE low  
85  
8
2t  
–40  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
LHLL  
CLCL  
t
–55  
AVLL  
LLAX  
LLIV  
CLCL  
CLCL  
Address hold after ALE low  
ALE low to valid instruction in  
ALE low to PSEN low  
28  
t
–35  
150  
83  
4t  
3t  
–100  
CLCL  
23  
t
–40  
LLPL  
PLPH  
PLIV  
PXIX  
PXIZ  
AVIV  
PLAZ  
CLCL  
PSEN pulse width  
143  
3t  
CLCL  
–45  
PSEN low to valid instruction in  
Input instruction hold after PSEN  
Input instruction float after PSEN  
Address to valid instruction in  
PSEN low to address float  
–105  
CLCL  
0
0
38  
208  
10  
t
–25  
CLCL  
5t  
CLCL  
–105  
10  
Data Memory  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
Address valid to ALE low  
RD pulse width  
28  
t
6t  
6t  
–35  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
AVLL  
CLCL  
CLCL  
CLCL  
275  
275  
–100  
–100  
RLRH  
WLWH  
RLDV  
RHDX  
RHDZ  
LLDV  
AVDV  
LLWL  
AVWL  
QVWX  
DW  
WR pulse width  
RD low to valid data in  
Data hold after RD  
148  
5t  
–165  
CLCL  
0
0
Data float after RD  
55  
2t  
–70  
CLCL  
ALE low to valid data in  
Address to valid data in  
ALE low to RD or WR low  
Address valid to WR low or RD low  
Data valid to WR transition  
Data setup time before WR  
Data hold after WR  
350  
398  
238  
8t  
CLCL  
9t  
CLCL  
–150  
–165  
138  
120  
3
3t  
–50  
3t  
+50  
CLCL  
CLCL  
4t  
–130  
–60  
CLCL  
CLCL  
CLCL  
CLCL  
t
288  
13  
7t  
t
–150  
–50  
WHQX  
RLAZ  
WHLH  
RD low to address float  
RD or WR high to ALE high  
0
0
23  
103  
t
–40  
t
+40  
CLCL  
CLCL  
Shift Register  
3
t
t
t
t
t
5
5
5
5
5
Serial port clock cycle time  
0.75  
492  
80  
12t  
µs  
ns  
ns  
ns  
ns  
XLXL  
CLCL  
3
Output data setup to clock rising edge  
10t  
–133  
QVXH  
XHQX  
XHDX  
XHDV  
CLCL  
3
Output data hold after clock rising edge  
2t  
CLCL  
–117  
3
Input data hold after clock rising edge  
0
0
3
Clock rising edge to input data valid  
492  
10t  
–133  
CLCL  
External Clock  
3
t
t
t
t
6
6
6
6
High time  
20  
20  
20  
20  
t
t
ns  
ns  
ns  
ns  
CHCX  
CLCX  
CLCH  
CHCL  
CLCL – LOW  
3
Low time  
t
t
CLCL – HIGH  
3
Rise time  
20  
20  
20  
3
Fall time  
20  
NOTES:  
1. Parameters are valid over operating temperature range unless otherwise specified.  
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.  
3. These values are characterized but not 100% production tested.  
10  
1999 Jul 23  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
1, 2  
AC ELECTRICAL CHARACTERISTICS  
20 MHz CLOCK  
VARIABLE CLOCK  
SYMBOL  
1/t  
FIGURE  
PARAMETER  
MIN  
MAX  
MIN  
MAX  
UNIT  
2
Oscillator frequency: Speed Versions  
3.5  
20  
MHz  
CLCL  
87C654  
–7, –8  
t
t
t
t
t
t
t
t
t
t
t
2
2
2
2
2
2
2
2
2
2
2
ALE pulse width  
Address valid to ALE low  
60  
25  
25  
2t  
–40  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
LHLL  
CLCL  
t
–25  
AVLL  
LLAX  
LLIV  
CLCL  
CLCL  
Address hold after ALE low  
ALE low to valid instruction in  
ALE low to PSEN low  
t
–25  
135  
90  
4t  
3t  
–65  
CLCL  
25  
t
–25  
LLPL  
PLPH  
PLIV  
PXIX  
PXIZ  
AVIV  
PLAZ  
CLCL  
PSEN pulse width  
105  
3t  
CLCL  
–45  
PSEN low to valid instruction in  
Input instruction hold after PSEN  
Input instruction float after PSEN  
Address to valid instruction in  
PSEN low to address float  
–60  
CLCL  
0
0
25  
170  
10  
t
–25  
CLCL  
5t  
CLCL  
–80  
10  
Data Memory  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
3, 4  
Address valid to ALE low  
RD pulse width  
25  
t
6t  
6t  
–25  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
AVLL  
CLCL  
CLCL  
CLCL  
200  
200  
–100  
–100  
RLRH  
WLWH  
RLDV  
RHDX  
RHDZ  
LLDV  
AVDV  
LLWL  
AVWL  
QVWX  
DW  
WR pulse width  
RD low to valid data in  
Data hold after RD  
160  
5t  
2t  
–90  
–28  
CLCL  
0
0
Data float after RD  
72  
CLCL  
ALE low to valid data in  
Address to valid data in  
ALE low to RD or WR low  
Address valid to WR low or RD low  
Data valid to WR transition  
Data setup time before WR  
Data hold after WR  
250  
285  
200  
8t  
–150  
–165  
CLCL  
CLCL  
9t  
100  
125  
20  
3t  
–50  
–75  
3t  
CLCL  
+50  
CLCL  
4t  
CLCL  
t
CLCL  
7t  
CLCL  
t
CLCL  
–30  
220  
25  
–130  
–25  
WHQX  
RLAZ  
WHLH  
RD low to address float  
RD or WR high to ALE high  
0
0
25  
75  
t
–25  
t
+25  
CLCL  
CLCL  
Shift Register  
3
t
t
t
t
t
5
5
5
5
5
Serial port clock cycle time  
0.6  
367  
40  
0
12t  
µs  
ns  
ns  
ns  
ns  
XLXL  
CLCL  
3
Output data setup to clock rising edge  
10t  
–133  
–60  
QVXH  
XHQX  
XHDX  
XHDV  
CLCL  
3
Output data hold after clock rising edge  
2t  
CLCL  
3
Input data hold after clock rising edge  
0
3
Clock rising edge to input data valid  
367  
10t  
–133  
CLCL  
External Clock  
3
t
t
t
t
6
6
6
6
High time  
17  
17  
17  
17  
t
t
ns  
ns  
ns  
ns  
CHCX  
CLCX  
CLCH  
CHCL  
CLCL – LOW  
3
Low time  
t
t
CLCL – HIGH  
3
Rise time  
20  
20  
20  
3
Fall time  
20  
NOTES:  
1. Parameters are valid over operating temperature range unless otherwise specified.  
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.  
3. These values are characterized but not 100% production tested.  
11  
1999 Jul 23  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
2
AC ELECTRICAL CHARACTERISTICS – I C INTERFACE  
SYMBOL  
PARAMETER  
INPUT  
OUTPUT  
SCL TIMING CHARACTERISTICS  
1
t
t
t
t
t
; STA START condition hold time  
≥ 14 t  
> 4.0 µs  
HD  
CLCL  
CLCL  
CLCL  
1
SCL LOW time  
SCL HIGH time  
SCL rise time  
SCL fall time  
≥ 16 t  
≥ 14 t  
> 4.7 µs  
LOW  
HIGH  
RC  
1
> 4.0 µs  
2
≤ 1 µs  
–
3
≤ 0.3 µs  
< 0.3 µs  
FC  
SDA TIMING CHARACTERISTICS  
t
t
t
t
t
t
t
t
t
; DAT1  
; DAT2  
; DAT3  
; DAT  
Data set-up time  
≥ 250 ns  
≥ 250 ns  
≥ 250 ns  
≥ 0 ns  
> 20 t  
– t  
SU  
SU  
SU  
HD  
SU  
SU  
CLCL  
RD  
FC  
1
SDA set-up time (before rep. START cond.)  
SDA set-up time (before STOP cond.)  
Data hold time  
> 1 µs  
> 8 t  
CLCL  
> 8 t  
– t  
CLCL  
1
; STA  
Repeated START set-up time  
STOP condition set-up time  
Bus free time  
≥ 14 t  
≥ 14 t  
≥ 14 t  
> 4.7 µs  
> 4.0 µs  
> 4.7 µs  
CLCL  
CLCL  
CLCL  
1
1
; STO  
BUF  
RD  
2
SDA rise time  
≤ 1µs  
≤ 0.3µs  
–
3
SDA fall time  
< 0.3 µs  
FD  
NOTES:  
1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.  
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1 µs.  
3. Spikes on the SDA and SCL lines with a duration of less than 3 t  
will be filtered out. Maximum capacitance on bus-lines SDA and  
CLCL  
SCL = 400 pF.  
4. t  
= 1/f  
= one oscillator clock period at pin XTAL1. For 62 ns < t  
< 285 ns (16 MHz) > f  
> 3.5 MHz) the SI01 interface meets  
OSC  
CLCL  
OSC  
CLCL  
2
the I C-bus specification for bit-rates up to 100 kbit/s.  
2
TIMING SIO1 (I C) INTERFACE  
repeated START condition  
STOP condition  
START or repeated START condition  
START condition  
t
SU;STA  
t
RD  
0.7 V  
CC  
SDA  
(INPUT/OUTPUT)  
0.3 V  
CC  
t
BUF  
t
t
t
FC  
FD  
RC  
t
SU;STO  
0.7 V  
CC  
SCL  
(INPUT/OUTPUT)  
0.3 V  
CC  
t
SU;DAT3  
t
t
t
t
SU;DAT1  
t
t
HD;STA  
LOW  
HIGH  
HD;DAT  
SU;DAT2  
SU00107A  
12  
1999 Jul 23  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
EXPLANATION OF THE AC SYMBOLS  
Each timing symbol has five characters. The  
first character is always ‘t’ (= time). The other  
characters, depending on their positions,  
indicate the name of a signal or the logical  
status of that signal. The designations are:  
A – Address  
Q – Output data  
R – RD signal  
– Time  
V – Valid  
W – WR signal  
t
X – No longer a valid logic level  
Z – Float  
C – Clock  
D – Input data  
H – Logic level high  
Examples: t  
= Time for address valid  
to ALE low.  
AVLL  
I
– Instruction (program memory contents)  
t
= Time for ALE low  
to PSEN low.  
LLPL  
L – Logic level low, or ALE  
P – PSEN  
t
LHLL  
ALE  
t
t
LLPL  
AVLL  
t
PLPH  
t
LLIV  
t
PLIV  
PSEN  
t
LLAX  
t
PXIZ  
t
PLAZ  
t
PXIX  
A0–A7  
INSTR IN  
A0–A7  
PORT 0  
PORT 2  
t
AVIV  
A0–A15  
A8–A15  
SU00006  
Figure 1. External Program Memory Read Cycle  
ALE  
PSEN  
RD  
t
WHLH  
t
LLDV  
t
t
LLWL  
RLRH  
t
RHDZ  
t
LLAX  
t
t
RLDV  
AVLL  
t
RLAZ  
t
RHDX  
A0–A7  
FROM RI OR DPL  
PORT 0  
PORT 2  
DATA IN  
A0–A7 FROM PCL  
INSTR IN  
t
AVWL  
t
AVDV  
P2.0–P2.7 OR A8–A15 FROM DPH  
A8–A15 FROM PCH  
SU00177  
Figure 2. External Data Memory Read Cycle  
13  
1999 Jul 23  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
ALE  
t
WHLH  
PSEN  
t
t
WLWH  
LLWL  
WR  
t
t
t
LLAX  
WHQX  
t
AVLL  
QVWX  
t
DW  
A0–A7  
FROM RI OR DPL  
PORT 0  
PORT 2  
DATA OUT  
A0–A7 FROM PCL  
INSTR IN  
t
AVWL  
P2.0–P2.7 OR A8–A15 FROM DPH  
A8–A15 FROM PCH  
SU00213  
Figure 3. External Data Memory Write Cycle  
INSTRUCTION  
ALE  
0
1
2
3
4
5
6
7
8
t
XLXL  
CLOCK  
t
XHQX  
t
QVXH  
OUTPUT DATA  
0
1
2
3
4
5
6
7
WRITE TO SBUF  
t
XHDX  
t
SET TI  
VALID  
XHDV  
INPUT DATA  
CLEAR RI  
VALID  
VALID  
VALID  
VALID  
VALID  
VALID  
VALID  
SET RI  
SU00027  
Figure 4. Shift Register Mode Timing  
V
–0.5  
CC  
0.7V  
CC  
CC  
0.45V  
0.2V  
–0.1  
t
CHCX  
t
t
t
CHCL  
CLCX  
CLCH  
t
CLCL  
SU00009  
Figure 5. External Clock Drive  
14  
1999 Jul 23  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
V
–0.5  
CC  
0.2V  
0.2V  
+0.9  
–0.1  
CC  
CC  
0.45V  
NOTE:  
AC inputs during testing are driven at V –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.  
CC  
Timing measurements are made at V min for a logic ‘1’ and V max for a logic ‘0’.  
IH  
IL  
SU00010  
Figure 6. AC Testing Input/Output  
V
V
+0.1V  
LOAD  
V
V
–0.1V  
TIMING  
REFERENCE  
POINTS  
OH  
V
LOAD  
–0.1V  
LOAD  
+0.1V  
OL  
NOTE:  
For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs,  
and begins to float when a 100mV change from the loaded V /V level occurs. I /I ≥ ±20mA.  
OH OL  
OH OL  
SU00011  
Figure 7. Float Waveform  
V
CC  
CC  
I
CC  
V
CC  
V
V
CC  
P0  
RST  
EA  
P1.6  
P1.7  
87C652/4  
*
*
(NC)  
XTAL2  
XTAL1  
CLOCK SIGNAL  
V
SS  
SU00272  
Figure 8. I Test Condition, Active Mode  
CC  
All other pins are disconnected  
NOTE:  
Ports 1.6 and 1.7 should be connected to V through resistors of sufficiently high value such that the sink current into these pins does not  
*
CC  
exceed the I  
specification.  
OL1  
15  
1999 Jul 23  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
V
CC  
CC  
I
CC  
V
CC  
P0  
V
RST  
EA  
87C652/4  
P1.6  
P1.7  
*
(NC)  
CLOCK SIGNAL  
XTAL2  
XTAL1  
*
V
SS  
SU00273  
Figure 9. I Test Condition, Idle Mode  
CC  
All other pins are disconnected  
V
–0.5  
CC  
0.7V  
CC  
CC  
0.45V  
0.2V  
–0.1  
t
CHCX  
t
t
t
CHCL  
CLCX  
CLCH  
t
CLCL  
SU00009  
Figure 10. Clock Signal Waveform for I Tests in Active and Idle Modes  
CC  
t
= t  
= 10 ns  
CHCL  
CLCH  
V
CC  
CC  
I
CC  
V
CC  
V
RST  
EA  
P0  
87C652/4  
P1.6  
P1.7  
(NC)  
XTAL2  
XTAL1  
*
*
V
SS  
SU00274  
Figure 11. I Test Condition, Power Down Mode  
CC  
All other pins are disconnected. V = 2 V to 5.5 V  
CC  
NOTE:  
Ports 1.6 and 1.7 should be connected to V through resistors of sufficiently high value such that the sink current into these pins does not  
*
CC  
exceed the I  
specification.  
OL1  
16  
1999 Jul 23  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
shown in Figure 12. The code byte to be  
programmed into that location is applied to  
port 0. RST, PSEN and pins of ports 2 and 3  
specified in Table 4 are held at the ‘Program  
Code Data’ levels indicated in Table 4. The  
ALE/PROG is pulsed low 25 times as shown  
in Figure 13.  
program verification. The address of the  
program memory locations to be read is  
applied to ports 1 and 2 as shown in  
Figure 14. The other pins are held at the  
‘Verify Code Data’ levels indicated in Table 4.  
The contents of the address location will be  
emitted on port 0. External pull-ups are  
required on port 0 for this operation.  
EPROM CHARACTERISTICS  
The 87C652/87C654 is programmed by using  
a modified Quick-Pulse Programming  
algorithm. It differs from older methods in the  
value used for V (programming supply  
PP  
voltage) and in the width and number of the  
ALE/PROG pulses.  
To program the encryption table, repeat the 25  
pulse programming sequence for addresses 0  
through 1FH, using the ‘Pgm Encryption Table’  
levels. Do not forget that after the encryption  
table is programmed, verification cycles will  
produce only encrypted data.  
The 87C652/87C654 contains two signature  
bytes that can be read and used by an  
EPROM programming system to identify the  
device. The signature bytes identify the device  
as an 87C652/87C654 manufactured by  
Philips Components.  
If the encryption table has been programmed,  
the data presented at port 0 will be the  
exclusive NOR of the program byte with one  
of the encryption bytes. The user will have to  
know the encryption table contents in order to  
correctly decode the verification data. The  
encryption table itself cannot be read out.  
To program the lock bits, repeat the 25 pulse  
programming sequence using the ‘Pgm Lock  
Bit’ levels. After one lock bit is programmed,  
further programming of the code memory and  
encryption table is disabled. However, the  
other lock bit can still be programmed.  
Table 4 shows the logic levels for reading the  
signature byte, and for programming the  
program memory, the encryption table, and  
the lock bits. The circuit configuration and  
waveforms for quick-pulse programming are  
shown in Figures 12 and 13. Figure 14 shows  
the circuit configuration for normal program  
memory verification.  
Reading the Signature Bytes  
The signature bytes are read by the same  
procedure as a normal verification of  
locations 030H and 031H, except that P3.6  
and P3.7 need to be pulled to a logic low. The  
values are:  
(030H) = 15H indicates manufactured by  
Philips  
(031H) = 99H  
Note that the EA/V pin must not be allowed  
PP  
to go above the maximum specified V level  
PP  
for any amount of time. Even a narrow glitch  
above that voltage can cause permanent  
Quick-Pulse Programming  
The setup for microcontroller quick-pulse  
programming is shown in Figure 12. Note  
that the 87C652/87C654 is running with a  
4 to 6 MHz oscillator. The reason the  
oscillator needs to be running is that the  
device is executing internal address and  
program data transfers.  
damage to the device. The V source  
PP  
should be well regulated and free of glitches  
and overshoot.  
Program/Verify Algorithms  
Any algorithm in agreement with the  
conditions listed in Table 4, and which  
satisfies the timing specifications, is suitable.  
Program Verification  
If lock bit 2 has not been programmed, the  
on-chip program memory can be read out for  
The address of the EPROM location to be  
programmed is applied to ports 1 and 2, as  
Table 4. EPROM Programming Modes  
MODE  
Read signature  
RST  
PSEN  
ALE/PROG  
EA/V  
P2.7  
P2.6  
P3.7  
P3.6  
PP  
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
0
1
1
0
1
1
1
1
0
0
1
1
0
1
0
Program code data  
Verify code data  
Pgm encryption table  
Pgm lock bit 1  
0*  
1
V
PP  
1
0*  
0*  
0*  
V
PP  
PP  
PP  
V
V
Pgm lock bit 2  
NOTES:  
1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.  
2. V = 12.75 V ±0.25 V.  
PP  
3. V = 5 V±10% during programming and verification.  
CC  
*
ALE/PROG receives 25 programming pulses while V is held at 12.75 V. Each programming pulse is low for 100 µs (±10 µs) and high for a  
PP  
minimum of 10 µs.  
Trademark phrase of Intel Corporation.  
17  
1999 Jul 23  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
+5V  
V
CC  
P0  
A0–A7  
PGM DATA  
+12.75V  
P1  
1
1
1
RST  
P3.6  
EA/V  
PP  
25 100µs PULSES TO GROUND  
ALE/PROG  
PSEN  
0
1
P3.7  
87C652/4  
XTAL2  
P2.7  
0
P2.6  
4–6MHz  
XTAL1  
A8–A13  
P2.0–P2.5  
V
SS  
SU00275  
Figure 12. Programming Configuration  
25 PULSES  
1
0
ALE/PROG:  
ALE/PROG:  
10µs MIN  
100µs+10  
1
0
SU00018  
Figure 13. PROG Waveform  
+5V  
V
CC  
P0  
A0–A7  
PGM DATA  
P1  
1
1
1
RST  
P3.6  
1
1
EA/V  
PP  
ALE/PROG  
PSEN  
0
P3.7  
87C652/4  
0 ENABLE  
XTAL2  
P2.7  
0
P2.6  
4–6MHz  
XTAL1  
A8–A13  
P2.0–P2.5  
V
SS  
SU00276  
Figure 14. Program Verification  
18  
1999 Jul 23  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS  
T
amb  
= 21°C to +27°C, V = 5V±10%, V = 0V (See Figure 15)  
CC SS  
SYMBOL  
PARAMETER  
MIN  
MAX  
13.0  
50  
UNIT  
V
V
PP  
Programming supply voltage  
Programming supply current  
Oscillator frequency  
12.5  
I
PP  
mA  
MHz  
1/t  
CLCL  
4
6
t
t
t
t
t
t
t
t
t
t
t
t
Address setup to PROG low  
Address hold after PROG  
Data setup to PROG low  
Data hold after PROG  
48t  
AVGL  
CLCL  
CLCL  
CLCL  
CLCL  
CLCL  
48t  
48t  
48t  
48t  
GHAX  
DVGL  
GHDX  
EHSH  
SHGL  
GHSL  
GLGH  
AVQV  
ELQZ  
EHQZ  
GHGL  
P2.7 (ENABLE) high to V  
PP  
V
PP  
V
PP  
setup to PROG low  
hold after PROG  
10  
10  
90  
µs  
µs  
µs  
PROG width  
110  
Address to data valid  
48t  
CLCL  
CLCL  
CLCL  
ENABLE low to data valid  
Data float after ENABLE  
PROG high to PROG low  
48t  
48t  
0
10  
µs  
PROGRAMMING*  
ADDRESS  
VERIFICATION*  
ADDRESS  
P1.0–P1.7  
P2.0–P2.3  
t
AVQV  
PORT 0  
DATA IN  
DATA OUT  
t
t
GHDX  
GHAX  
t
t
DVGL  
AVGL  
ALE/PROG  
t
t
t
GHGL  
GLGH  
t
SHGL  
GHSL  
LOGIC 1  
LOGIC 1  
EA/V  
PP  
LOGIC 0  
t
t
t
EHSH  
ELQV  
EHQZ  
P2.7  
ENABLE  
SU00270  
*
FOR PROGRAMMING VERIFICATION SEE FIGURE 12.  
FOR VERIFICATION CONDITIONS SEE FIGURE 14.  
Figure 15. EPROM Programming and Verification  
2
2
Purchase of Philips I C components conveys a license under the Philips’ I C patent  
2
to use the components in the I C system provided the system conforms to the  
I C specifications defined by Philips. This specification can be ordered using the  
2
code 9398 393 40011.  
19  
1999 Jul 23  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
DIP40: plastic dual in-line package; 40 leads (600 mil)  
SOT129-1  
20  
1999 Jul 23  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
PLCC44: plastic leaded chip carrier; 44 leads  
SOT187-2  
21  
1999 Jul 23  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm  
SOT307-2  
22  
1999 Jul 23  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
NOTES  
23  
1999 Jul 23  
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller  
8K/16K, 256 OTP, I2C  
87C652/87C654  
Data sheet status  
[1]  
Data sheet  
status  
Product  
status  
Definition  
Objective  
specification  
Development  
This data sheet contains the design target or goal specifications for product development.  
Specification may change in any manner without notice.  
Preliminary  
specification  
Qualification  
This data sheet contains preliminary data, and supplementary data will be published at a later date.  
Philips Semiconductors reserves the right to make changes at any time without notice in order to  
improve design and supply the best possible product.  
Product  
specification  
Production  
This data sheet contains final specifications. Philips Semiconductors reserves the right to make  
changes at any time without notice in order to improve design and supply the best possible product.  
[1] Please consult the most recently issued datasheet before initiating or completing a design.  
Definitions  
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one  
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or  
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended  
periods may affect device reliability.  
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips  
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or  
modification.  
Disclaimers  
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications  
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.  
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard  
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless  
otherwise specified.  
Philips Semiconductors  
811 East Arques Avenue  
P.O. Box 3409  
Copyright Philips Electronics North America Corporation 1999  
All rights reserved. Printed in U.S.A.  
Sunnyvale, California 94088–3409  
Telephone 800-234-7381  
Date of release: 07-99  
Document order number:  
9397-750-06607  
Philips  
Semiconductors  

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