88W8801-B0-NMDI/AK_技术文档

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

Rev. 2 — 14 December 2020

Product short data sheet

1 Product overview

The 88W8801 is a highly integrated, single-band (2.4 GHz) IEEE 802.11n 1x1 System-

on-Chip (SoC), specifically designed to support High Throughput (HT) data rates for Wi-

Fi products.

The device provides the combined functions of Direct Sequence Spread Spectrum

(DSSS) and Orthogonal Frequency Division Multiplexing (OFDM) baseband modulation,

Medium Access Controller (MAC), CPU, memory, host interfaces, and direct conversion

Wi-Fi RF radio on a single integrated chip.

For security, the 802.11i security standard is supported through several protocols. And for

video, voice, and multimedia applications, 802.11e Quality of Service (QoS) is supported.

Host interfaces include USB 2.0 and SDIO 2.0 to connect the Wi-Fi radio to the host

processor.

The device is available in a 48-pin QFN package.

Figure 1 shows the application block diagram of the device.

Wi-Fi

Antenna

88W8801

SDIO Interface

Wi-Fi 2.4 GHz

USB 2.0 Interface

GPIO Interface

3.3V and 1.8V

Power-Down

XTAL_IN

XTAL_OUT

Figure 1.ꢀApplication block diagram

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

1.1 Applications

• Internet of Things

• Imaging platforms (printers, digital still cameras, digital picture frames)

• Consumer electronic devices

• Smart Energy systems

• Connected appliances

1.2 Wi-Fi key features

• 1x1 SISO and HT20 operation

• 802.11e Quality of Service (QoS)

• Thick MAC architecture

• Simultaneous operation

– Mobile AP and STA

– Wi-Fi direct and STA

• Supports WPA2/WPA2 mixed mode and WPA3 security standards

1.3 Host interfaces

• USB 2.0 with Link Power Management (LPM)

• SDIO 2.0

1.4 Operating characteristics

• Supply voltage: 1.8V and 3.3V

• Operating temperature

– Commercial: 0 to 70°C

– Extended: -30 to 85°C

– Industrial: -40 to 85°C

1.5 General features

• Package: 48-pin QFN (6 mm x 6 mm)

• 26 MHz and 38.4 MHz crystal clock support

– Supports CMOS and low-swing sine wave input clock

• Low-power operation supporting deep-sleep and standby modes

• ARM-based CPU

• 128 MHz maximum CPU clock speed

• Peripheral interfaces:

– Clocked serial unit: 2-Wire serial interface

– UART (debug) interface

– General Purpose Input Output (GPIO)

• Memory

– Internal SRAM

– Boot ROM

– One Time Programmable (OTP) memory for storing the MAC address and calibration

data

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

2 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

1.6 Internal block diagram

SDIO 2.0

USB 2.0

1x1

Wi-Fi 4 MAC/

Baseband (802.11n)

CPU

Wi-Fi 2.4G Tx/Rx

2.4 GHz PA/LNA

GPIO interface

3.3V and 1.8V

Power regulator

OTP

Figure 2.ꢀInternal block diagram

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

3 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

2 Ordering information

88W8801-xx-xxxC/xx

Packing code

Temperature code

C = Commercial

E = Extended

I = Indutrial

Part number

Revision number

Package code

Figure 3.ꢀPart numbering scheme

Table 1.ꢀPart order codes

Part Order Code

Package Type

Packing

88W8801-B0-NMDC/AK 48-pin QFN - 6 x 6 x 0.85 mm, with 0.4 mm pitch

88W8801-B0-NMDC/AZ 48-pin QFN - 6 x 6 x 0.85 mm, with 0.4 mm pitch

88W8801-B0-NMDE/AK 48-pin QFN - 6 x 6 x 0.85 mm, with 0.4 mm pitch

88W8801-B0-NMDE/AZ 48-pin QFN - 6 x 6 x 0.85 mm, with 0.4 mm pitch

88W8801-B0-NMDI/AK 48-pin QFN - 6 x 6 x 0.85 mm, with 0.4 mm pitch

88W8801-B0-NMDI/AZ 48-pin QFN - 6 x 6 x 0.85 mm, with 0.4 mm pitch

Tray

Tape and Reel

Tray

Tape and Reel

Tray

Tape and Reel

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

4 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

3 Wi-Fi subsystem

3.1 IEEE 802.11 standards

• 802.11 data rates of 1 and 2 Mbps

• 802.11b data rates of 5.5 and 11 Mbps

• 802.11g data rates 6, 9, 12, 18, 24, 36, 48, and 54 Mbps for multimedia content

transmission

• 802.11g/b performance enhancements

• 802.11n compliant with maximum data rates up to 72.2 Mbps (20 MHz channel)

• 802.11d international roaming

• 802.11e quality of service

• 802.11h transmit power control

• 802.11i enhanced security

• 802.11k radio resource measurement

• 802.11n block acknowledgement extension

• 802.11r fast hand-off for AP roaming

• 802.11w protected management frames

• Fully supports clients (stations) implementing IEEE Power Save mode

• Wi-Fi direct connectivity

3.2 Wi-Fi MAC

• Simultaneous peer-to-peer and infrastructure modes

• RTS/CTS for operation under DCF

• Hardware filtering of 32 multicast addresses

• On-chip Tx and Rx FIFO for maximum throughput

• Open system and shared key authentication services

• A-MPDU Rx (de-aggregation) and Tx (aggregation)

• Reduced Inter-Frame Spacing (RIFS) receive

• Management information base counters

• Radio resource measurement counters

• Quality of service queues

• Block acknowledgement extension

• Multiple-BSSID and Multiple-Station operation

• Transmit rate adaptation

• Transmit power control

• Long and short preamble generation on a frame-by-frame basis for 802.11b frames

• Mobile hotspot

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

5 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

3.3 Wi-Fi baseband

• 802.11n 1x1 SISO

• Backward compatibility with legacy 802.11g/b technology

• PHY data rates up to 72.2 Mbit/s

• 20 MHz channel bandwidth

• Modulation and Coding Scheme (MCS)—MCS 0~7

• Radio resource measurement

• Optional 802.11n SISO features:

– 1 spatial stream STBC reception and transmission

– Short guard interval

– RIFS on receive path for 802.11n packets

– 802.11n greenfield Tx/Rx

• Power save features

3.4 Wi-Fi radio

• Integrated direct-conversion radio

• 20 MHz channel bandwidth

• Integrated Tx/Rx RF switch, PA, and LNA

Wi-Fi Rx path

• Direct conversion architecture eliminates need for external SAW filter

• On-chip gain selectable LNA with optimized noise figure and power consumption

• High dynamic range AGC function in receive mode

Wi-Fi Tx path

• Integrated power amplifier with power control

• Optimized Tx gain distribution for linearity and noise performance

Wi-Fi local oscillator

• Fractional-N oscillator for multiple reference clock support

• Fine channel step

3.5 Wi-Fi encryption

• WEP 64- and 128-bit encryption

• AES-CCMP hardware implementation as part of 802.11i security standard (WPA2)

• Enhanced AES engine performance

• AES-Cipher-Based Message Authentication Code (CMAC) as part of the 802.11w

security standard

• Simultaneous Authentication of Equals (SAE) WPA3

• WLAN Authentication and Privacy Infrastructure (WAPI)

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

6 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

3.6 Wi-Fi host interfaces

• USB 2.0 with Link Power Management (LPM)

• SDIO 2.0

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

7 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

4 Pin information

4.1 Signal diagram

88W8801

RF_CNTL0_N

RF Front End Interface

RF_TR

Wi-Fi Radio Interface

RF_CNTL1_P

USB_DMNS

USB_DPLS

USB 2.0 Host Interface

SDIO 2.0 Interface

Power-down

PDn

USB_VBUS_ON

XTAL_IN

Clock Interface

SD_CLK

XTAL_OUT

SD_CMD

SD_DAT[3:0]

XOSC_EN

REF_CLK_OUT

HOST_WAKE

CON[1]

GPIO[3:0]

GPIO Interface

Control Interface

CON[0]

SER_CLK

SER_DAT

Two-wire Serial Interface

TCK

TDI

UART_SIN

JTAG Interface

UART Interface (debug)

TDO

TMS

UART_SOUT

Figure 4.ꢀSignal diagram

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

8 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

4.2 Pin assignment

Figure 5 shows the pin assignment on the 48-pin QFN package top view.

24

23

22

21

20

19

18

17

16

15

14

13

37

38

39

40

41

42

43

44

45

46

47

48

SD_DAT[0]

VDD11

SD_DAT[1]

SD_DAT[2]

REF_CLK_OUT

CON[0]

CON[1]

SD_DAT[3]

SD_CMD / USB_VBUS_ON

HOST_WAKE

AVDD18

SD_CLK

VIO_SD

88W8801

XTAL_OUT

XTAL_IN

GPIO[0]

GPIO[1]

AVDD18

GPIO[2]

GPIO[3]

VIO

VSS

Figure 5.ꢀ88W8801 pin assignment (package top view)

4.3 Signal types

Table 2.ꢀPin types

Pin type

Description

I/O

I

Digital input/output

Digital input

O

Digital output

Analog input

Analog output

A, I

A, O

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

9 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

4.4 Pin list

Table 3 shows the pin list sorted by pin number.

Table 3.ꢀPin list by number

Pin number

Pin name

TDI

Supply

Type

I

1

VIO

2

TCK

VIO

I

3

TDO

VIO

O

4

TMS

VIO

I

5

VDD33

--

Power

O

6

RF_CNTL0_N

RF_CNTL1_P

AVDD18

AVDD33

RF_TR

VDD33

7

VDD33

O

8

--

Power

A, I/O

Ground

Power

A, I

9

--

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

--

AVDD33

VSS

--

VSS

--

AVDD18

XTAL_IN

XTAL_OUT

AVDD18

HOST_WAKE

CON[1]

--

AVDD18

A, O

Power

I

--

AVDD18

I

CON[0]

AVDD18

I

REF_CLK_OUT

VDD11

AVDD18

O

--

Power

I

VSS

--

VSS

--

VSS

--

LDO11_VOUT

LDO18_VOUT

VDD33

--

PDn

AVDD18

VDD11

--

Power

AVDD33

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

10 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

Table 3.ꢀPin list by number...continued

Pin number

Pin name

USB_DPLS

USB_DMNS

SD_DAT[0]

SD_DAT[1]

SD_DAT[2]

SD_DAT[3]

SD_CMD / USB_VBUS_ON

SD_CLK

Supply

AVDD33

VIO_SD

--

Type

I/O

35

36

37

38

39

40

41

42

43

44

45

46

47

48

I/O

I

VIO_SD

Power

I/O

GPIO[0]

VIO

GPIO[1]

VIO

I/O

GPIO[2]

VIO

I/O

GPIO[3]

VIO

I/O

VIO

--

Power

4.5 Pin description

4.5.1 Pin states

The terminology used for the pin state information in some pin description tables is as

follows:

• HW State: Hardware default state after reset

• PD State: Power-down state

• PU/PD: Programmable pull-up/pull-down

Note:

After firmware is downloaded, the pads (GPIO, serial interface, JTAG, and RF control)

are programmed in functional mode per the functionality of the pins.

For SDIO, once the command is received from the host, the pads are configured

accordingly. Pull-up (PU) and pull-down (PD) are only effective when the pad is in input

mode.

4.5.2 Wi-Fi radio interface

Table 4.ꢀWi-Fi radio interface

QFN

Pin No.

Pin name

RF_TR

Type

Supply

Description

11

A, I/O

AVDD33

Transmit/Receive RF Input/Output—2.4 GHz

Baseband input/output data

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

11 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

4.5.3 RF front-end control interface

Table 5.ꢀRF font-end control interface

QFN

Pin No.

No Pad

Power State

Reset

State

PD

State

Internal

PU

Pin Name

Supply

HW State

PU

no

PD

no

6

RF_CNTL0_N

VDD33

tristate

input

output drive drive

low low

weak PU

enable

RF Control 0 - RF control output low

RF_CNTL1_P VDD33

7

tristate

input

output drive drive

high high

weak PU

enable

no

RF Control 1 - RF control output high

4.5.4 General purpose I/O (GPIO) interface

Table 6.ꢀGeneral purpose I/O (GPIO) interface

QFN

Pin No.

Pad

supply

No pad

power state

Reset

state

Pin name

HW state PD state Internal PU

PU

PD

47

GPIO[3]

VIO

tristate

output drive output drive tristate

nominal PU yes

enable

yes

high

GPIO Mode: GPIO[3]

TWSI EEPROM Mode: SER_DAT

Serial interface data (input/output)

46

GPIO[2]

VIO

tristate

input

output drive tristate

high

weak PU

enable

no

GPIO Mode: GPIO[2]

TWSI EEPROM Mode: SER_CLK

Serial interface clock (input/output)

45

GPIO[1]

VIO

input

output drive tristate

high

weak PU

enable

yes

GPIO Mode: GPIO[1]

UART Mode: UART_SOUT (output), debug only

Host Wakeup: SoC-to-Host wakeup (output)

44

GPIO[0]

VIO

tristate

output

output drive tristate

high

nominal PU yes

enable

GPIO Mode: GPIO[0]

UART Mode: UART_SIN (input), debug only

Oscillator Mode: XOSC_EN (output, active high)

0 = disable external oscillator

1 = enable external oscillator

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

12 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

4.5.5 SDIO 2.0 host interface

Table 7.ꢀSDIO host interface

QFN

No pad

power state

Reset

state

HW

state

Pin name

Pin No.

Supply

PD state Internal PU

PU

PD

yes

42

SD_CLK

VIO_SD

tristate

input

tristate

nomi-nal PU yes

enable

SDIO 4-bit Mode: Clock input

SDIO 1-bit Mode: Clock input

SDIO SPI Mode: Clock input

41

SD_CMD/

VIO_SD

tristate

input

nomi-nal PU yes

enable

yes

USB_VBUS_ON

SDIO 4-bit Mode: Command/response (input/output)

SDIO 1-bit Mode: Command line

SDIO SPI Mode: Data input

USB Mode: USB_VBUS_ON (input)

37

SD_DAT[0]

VIO_SD

tristate

input

tristate

nomi-nal PU yes

enable

yes

SDIO 4-bit Mode: Data line Bit[0]

SDIO 1-bit Mode: Data line

SDIO SPI Mode: Data output

38

SD_DAT[1]

nomi-nal PU yes

enable

SDIO 4-bit Mode: Data line Bit[1]

SDIO 1-bit Mode: Interrupt

SDIO SPI Mode: Interrupt

39

SD_DAT[2]

nomi-nal PU yes

enable

SDIO 4-bit Mode: Data line Bit[2] or read wait (optional)

SDIO 1-bit Mode: Read wait (optional)

SDIO SPI Mode: Reserved

40

SD_DAT[3]

VIO_SD

tristate

nomi-nal PU yes

enable

SDIO 4-bit Mode: Data line Bit[3]

SDIO 1-bit Mode: Reserved

SDIO SPI Mode: Card select (active low)

4.5.6 USB 2.0 host interface

Table 8.ꢀUSB host interface^[1]

QFN

Pin No.

Pin name

Type

Supply

Description

36

35

USB_DMNS

USB_DPLS

I/O

AVDD33

USB Serial Differential Data Negative

USB Serial Differential Data Positive

[1] For USB_VBUS_ON, see Section 4.5.5 "SDIO 2.0 host interface".

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

13 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

4.5.7 Control interface

Table 9.ꢀControl interface

QFN

No pad

power state

Reset

state

HW

state

Pin name

Pin No.

Supply

PD state Internal PU

PU

yes

PD

yes

20

HOST_WAKE

AVDD18

tristate

input

tristate

weak PD

enable

Host Wakeup

Host-to-SoC Wakeup (input)

21

CON[1]

AVDD18

tristate

input

weak PU

enable

yes

no

yes

no

Configuration Pin (CON[1])

See Section 4.6 "Configuration pins".

22 CON[0] AVDD18

input

weak PU

ena-ble

Configuration Pin (CON[0])

See Section 4.6 "Configuration pins".

23 REF_CLK_OUT AVDD18

Reference Clock Output

analog

yes

4.5.8 Clock interface

Table 10.ꢀClock interface

QFN

Pin No.

Pin name

XTAL_IN

Type

A, I

Supply

Description

Crystal/Crystal Oscillator / System Clock Input

17

AVDD18

Accepts 26/38.4 MHz clock signals from a crystal oscillator

(frequency stability ±20 ppm).

18

XTAL_OUT

A, O

AVDD18

Crystal / Crystal Oscillator Output

Connect this pin to ground when an external oscil-lator is used.

4.5.9 Power-down

Table 11.ꢀPower-down

QFN

Pin No.

Pin name

Type

Supply

Description

31

PDn

I

Input

Full Power-Down (active low)

0 = full power-down mode

1 = normal mode

• Connect to power-down pin of host or 3.3V/1.8V

• External host required to drive this pin high for normal operation

No internal pull-up on this pin.

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

14 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

4.5.10 Power supply and ground pins

Table 12.ꢀPower supply and ground pins

QFN

Pin No.

Pin name

Type

Description

24

VDD11

Power

1.1V Core Power Supply

32

48

43

VIO

Power

1.8V/3.3V Digital I/O Power Supply

1.8V/3.3V Digital I/O SDIO Power Supply

3.3V Digital Power Supply

VIO_SD

VDD33

5

30

8

AVDD18

Power

1.8V Analog Power Supply

9

14

15

16

19

10

33

34

AVDD33

Power

3.3V Analog Power Supply

28

29

LDO11_VOUT

LDO18_VOUT

VSS

Power

Ground

1.1V LV LDO Voltage Output

1.8V LV LDO Voltage Output

12

13

25

26

27

Ground

Connect these pins to ground

4.5.11 UART interface (debug)

Table 13.ꢀUART interface (debug)

QFN

Pin name

Type

Supply

Description

Pin No.

44

45

UART_SIN

UART_SOUT

I

VIO

UART serial input signal. GPIO[0] input/output

UART serial output signal. GPIO[1] input/output

O

4.5.12 Two-wire serial interface

Table 14.ꢀTwo-wire serial interface

QFN

Pin No.

Pin name

Type

Supply

Description

46

SER_CLK

SER_DAT

I/O

VIO

Serial interface clock signal. GPIO[2] input/output

Serial interface data signal. GPIO[3] input/output

47

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

15 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

4.5.13 JTAG interface

Table 15.ꢀJTAG interface

QFN

No pad

power state

Reset

state

Pin name

Pin No.

Supply

VIO

HW state PD state Internal PU

PU

PD

yes

2

TCK

tristate

input

tristate

nominal PU yes

enable

JTAG test clock (input)

TDI

1

VIO

tristate

input

nominal PU yes

enable

yes

no

JTAG test data (input)

TDO

3

output

drive low

weak PU

ena-ble

no

JTAG test data (output)

TMS

4

input

nominal PU yes

enable

yes

JTAG controller select (input)

4.6 Configuration pins

Table 16 shows the pins used as configuration inputs to set parameters following a reset.

The definition of these pins changes immediately after reset to their usual function. To

set a configuration bit to 0, attach a 100 kΩ resistor from the pin to ground. No external

circuitry is required to set a configuration bit to 1.

Table 16.ꢀConfiguration pins

Configuration bits

Pin name

SER_CLK

Configuration function

CON[2]

Oscillator frequency select

0 = 26 MHz

1 = 38.4 MHz (default)

CON[1]

CON[0]

CON[1]

CON[0]

Firmware boot options

00 = UART (debug)

01 = reserved

10 = SDIO

11 = USB (default)

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

16 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

5 Power information

5.1 Leakage optimization

For applications not using Wi-Fi, the device can be put into a low-leakage mode of

operation. Methods used to achieve this include:

• Using PDn pin

The power-down state provides the lowest leakage mode of operation. Assert PDn low

to enter power-down. This must be met to enter a power-down state.

• All rails powered off

Alternatively, all power rails can be powered off. In this case, the state of the PDn pin is

irrelevant.

5.2 Power options

5.2.1 Case 1 - Internal 1.1V and internal 1.8V

Figure 6 shows the power option with the internal 1.1V and internal 1.8V supply.

88W8801

VDD11

LDO11

AVDD18

LDO18

VDD33

AVDD33

External 3.3V

Host

VIO

Figure 6.ꢀCase 1 - Internal 1.1V and internal 1.8V

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

17 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

5.2.1.1 Power-up sequence for case 1 and PDn driven by host

• External VDD33/VIO/VIO_SD from host

• Internal AVDD18/VDD11 from on-chip LDOs

• PDn driven by host

The following requirements must be met for correct power-up:

• Assert PDn low (active) during VDD33/VIO/VIO_SD ramp-up. Continue to assert low

for a minimum of 1 ms after VDD33/VIO/VIO_SD are stable.

• External 3.3V or 1.8V can be used for VIO/VIO_SD as needed by the platform.

• VIO_SD is provided by host if SDIO interface is used.

• VDD33 is used as input to LDO18, which outputs AVDD18.

• VDD33 is used as input to LDO11, which outputs VDD11.

• If an external crystal oscillator is used, then GPIO[0] is used as XOSC_EN.

Figure 7 shows the power-up sequence for case 1 and PDn driven by host.

3.3V

1ms

VDD33 / VIO /

VIO_SD

PDn

1.8V

AVDD18

(on-chip LDO18)

1.1V

VDD11

(on-chip LDO11)

~ 5ms

Internal POR

XOSC_EN

(GPIO[0])

XTAL_IN

(reference clock)

Strap/

Internal Reset

Boot ROM execution starts and

Firmware download begins

Figure 7.ꢀPower-up sequence for case 1 and PDn driven by host

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

18 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

5.2.1.2 Power-up sequence for case 1 and PDn tied to VDD33

• External VDD33/VIO/VIO_SD from host

• Internal AVDD18/VDD11 from on-chip LDOs

• PDn is tied to VDD33

The following requirements must be met for correct power-up:

• Ramp-up time of VDD33 should be < 5 ms.

• VDD33 is used as VIO/VIO_SD.

• VDD33 is used as input to LDO18, which outputs AVDD18.

• VDD33 is used as input to LDO11, which outputs VDD11.

• If an external crystal oscillator is used, then GPIO[0] is used as XOSC_EN.

Figure 8 shows the power-up sequence for case 1 and PDn tied to VDD33.

3.3V

VDD33 / VIO /

VIO_SD

PDn

1.8V

AVDD18

(on-chip LDO18)

1.1V

VDD11

(on-chip LDO11)

~ 5ms

Internal POR

XOSC_EN

(GPIO[0])

XTAL_IN

(reference clock)

Boot ROM execution starts and

Firmware download begins

Strap/

Internal Reset

Figure 8.ꢀPower-up sequence for case 1 and PDn tied to VDD33

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

19 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

5.2.2 Case 2 - Internal 1.1V and external 1.8V

Figure 9 shows the second power option with 1.1V internal voltage supply and 1.8V

external supply.

88W8801

Power Management

Device

VDD11

LDO11

Battery

DC-DC/LDO

AVDD18

LDO18

External 1.8V

VDD33

AVDD33

VIO

External 3.3V

Host

Figure 9.ꢀPower options, case 2—Internal 1.1V, external 1.8V

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

20 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

5.2.2.1 Power-up sequence for case 2

• External VDD33/VIO/VIO_SD from host

• External AVDD18

• Internal VDD11 from on-chip LDO

• PDn is driven by host

The following requirements must be met for correct power-up:

• Assert PDn low (active) during VDD33/VIO/VIO_SD and AVDD18 ramp-up. Continue to

assert low for a minimum of 1 ms after VDD33/VIO/VIO_SD and AVDD18 are stable.

• External 3.3V or 1.8V can be used for VIO/VIO_SD as needed by the platform.

• VIO_SD is provided by host if SDIO interface is used.

• VDD33 is used as input to LDO11, which outputs VDD11.

• If an external crystal oscillator is used, then GPIO[0] is used as XOSC_EN.

Figure 10 shows the power-up sequence for the power option with internal 1.1V and

external 1.8V.

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

21 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

3.3V

VDD33

AVDD18 / VIO /

VIO_SD (external)

1ms

PDn

1.1V

VDD11

(on-chip LDO11)

~ 5ms

Internal POR

XOSC_EN

(GPIO[0])

XTAL_IN

(reference clock)

Strap/

Internal Reset

Boot ROM execution starts and

Firmware download begins

Figure 10.ꢀPower-up sequence for case 2

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

22 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

6 Absolute maximum ratings

Table 17.ꢀAbsolute maximum ratings

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDD11

Power supply voltage

with respect to VSS

--

1.1

1.26

V

VIO

Power supply voltage

with respect to VSS

--

1.8

3.3

1.8

3.3

2.2

4.0

2.2

4.0

V

VIO_SD

Power supply voltage

with respect to VSS

--

VDD33

Power supply voltage

with respect to VSS

--

AVDD18

AVDD33

Power supply voltage

with respect to VSS

--

1.8

3.3

1.98

4.0

V

Power supply voltage

with respect to VSS

T_STORAGEStorage temperature

V_ESD

-55

-2

--

+125

+2

°C

kV

electrocstatic discharge human body model

voltage

(HBM)^[1]

charged device model

(CDM)^[2]

-500

--

+500

V

[1] According to JESD22-A114F

[2] According to JESD22-C101E

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

23 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

7 Recommended operating conditions

Table 18.ꢀRecommended operating conditions

Symbol

VDD11

VIO

Parameter

Condition

Min

--

Typ

1.1

1.8

3.3

1.8

3.3

1.8

Max

1.21

1.98

3.63

1.98

3.63

1.89

Unit

V

1.1V core power supply --

1.8V/3.3V digital I/O

power supply

--

1.62

2.97

1.62

2.97

1.71

V

VIO_SD

1.8V/3.3V digital I/O

SDIO power supply

V

VDD33

3.3V I/O power supply

V

AVDD18

1.8V analog power

supply

V

AVDD33

T_A

3.3V analog power

supply

--

2.97

3.3

3.63

V

Ambient operating

temperature

Commercial

Extended

Industrial

--

0

--

70

85

°C

-30

-40

--

85

T_J

Maximum junction

temperature

125

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

24 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

8 Electrical specifications

8.1 GPIO interface specifications

8.1.1 VIO DC characteristics

8.1.1.1 VIO DC characteristics - 1.8V operation

Table 19.ꢀDC electricals—1.8V operation (VIO)

Symbol

V_IH

Parameter

Input high voltage

Input low voltage

Input hysteresis

Condition

--

Min

0.7*VIO

-0.4

Typ

--

Max

VIO+0.4

0.3*VIO

--

Unit

V

V_IL

--

V

V_HYS

V_OH

V_OL

100

--

mV

V

Output high voltage

Output low voltage

VIO-0.4

--

0.4

V

8.1.1.2 VIO DC characteristics - 3.3V operation

Table 20.ꢀDC electricals—3.3V operation (VIO)

Symbol

V_IH

Parameter

Input high voltage

Input low voltage

Input hysteresis

Condition

--

Min

0.7*VIO

-0.4

Typ

--

Max

VIO+0.4

0.3*VIO

--

Unit

V

V_IL

--

V

V_HYS

V_OH

V_OL

100

--

mV

V

Output high voltage

Output low voltage

VIO-0.4

--

0.4

V

8.2 RF front-end control interface specifications

Table 21.ꢀDC electricals—3.3V operation (VDD33)

Symbol

V_IH

Parameter

Input high voltage

Input low voltage

Input hysteresis

Condition

--

Min

0.7*VDD33

-0.4

Typ

--

Max

Unit

V

VDD33+0.4

V_IL

--

0.3*VDD33

V

V_HYS

V_OH

V_OL

100

--

mV

V

Output high voltage

Output low voltage

VDD33-0.4

--

0.4

V

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

25 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

8.3 Wi-Fi radio specifications

8.3.1 Wi-Fi radio performance measurement

The Wi-Fi transmit/receive performance is measured either at the antenna port or at the

chip output port.

88W8801

Wi-Fi 2.4G Tx/Rx

Filter

Chip

output port

Antenna

port

Figure 11.ꢀRadio performance measurement points

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

26 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

8.3.2 Wi-Fi receiver performance

Note: Unless otherwise stated, all specifications are at 25°C, typical voltage, across

frequency range, and at the chip output port. See Section 7 "Recommended operating

conditions" for typical voltage levels.

Table 22.ꢀWi-Fi receiver performance

Parameter

RF frequency range

Condition

Min

2400

--

Typ

--

Max

2500

--

Unit

MHz

dBm

2.4 GHz—IEEE 802.11n/g/b

Receiver input IP3 at RF high gain Rx input IP3 when LNA in high

-15

gain mode (24 dB) at chip input

(In-band)

Receiver sensitivity 802.11b

1 Mbit/s

2 Mbit/s

5.5 Mbit/s

11 Mbit/s

6 Mbit/s

9 Mbit/s

12 Mbit/s

18 Mbit/s

24 Mbit/s

36 Mbit/s

48 Mbit/s

54 Mbit/s

MCS0

--

-98

-95

-92

-89

-91

-90

-88

-86

-83

-80

-75

-74

-91

-88

-86

-84

-80

-76

-74

-72

--

dBm

Receiver sensitivity 802.11g

Receiver sensitivity 802.11n -

HT20

MCS1

MCS2

MCS3

MCS4

MCS5

MCS6

MCS7

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

27 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

8.3.3 Wi-Fi transmitter performance

Note: Unless otherwise stated, all specifications are at 25°C, typical voltage, across

frequency range, and at chip output port. See Section 7 "Recommended operating

conditions" for typical voltage levels.

Table 23.ꢀWi-Fi transmitter performance

Parameter

RF frequency range

Condition

Min

2400

--

Typ

--

Max

2500

--

Unit

MHz

dBm

2.4 GHz—IEEE 802.11n/g/b

Transmit output saturation power 2.4 GHz—IEEE 802.11n/g/b

at chip output port

26

Transmit carrier suppression (CW) --

--

-36

-45

--

dB

Transmit I/Q suppression with IQ

calibration

--

dBc

Transmit power (EVM and mask

compliant) 20MHz

802.11b

--

19

17

29

--

dBm

dB

OFDM 64-QAM (MCS7)

Transmit carrier supression

(modulated signal)

802.11g OFDM 54 Mbit/s,

at 16dBm

8.3.4 Local oscillator

Table 24.ꢀLocal oscillator

Parameter

Condition

Min

Typ

Max

Unit

Phase noise

Measured at 2.438 GHz,

at 100kHz offset

--

-103

--

dBc/Hz

Integrated RMS phase noise at RF Reference clock frequency=

--

0.6

--

degree

kHz

output

26MHz or 38.4MHz (2.4GHz)

(from 1 kHz–10 MHz)

Frequency resolution

--

0.02

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

28 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

8.4 Current consumption

Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, across

frequency and typical value. The power consumption data was collected with SDIO

interface configuration.

Table 25.ꢀCurrent consumption

Mode

Conditions

3.3V

0.14

1.28

0.53

0.37

68

Unit

mA

Sleep mode

Wi-Fi in deep sleep mode

DTIM-1

IEEE power save (average)^[1]

(Beacon interval: 100 msec)

DTIM-3

DTIM-5

802.11b, 11 Mbit/s

802.11g, 54 Mbit/s

802.11n, HT20 MCS7

802.11b, 11 Mbit/s at 18 dBm

802.11g, 54 Mbit/s at 15 dBm

802.11n, HT20 MCS7 at 13 dBm

Wi-Fi receive

74

82

359

290

285

Wi-Fi transmit

[1] Measured using the internal LDO

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

29 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

8.5 SDIO host interface specifications

8.5.1 VIO_SD DC characteristics

8.5.1.1 VIO_SD DC characteristics - 1.8V operation

Table 26.ꢀDC electricals—1.8V operation (VIO_SD)

Symbol

V_IH

Parameter

Input high voltage

Input low voltage

Input hysteresis

Condition

--

Min

0.7*VIO_SD

-0.4

Typ

--

Max

Unit

V

VIO_SD+0.4

V_IL

--

0.3*VIO_SD

V

V_HYS

V_OH

V_OL

100

--

mV

V

Output high voltage

Output low voltage

VIO_SD-0.4

--

0.4

V

8.5.1.2 VIO_SD DC characteristics - 3.3V operation

Table 27.ꢀDC electricals—3.3V operation (VIO_SD)

Symbol

V_IH

Parameter

Input high voltage

Input low voltage

Input hysteresis

Condition

--

Min

0.7*VIO_SD

-0.4

Typ

--

Max

Unit

V

VIO_SD+0.4

V_IL

--

0.3*VIO_SD

V

V_HYS

V_OH

V_OL

100

--

mV

V

Output high voltage

Output low voltage

VIO_SD-0.4

--

0.4

V

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

30 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

8.5.2 SDIO host interface specifications

The 88W8801 SDIO host interface pins are powered from the VIO_SD voltage supply.

See the specifications in Section 8.5.1 "VIO_SD DC characteristics".

The SDIO electrical specifications are identical for the 1-bit SDIO and 4-bit SDIO modes.

f_PP

T_WL

T_WH

Clock

Input

T_ISU

T_IH

T_ODLY

Output

Figure 12.ꢀSDIO protocol timing diagram—Normal mode

f_PP

T_WL

T_WH

Clock

Input

T_ISU

T_IH

T_ODLY

T_OH

Output

Figure 13.ꢀSDIO protocol timing diagram—High-speed mode

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

31 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

Table 28.ꢀSDIO timing data^[1]

Over full range of values specified in the Recommended Operating Conditions unless otherwise specified.

Symbol

f_PP

Parameter

Condition

Normal

Min

0

Typ

--

Max

25

50

--

Unit

MHz

ns

Clock frequency

High-speed

Normal

0

--

T_WL

T_WH

T_ISU

T_IH

Clock low time

Clock high time

Input setup time

Input hold time

Output delay time

Output hold time

10

7

--

High-speed

Normal

--

ns

10

7

--

ns

High-speed

Normal

--

ns

5

--

ns

High-speed

Normal

6

--

ns

5

--

ns

High-speed

Normal

2

--

ns

T_ODLY

--

14

--

ns

High-speed

--

ns

T_OH

2.5

--

ns

[1] The SDIO-SPI CS signal timing is identical to all other SDIO inputs.

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

32 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

8.6 USB 2.0 host interface specifications

The USB 2.0 host interface pins are powered by AVDD33 voltage supply.

Table 29.ꢀElectrical characteristics

Over full range of values specified in the Recommended Operating Conditions unless otherwise specified.

Symbol

Supply current

I_CCHPF

Parameter

Conditions

Min

Typ

Max

Unit

High-power function

Low-power function

Unconfigured function

--

500

100

2.5

mA

I_CCLPF

I_CCINIT

I_CCSH

Suspended high-power

device

I_CCSL

Suspended low-power

device

--

500

µA

Input levels for low/full-speed

V_IH

Input high voltage (driven)

--

2.0

2.7

--

V

V_IHZ

V_IL

Input high voltage (floating) --

3.6

0.8

--

Input low voltage

--

V_DI

Differential input sensitivity --

0.2

0.8

V_CM

Differential common mode

range

--

2.5

Input levels for high-speed

V_HSSQ

V_HSDSC

--

High-speed squelch

100

525

--

150

625

--

mV

--

detection threshold

(differential signal

amplitude)

High-speed disconnect

detec-tion threshold

(differential signal

amplitude)

--

High-speed differential input Specified by eye pattern

signaling levels

templates; see Section

7.1.7.2 in the USB 2.0

specification.

V_HSCM

High-speed data signaling

common mode voltage

range

--

-50

500

mV

Output levels for low/full-speed

V_OL

Output low voltage

--

0.0

2.8

0.8

1.3

--

0.3

3.6

V

V_OH

Output high voltage (driven) --

V_OSE1

V_CRS

Output SE1 voltage

--

Output signal crossover

voltage

2.0

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

33 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

Table 29.ꢀElectrical characteristics...continued

Over full range of values specified in the Recommended Operating Conditions unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Output levels for high-speed

V_HSOI

High-speed idle level

--

-10.0

360

--

10.0

440

mV

V_HSOH

High-speed data signaling

high

V_HSOL

High-speed data signaling

low

--

-10.0

700

--

10.0

1100

-500

mV

V_CHIRPJ

V_CHIRPK

Chirp J level (differential

voltage)

Chirp K level (differential

voltage)

-900

Decoupling capacitance

C_RPBUpstream facing port

--

1.0

--

10.0

µF

bypass capacitance

Input capacitance for low/full-speed

C_INUB

Upstream facing port

capacitance (without cable)

--

100

75

pF

C_EDGE

Transceiver edge rate

control capacitance

Input impedance for high-speed

TDR spec for high-speed

Differential impedance

80

--

100

W

--

termination

Terminations

R_PUI

Bus pull-up resistor on

upstream port (idles bus)

--

0.900

1.425

300

--

1.575

3.090

--

kΩ

R_PUA

Z_INP

Bus pull-up resistor on

upstream port (receiving)

Input impedance exclusive --

of pull-up/pull-down (for low/

full-speed)

V_TERM

Termination voltage for

upstream facing port pull-up

--

3.0

-10

--

3.6

10

V

resistor (R_PU

)

Terminations in high-speed

V_HSTERM

Termination voltage

in high-speed

--

mV

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

34 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

Table 30.ꢀHigh-speed source electrical characteristics

Over full range of values specified in the Recommended Operating Conditions unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Driver characteristics

T_HSR

T_HSF

Rise Time (10% - 90%)

Fall Time (10% - 90%)

--

500

--

ps

--

Driver waveform

requirements

Specified by eye pattern

templates in Section 7.1.2 in

the USB 2.0 specification.

--

Z_{HS DRV}

-

Driver output resistance

--

40.5

--

49.5

W

(also serves as high-speed

termination)

Clock timings

T_HSDRAT

High-speed data rate

Microframe interval

--

479.760

124.9375

--

480.240

Mb/s

µs

T_HSFRAM

125.0625

T_HSRFI

Consecutive microframe

interval difference

4 high-

speed

--

bit times

High-speed data timings

Data source jitter

Specified by eye pattern

templates in Section 7.1.2.2

in the USB 2.0 specification.

--

Receiver jitter tolerance

Specified by eye pattern

--

templates in Section 7.1.2.2

in the USB 2.0 specification.

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

35 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

Table 31.ꢀFull-speed source electrical characteristics

Over full range of values specified in the Recommended Operating Conditions unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Driver characteristics

T_FR

Rise time

Fall time

--

4

--

20

ns

%

T_FF

T_FRFM

Differential rise and fall time T_FR/T_FF

matching

90

111.11

Clock timing

T_FDRATHS

T_FDRATE

T_RFI

Full-speed data rate

Frame interval

Average bit rate

--

11.9940

0.9995

--

12.0060

1.00005

42

Mb/s

ms

Consecutive frame interval No clock adjustment

difference

ms

Full-speed data timing

T_DJ1Source jitter total to next

--

-3.5

-4

--

3.5

4

ns

transition (including

frequency tolerance)

T_DJ2

Source jitter total for paired --

tran-sitions (including

frequency tolerance)

T_FDEOP

T_JR1

Source jitter for differential

transition to SE0 transition

--

-2

-18.5

-9

--

5

18.5

9

ns

Receiver jitter to next

transition

T_JR2

Receiver jitter to next

transition

T_FEOPT

T_FEOPR

Source SE0 interval of EOP --

160

82

--

175

--

ns

Receiver SE0 interval of

EOP

--

T_FST

Width of SE0 interval during --

differential transition

--

14

ns

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

36 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

Table 32.ꢀDevice event timing characteristics

Over full range of values specified in the Recommended Operating Conditions unless otherwise specified.

Symbol

T_SIGATT

Parameter

Conditions

Min

Typ

Max

Unit

Time from internal power

good to device pulling D

+/D- beyond V_IHZ(min)

(signaling attach)

--

100

ms

T_ATTDB

Debounce interval provided --

by USB system software

after attach

--

100

10

ms

T_2SUSP

Maximum time a device

can draw power > suspend

power when bus is

--

continuously in idle state

T_SUSAVGI

T_WTRSM

T_DRSMUP

T_RSMCY

Maximum duration of

suspend averaging interval

--

5

--

1

--

s

Period of idle bus before

device can initiate resume

Device must be remote-

wake-up enabled

ms

Duration of driving resume --

upstream

1

15

Resume recovery time

Provided by USB system

10

software

T_RSTRCY

T_IPD

Reset recovery time

--

2

--

10

ms

Inter-packet delay (for low/ --

full-speed)

bit times

T_RSPIPD1

T_RSPIPD2

T_DSETADDR

Inter-packet delay for device --

response with detachable

cable for low/full-speed

--

6.5

7.5

bit times

Inter-packet delay for device --

response with captive cable

for low/full-speed

SetAddress() completion

time

--

50

ms

T_DRQCMPLTNDTime to complete standard --

request with no data

T_DRETDATA1

Time to deliver first and

subsequent (except last)

data for standard request

--

500

T_DRETDATAN

T_HSRSPIPD2

Time to deliver last data for --

standard request

--

50

ms

--

Inter-packet delay for device --

response with captive cable

(high-speed)

192 bit

times +

52 ns

Reset Handshake Protocol

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

37 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

Table 32.ꢀDevice event timing characteristics...continued

Over full range of values specified in the Recommended Operating Conditions unless otherwise specified.

Symbol

F_FILTSE0

Parameter

Conditions

Min

Typ

Max

Unit

Time for which a suspended --

high-speed capable device

must see a continuous SE0

before beginning the high-

speed detection handshake

2.5

--

µs

T_WTRSTFS

Time for which a high-speed --

capable device operating in

non-suspended full-speed

must wait after start of SE0

before beginning the high-

speed detection handshake

2.5

--

3000

µs

T_WTREV

Time for which a high-speed --

capable device operating in

high-speed must wait after

start of SE0 before reverting

to full-speed

3.0

--

3.125

875

ms

µs

T_WTRSTHS

Time for which a device

must wait after reverting to

full-speed before sampling

the bus state for SE0 and

beginning the high-speed

detection handshake

--

100

T_UCH

Minimum duration of a

Chirp K from a high-speed

capable device within the

reset protocol

--

1.0

--

ms

T_UCHEND

Time after start of SE0 by

which a high-speed capable

device is required to have

completed its Chirp K within

the reset protocol

7.01

T_WTHS

Time after end of upstream --

chirp at which device enters

the high-speed default

state if downstream chirp is

detected

--

500

2.5

µs

T_WTFS

Time after end of upstream --

chirp at which device

1.0

ms

reverts to full-speed default

stat if no down-stream chirp

is detected

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

38 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

Table 33.ꢀLPM timing characteristics

Symbol

TL1_Residency

TL1_TokenRetry

Parameter

L1 residency

Conditions

Min

50

8

Typ

--

Max

>50

10

Unit

µs

--

Device delay before

transitioning to L1 after

transmitting ACK

--

µs

TL1_{HubDrvResume1}Host initiated L1 exit host

drives resume time

--

50 ±1

--

1200 ±1

--

µs

TL1_DevDrvResumeDevice initiated L1 exit

Device drives resume time

TL1_{ExitDevRecovery}L1 exit device recovery time --

10

60

--

µs

TL1_ExitLatency1

L1 exit latency (host

initiated)

--

1210

TL1_ExitLatency2

L1 exit latency (device

initiated)

--

70

--

1000

µs

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

39 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

8.7 Clock interface specifications

8.7.1 Single-ended clock input mode

Table 34.ꢀCMOS mode^[1]

Symbol

V_IH

V_IL

Parameter

Input high voltage

Input low voltage

Condition

Min

AVDD18 - 0.5

0

Typ

AVDD18

0

Max

1.98

0.4

Unit

V

--

V

[1] Typical input capacitance is approximately 2 pF and input resistance is >20 kΩ.

Table 35.ꢀPhase noise—2.4 GHz operation

Parameter

Fref = 26 MHz

Test Conditions

Offset = 1 kHz

Min

--

Typ

--

Max

-126

-137

-143

-123

-134

-140

Unit

dBc/Hz

Offset = 10 kHz

Offset = 100 kHz

Offset > 1 MHz

Offset = 1 kHz

Offset = 10 kHz

Offset = 100 kHz

Offset > 1 MHz

--

Fref = 38.4 MHz

--

8.7.2 Crystal specifications

Table 36.ꢀCrystal specifications

Parameter

Conditions

Min

--

Typical

26, 38.4

< ±10

<1.2

Min

--

Unit

MHz

ppm

mm

pF

Fundamental frequencies

Frequency tolerance

--

Over operating temperature

--

Over process at 25ºC

--

SMD and AT cut height

Load capacitor

--

10

--

Maximum series resistance

Resonance mode

--

60

--

Ω

--

A1,

--

Fundamental

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

40 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

8.8 Two-wire serial interface specifications

The 2-wire serial interface pins are powered by the VIO voltage supply.

See the specifications in Section 8.1.1 "VIO DC characteristics".

1

2

3

4

SCLK

SDA

TWSI Start

SER_CLK (SCLK)

SER_DAT (SDA)

TWSI Repeat Start

SER_CLK (SCLK)

SER_DAT (SDA)

TWSI Stop

SER_CLK (SCLK)

SER_DAT (SDA)

TWSI Write

SER_CLK (SCLK)

SER_DAT (SDA)

TWSI Read

Figure 14.ꢀTwo-wire serial interface signaling

8.9 UART (debug) interface specifications

The UART pins are powered by the VIO voltage supply.

See the specifications in Section 8.1.1 "VIO DC characteristics".

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

41 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

8.10 JTAG interface specifications

The JTAG test interface pins are powered by VIO voltage supply.

See the specifications in Section 8.1.1 "VIO DC characteristics".

T_{P_TCK}

T_{L_TCK}

T_{H_TCK}

TCK

T_{SU_TDI}

T_{HD_TDI}

TDI

TMS

T_{DLY_TDO}

TDO

Figure 15.ꢀJTAG timing diagram

Table 37.ꢀJTAG timing data^[1]

Over full range of values specified in the Recommended Operating Conditions unless otherwise specified.

Symbol

T_{P_TCK}

T_{H_TCK}

T_{L_TCK}

Parameter

TCK period

Conditions

Min

40

12

10

0

Typ

--

Max

--

Unit

ns

--

TCK high

TCK low

--

ns

--

ns

T_{SU_TDI}

T_{HD_TDI}

T_{DLY_TDO}

TDI, TMS to TCK setup time --

TDI, TMS to TCK hold time --

--

ns

--

ns

TCK to TDO delay

--

15

ns

[1] Does not apply to CPU JTAG enabled by the TMS_CPU pin.

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

42 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

9 Package information

9.1 Package thermal conditions

Table 38.ꢀThermal conditions—QFN

Symbol Parameter

Conditions

Typ

Unit

θ_JA

Thermal resistance

JEDEC

34.6

°C/W

Junction to ambient of

package.

3 x 4.5 inch, 4-layer PCB

no air flow

θ_JA= (T_J- T_A)/ P

JEDEC

33.9

32.8

32.3

9.4

°C/W

P = total power dissipation

3 x 4.5 inch, 4-layer PCB

1 meter/sec air flow

JEDEC

3 x 4.5 inch, 4-layer PCB

2 meter/sec air flow

JEDEC

3 x 4.5 inch, 4-layer PCB

3 meter/sec air flow

ψ_JT

Thermal characteristic

parameter¹

JEDEC

3 x 4.5 inch, 4-layer PCB

no air flow

Junction to top center of

package.

ψ_JT= (T_J- T_TOP)/P

T_TOP= temperature on top

center of package

ψ_JB

Thermal characteristic

parameter¹

JEDEC

21.4

°C/W

3 x 4.5 inch, 4-layer PCB

no air flow

Junction to top center of

package.

ψ_JT= (T_J- T_B)/P

T_B= power dissipation from

top center of package

θ_JC

Thermal resistance¹

JEDEC

23.4

21.5

°C/W

Junction to case of the

package

3 x 4.5 inch, 4-layer PCB

no air flow

θ_JC= (T_J- T_C)/ P_Top

P_Top= power dissipation

from top of package

Thermal resistance¹

θ_JB

JEDEC

Junction to board of

package

3 x 4.5 inch, 4-layer PCB

no air flow

θ_JB= (T_J- T_B)/ P_bottom

P_bottom= power dissipation

from bottom of package to

PCB surface

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

43 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

9.2 Package mechanical drawing

Figure 16.ꢀMechanical drawing of 48-pin QFN package

• The QFN package uses Epad size Option #2 only. See Section 9.1 "Package thermal

conditions" and Section 9.3 "Package marking".

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

44 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

9.3 Package marking

Figure 17 shows the marking and pin 1 location for 88W8801 parts.

Part Number, Package Code,

Environmental Code

xxx = package code

88W8801-NMD2

Lot Number

YYWW xx#

Country of Origin

Date code, Die revision, Assembly Plant

YYWW = Date Code

Country of Origin

(Contained in the mold ID or

marked as the last line on the

package)

(YY = Year, WW = Work Week)

xx = Revision number

# = Assembly Plant Code

E

Temperature code

none = commercial

E = extended

Pin 1 Location

I = Industrial

Note: The above drawing is not drawn to scale. The location of markings is approximate.

Figure 17.ꢀPackage marking and pin 1 location

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

45 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

10 Acronyms and abbreviations

Table 39.ꢀAcronyms and abbreviations

Acronym

A2DP

ABR

ACK

ADAS

ADC

AES

AFC

AFH

AGC

AIFS

AoA

Definition

Advanced Audio Distribution Profiles

Automatic Baud Rate

Acknowledgment

Advanced Driver Assistance Systems

Analog-to-Digital Converter

Advanced Encryption Standard

Automatic Frequency Correction

Adaptive Frequency Hopping

Automatic Gain Control

Arbitration Interframe Space

Angle of Arrival

AoD

Angle of Departure

AP

Access Point

APB

API

Advanced Peripheral Bus

Application Program Interface

Advanced Quad Flat Non-leaded Package

Advanced RISC Machine

Announcement Traffic Indication Message

Base Address Mask Register

Base Address Register

Baseband Processor Unit

Benzocyclobutene (flip chip bump process)

Basic Data Rate

aQFN

ARM

ATIM

BAMR

BAR

BBU

BCB

BDR

BER

BOM

BR

Bit Error Rate

Bill of Materials

Baud Rate

BSS

BSSID

BTU

BRF

BWQ

CBC

CBP

CCA

Basic Service Set

Basic Service Set Identifier

Bluetooth Baseband Unit

Bluetooth RF Unit

Bandwidth Queue

Cipher Block Chaining

Contention-Based Period

Clear Channel Assessment

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

46 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

Table 39.ꢀAcronyms and abbreviations...continued

Acronym Definition

CCK

Complementary Code Keying

Counter Mode CBC-MAC Protocol

Close Descriptor Enable

CCMP

CDE

CFP

Contention-Free Period

CFQ

Contention-Free Queue

CID

Connection Identifier

CIS

Card Information Structure

CPU Interface Unit

CIU

CMD

CMQ

CRC

CS

Command

Control Management Queue

Cyclic Redundancy Check

Card Select

CSMA/CA

CSMA/CD

CSU

Carrier Sense Multiple Access / Collision Avoidance

Carrier Sense Multiple Access / Collision Detection

Clocked Serial Unit

CTS

Clear to Send

DAC

Digital-to-Analog Converter

Differential Binary Phase Shift Keying

Device Controller Driver

DBPSK

DCD

DCE

Data Communication Equipment

Distributed Coordination Function

Direct Current Level Adjustment

Digital Contactless Bridge

DMA Controller Unit

DCF

DCLA

DCLB

DCU

DFS

Dynamic Frequency Selection

Distributed Interframe Space

Direct Memory Access

DIFS

DMA

dQH

Device Queue Head

DQPSK

DSM

DSP

Differential Quadrature Phase Shift Keying

Distribution System Medium

Digital Signal Processor

DSRC

dTD

Dedicated Short Range Communications

Linked List Transfer Descriptors

Delivery Traffic Indication Message

Digital Voltage Scaling Control

Extensible Authentication Protocol

DTIM

DVSC

EAP

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

47 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

Table 39.ꢀAcronyms and abbreviations...continued

Acronym Definition

EBRAM

ED

Extended Block Random Access Memory

Energy Detect

EDCA

EEPROM

EIFS

EMC

ERP-OFDM

ETSI

eWLP

FAE

Enhanced Distributed Channel Access

Electrically Erasable Programmable Read Only Memory

Extended Interframe Space

Electromagnetic Compatibility

Extended Rate PHY-Orthogonal Frequency Division Multiplexing

European Telecommunications Standards Institute

Embedded Wafer Level Package

Field Application Engineer

Federal Communications Commission

First In First Out

FCC

FIFO

FIPS

FIQ

Federal Information Processing Standards

Fast Interrupt Request

FW

Firmware

GATT

GCMP

GI

Generic Attribute Profile

Galois/Counter Mode Protocol

Guard Interval

GPIO

GPL

GPU

HID

General Purpose Input/Output

General Public License

General Purpose Input/Output Unit

Human Interface Device

HIU

Host Interface Unit

HOGP

HSP

HT

HID Over GATT Profile

Hands-Free Profile

High Throughput

HW

Hardware

I/Q

Inphase/Quadrature

IB

InBand

IBSS

ICE

Independent Basic Service Set

In-Circuit Emulator (or Emulation)

Interrupt Cause Register

ICR

ICU

Interrupt Controller Unit

ICV

Integrity Check Value

IE

Information Element

IEEE

Institute of Electrical and Electronics Engineers

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

48 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

Table 39.ꢀAcronyms and abbreviations...continued

Acronym Definition

IEMR

I/F

Interrupt Event Mask Register

Interface

IFS

Interframe Space

IMR

IPG

Interrupt Mask Register

Inter-Packet Gap

IPsec

IR

Internet Protocol Security

Infrared

IRQ

Interrupt Request

ISA

Instruction Set Architecture

Integrated Services Digital Network

Industrial, Scientific, and Medical

Interrupt Status Mask Register

Interrupt Status Register

Joint Electronic Device Engineering Council

Joint Test Action Group

Low Density Parity Check

Low Energy

ISDN

ISM

ISMR

ISR

JEDEC

JTAG

LDPC

LE

LED

LME

LNA

LPM

LQFN

LSb

Light Emitting Diode

Layer Management Entity

Low Noise Amplifier

Low Power Management

Low Quad Flat Non-leaded

Least Significant bit

LSB

LSP

LTE

Least Significant Byte

Low-Speed Peripheral

Long Term Evolution

MAC

MC

Media/Medium Access Controller

Memory Controller

MCS

MCU

MDI

MIB

Modulation and Coding Scheme

MAC Control Unit

Modem Data Interface

Management Information Base

Message Integrity Code

Media Independent Interface

Multiple Input Multiple Output

Million Instructions Per Second

MIC

MII

MIMO

MIPS

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

49 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

Table 39.ꢀAcronyms and abbreviations...continued

Acronym Definition

MLME

MMI

MAC Sublayer Management Entity

Modem Management Interface

MAC Management Protocol Data Unit

Memory Management Unit

MAC Protocol Data Unit

Most Significant bit

MMPDU

MMU

MPDU

MSb

MSB

Most Significant Byte

MSDU

MU-MIMO

MU-PPDU

MWS

MAC Service Data Unit

Multi-User MIMO

Multi-User PPDU

Mobile Wireless System

Multimedia Wireless System

NAV

NDP

NL

Network Allocation Vector

Null Data Packet

No Load

NPTR

OCB

OFDM

OID

Next Descriptor Pointer

Outside the Context of a BSS

Orthogonal Frequency Division Multiplexing

Object Identifier

OOB

OTP

P2P

PA

Out of Band

One Time Programmable

Peer-to-Peer

Power Amplifier

PAD

PBU

PC

Packet Assembler/Disassembler

Peripheral Bus Unit

Point Coordinator

PCB

PCF

PCI

Printed Circuit Board

Point Coordination Function

Peripheral Component Interconnect

PCI Express

PCIe

PCM

PDn

PDU

PEAP

PHY

PIFS

Pulse Code Modulation

Power Down

Protocol Data Unit

Protected EAP

Physical Layer

Priority Interframe Space

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

50 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

Table 39.ꢀAcronyms and abbreviations...continued

Acronym

Definition

PLL

Phase-Locked Loop

PLME

PMU

POST

PPDU

PPK

PPM

PSK

PTA

Physical Layer Management Entity

Power Management Unit

Power-On Self Test

PHY Protocol Data Unit

Per-Packet Key

Pulse Position Modulation

Pre-Shared Keys

Packet Traffic Arbitration

Pairwise Key

PWK

QAM

QFN

QoS

RA

Quadrature Amplitude Modulation

Quad Flat Non-leaded Package

Quality of Service

Receiver Address

RBDS

RDS

RF

Radio Broadcast Data System

Radio Data System

Radio Frequency

RFID

RIFS

RISC

ROM

RSSI

RTS

RTU

RU

Radio Frequency Identification

Reduced Interframe Space

Reduced Instruction Set Computer

Read Only Memory

Receiver Signal Strength Indication

Request to Send

General Purpose Timer Unit

Resource Unit

SA

Source Address

SAP

SCLK

SDA

SE

Service Access Point

Serial Interface Clock

Serial Interface Data

Secure Element

SFD

SIFS

SISO

SIU

Start of Frame Delimiter

Short Interframe Space

Single Input Single Output

Serial Interface Unit (UART)

System/Software JTAG Controller Unit

Switch Module

SJU

SM

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

51 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

Table 39.ꢀAcronyms and abbreviations...continued

Acronym Definition

SMI

Serial Management Interface

Signal-to-Noise Ratio

SNR

SO

Serial Out

SoC

System-on-Chip

SPDT

SPI

Single Pole Double Throw

Serial Peripheral Interface

Internal SRAM Unit

SQU

SRWB

SS

Serial Interface Read Write

Service Set

SSID

STA

Service Set Identifier

Station

STBC

SWD

SWP

TA

Space-Time Block Code

Serial Wire Debug

Single Wire Protocol

Transmitter Address

TBG

TBTT

TCM

TCP/IP

TCQ

TIM

Time Base Generator

Target Beacon Transmission Time

Tightly Coupled Memory

Transmission Control Protocol/Internet Protocol

Traffic Category Queue

Traffic Indication Map

TKIP

TPC

TQFP

TRPC

TSC

TSF

Temporal Key Integrity Protocol

Transmit Power Control

Thin Quad Flat Pack

Transmit Rate-based Power Control

TKIP Sequence Counter

Timing Synchronization Function

Target Wait Time

TWT

UART

UBM

UDP

UNII

VCO

VIF

Universal Asynchronous Receiver/Transmitter

Under Bump Metal

User Datagram Protocol

Unlicensed National Information Infrastructure

Voltage Controlled Oscillator

Voice Interface

VHT

WAP

Very High Throughput

Wireless Application Protocol

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

52 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

Table 39.ꢀAcronyms and abbreviations...continued

Acronym Definition

WAVE

WCI-2

WEP

Wireless Access in Vehicular Environments

Wireless Coexistence Interface 2

Wired Equivalent Privacy

WI

Wired Interface

Wi-Fi

Hardware implementation of IEEE 802.11 for wireless connectivity

Wireless Local Area Network

Wi-Fi Multimedia

WLAN

WMM

WPA

Wi-Fi Protected Access

WPA2

WPA2-PSK

WPA-PSK

XFQFN

XOSC

Wi-Fi Protected Access 2

Wi-Fi Protected Access 2-Pre-Shared Key

Wi-Fi Protect Access-Pre-Shared Key

Extra-Fine Quad Flat Non-leaded

Crystal Oscillator

11 Revision history

Table 40.ꢀRevision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

88W8801_SDS v.2.0

20201214

Product short data

sheet

202007006F01

88W8801 v.1.0

Modifications

• Changed 88W8801 document ID to 88W8801_SDS.

• Figure 17 "Package marking and pin 1 location": updated.

• Section 2 "Ordering information": moved to the beginning of the document (no other

changes).

88W8801 v.1.0

20200713

Product short data

sheet

-

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

53 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

12 Legal information

12.1 Data sheet status

Document status^[1][2]

Product status^[3]

Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product

development.

Preliminary [short] data sheet

Product [short] data sheet

Qualification

Production

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

12.2 Definitions

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — A draft status on a document indicates that the content is still

under internal review and subject to formal approval, which may result

in modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included in a draft version of a document and shall have no

liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local NXP

Semiconductors sales office. In case of any inconsistency or conflict with the

short data sheet, the full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes

no representation or warranty that such applications will be suitable

for the specified use without further testing or modification. Customers

are responsible for the design and operation of their applications and

products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications

and products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with

their applications and products. NXP Semiconductors does not accept any

liability related to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications or products, or

the application or use by customer’s third party customer(s). Customer is

responsible for doing all necessary testing for the customer’s applications

and products using NXP Semiconductors products in order to avoid a

default of the applications and the products or of the application or use by

customer’s third party customer(s). NXP does not accept any liability in this

respect.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product

is deemed to offer functions and qualities beyond those described in the

Product data sheet.

12.3 Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, NXP Semiconductors does not

give any representations or warranties, expressed or implied, as to the

accuracy or completeness of such information and shall have no liability

for the consequences of use of such information. NXP Semiconductors

takes no responsibility for the content in this document if provided by an

information source outside of NXP Semiconductors. In no event shall NXP

Semiconductors be liable for any indirect, incidental, punitive, special or

consequential damages (including - without limitation - lost profits, lost

savings, business interruption, costs related to the removal or replacement

of any products or rework charges) whether or not such damages are based

on tort (including negligence), warranty, breach of contract or any other

legal theory. Notwithstanding any damages that customer might incur for

any reason whatsoever, NXP Semiconductors’ aggregate and cumulative

liability towards customer for the products described herein shall be limited

in accordance with the Terms and conditions of commercial sale of NXP

Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to

make changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

54 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Security — Customer understands that all NXP products may be subject

to unidentified or documented vulnerabilities. Customer is responsible

for the design and operation of its applications and products throughout

their lifecycles to reduce the effect of these vulnerabilities on customer’s

applications and products. Customer’s responsibility also extends to other

open and/or proprietary technologies supported by NXP products for use

in customer’s applications. NXP accepts no liability for any vulnerability.

Customer should regularly check security updates from NXP and follow up

appropriately. Customer shall select products with security features that best

meet rules, regulations, and standards of the intended application and make

the ultimate design decisions regarding its products and is solely responsible

for compliance with all legal, regulatory, and security related requirements

concerning its products, regardless of any information or support that may

be provided by NXP. NXP has a Product Security Incident Response Team

(PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation,

reporting, and solution release to security vulnerabilities of NXP products.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor

tested in accordance with automotive testing or application requirements.

NXP Semiconductors accepts no liability for inclusion and/or use of non-

automotive qualified products in automotive equipment or applications. In

the event that customer uses the product for design-in and use in automotive

applications to automotive specifications and standards, customer (a) shall

use the product without NXP Semiconductors’ warranty of the product for

such automotive applications, use and specifications, and (b) whenever

customer uses the product for automotive applications beyond NXP

Semiconductors’ specifications such use shall be solely at customer’s own

risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,

damages or failed product claims resulting from customer design and use

of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

12.4 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

NXP — wordmark and logo are trademarks of NXP B.V.

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

55 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

Tables

Tab. 1.

Tab. 2.

Tab. 3.

Tab. 4.

Tab. 5.

Tab. 6.

Tab. 7.

Tab. 8.

Tab. 9.

Part order codes ............................................... 4

Tab. 21. DC electricals—3.3V operation (VDD33) ........ 25

Tab. 22. Wi-Fi receiver performance .............................27

Tab. 23. Wi-Fi transmitter performance .........................28

Tab. 24. Local oscillator ................................................ 28

Tab. 25. Current consumption .......................................29

Tab. 26. DC electricals—1.8V operation (VIO_SD) .......30

Tab. 27. DC electricals—3.3V operation (VIO_SD) .......30

Tab. 28. SDIO timing data .............................................32

Tab. 29. Electrical characteristics ..................................33

Tab. 30. High-speed source electrical characteristics ... 35

Tab. 31. Full-speed source electrical characteristics .....36

Tab. 32. Device event timing characteristics .................37

Tab. 33. LPM timing characteristics .............................. 39

Tab. 34. CMOS mode ................................................... 40

Tab. 35. Phase noise—2.4 GHz operation ....................40

Tab. 36. Crystal specifications .......................................40

Tab. 37. JTAG timing data ............................................ 42

Tab. 38. Thermal conditions—QFN ...............................43

Tab. 39. Acronyms and abbreviations ...........................46

Tab. 40. Revision history ...............................................53

Pin types ........................................................... 9

Pin list by number ........................................... 10

Wi-Fi radio interface ........................................11

RF font-end control interface ...........................12

General purpose I/O (GPIO) interface .............12

SDIO host interface .........................................13

USB host interface ..........................................13

Control interface ..............................................14

Tab. 10. Clock interface ................................................ 14

Tab. 11. Power-down .....................................................14

Tab. 12. Power supply and ground pins ........................15

Tab. 13. UART interface (debug) .................................. 15

Tab. 14. Two-wire serial interface ................................. 15

Tab. 15. JTAG interface .................................................16

Tab. 16. Configuration pins ........................................... 16

Tab. 17. Absolute maximum ratings ..............................23

Tab. 18. Recommended operating conditions ...............24

Tab. 19. DC electricals—1.8V operation (VIO) ..............25

Tab. 20. DC electricals—3.3V operation (VIO) ..............25

Figures

Fig. 1.

Fig. 2.

Fig. 3.

Fig. 4.

Fig. 5.

Application block diagram ................................. 1

Internal block diagram .......................................3

Part numbering scheme ....................................4

Signal diagram .................................................. 8

88W8801 pin assignment (package top

view) .................................................................. 9

Case 1 - Internal 1.1V and internal 1.8V ......... 17

Power-up sequence for case 1 and PDn

driven by host ................................................. 18

Power-up sequence for case 1 and PDn

tied to VDD33 ................................................. 19

Power options, case 2—Internal 1.1V,

Fig. 10. Power-up sequence for case 2 ....................... 22

Fig. 11.

Radio performance measurement points ........ 26

Fig. 12. SDIO protocol timing diagram—Normal

mode ............................................................... 31

Fig. 13. SDIO protocol timing diagram—High-speed

mode ............................................................... 31

Fig. 14. Two-wire serial interface signaling .................. 41

Fig. 15. JTAG timing diagram .......................................42

Fig. 16. Mechanical drawing of 48-pin QFN

Fig. 6.

Fig. 7.

Fig. 8.

Fig. 9.

package ...........................................................44

Fig. 17. Package marking and pin 1 location ............... 45

external 1.8V ...................................................20

88W8801_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 2 — 14 December 2020

56 / 57

NXP Semiconductors

88W8801_SDS

2.4 GHz Single-band 1x1 Wi-Fi 4 Solution

Contents

1

1.1

1.2

1.3

1.4

1.5

1.6

2

3

3.1

3.2

3.3

3.4

3.5

3.6

4

Product overview ................................................ 1

8.3

Wi-Fi radio specifications .................................26

Wi-Fi radio performance measurement ........... 26

Wi-Fi receiver performance ............................. 27

Wi-Fi transmitter performance ......................... 28

Local oscillator .................................................28

Current consumption ....................................... 29

SDIO host interface specifications ...................30

VIO_SD DC characteristics ............................. 30

VIO_SD DC characteristics - 1.8V

Applications ........................................................2

Wi-Fi key features ............................................. 2

Host interfaces ...................................................2

Operating characteristics ...................................2

General features ................................................2

Internal block diagram ....................................... 3

Ordering information .......................................... 4

Wi-Fi subsystem ..................................................5

IEEE 802.11 standards ......................................5

Wi-Fi MAC ......................................................... 5

Wi-Fi baseband ................................................. 6

Wi-Fi radio ......................................................... 6

Wi-Fi encryption .................................................6

Wi-Fi host interfaces ..........................................7

Pin information ....................................................8

Signal diagram ...................................................8

Pin assignment ..................................................9

Signal types .......................................................9

Pin list ..............................................................10

Pin description .................................................11

Pin states .........................................................11

Wi-Fi radio interface ........................................ 11

RF front-end control interface ..........................12

General purpose I/O (GPIO) interface ............. 12

SDIO 2.0 host interface ...................................13

USB 2.0 host interface .................................... 13

Control interface .............................................. 14

Clock interface .................................................14

Power-down .....................................................14

Power supply and ground pins ........................ 15

UART interface (debug) ...................................15

Two-wire serial interface ..................................15

JTAG interface .................................................16

Configuration pins ............................................16

Power information .............................................17

Leakage optimization .......................................17

Power options ..................................................17

Case 1 - Internal 1.1V and internal 1.8V ..........17

Power-up sequence for case 1 and PDn

8.3.1

8.3.2

8.3.3

8.3.4

8.4

8.5

8.5.1

8.5.1.1

operation ..........................................................30

VIO_SD DC characteristics - 3.3V

8.5.1.2

operation ..........................................................30

SDIO host interface specifications ...................31

USB 2.0 host interface specifications .............. 33

Clock interface specifications .......................... 40

Single-ended clock input mode ....................... 40

Crystal specifications .......................................40

Two-wire serial interface specifications ............41

UART (debug) interface specifications ............ 41

JTAG interface specifications .......................... 42

Package information .........................................43

Package thermal conditions .............................43

Package mechanical drawing ..........................44

Package marking .............................................45

Acronyms and abbreviations ...........................46

Revision history ................................................ 53

Legal information ..............................................54

8.5.2

8.6

8.7

8.7.1

8.7.2

8.8

8.9

8.10

9

9.1

9.2

9.3

10

4.1

4.2

4.3

4.4

4.5

4.5.1

4.5.2

4.5.3

4.5.4

4.5.5

4.5.6

4.5.7

4.5.8

4.5.9

4.5.10

4.5.11

4.5.12

4.5.13

4.6

11

12

5

5.1

5.2

5.2.1

5.2.1.1

driven by host ..................................................18

Power-up sequence for case 1 and PDn

5.2.1.2

tied to VDD33 ..................................................19

Case 2 - Internal 1.1V and external 1.8V .........20

Power-up sequence for case 2 ........................21

Absolute maximum ratings ..............................23

Recommended operating conditions .............. 24

Electrical specifications ................................... 25

GPIO interface specifications .......................... 25

VIO DC characteristics .................................... 25

VIO DC characteristics - 1.8V operation ..........25

VIO DC characteristics - 3.3V operation ..........25

RF front-end control interface specifications ....25

5.2.2

5.2.2.1

6

7

8

8.1

8.1.1

8.1.1.1

8.1.1.2

8.2

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 14 December 2020

Document identifier: 88W8801_SDS


型号：	88W8801-B0-NMDI/AK
厂家：	NXP
描述：	2.4 GHz Single-band 1x1 Wi-Fi 4 Solution
文件：	总57页 (文件大小：674K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

88W8801-B0-NMDI/AK [NXP]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E