88W8977-A1-EADE/AZ [NXP]
2.4 GHz/5 GHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2Combo SoC;型号: | 88W8977-A1-EADE/AZ |
厂家: | NXP |
描述: | 2.4 GHz/5 GHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2Combo SoC |
文件: | 总81页 (文件大小:945K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2
Combo SoC
Rev. 3 — 13 May 2021
Product short data sheet
1 Product overview
The 88W8977 System-on-Chip (SoC) is a highly integrated single-chip solution that
®
®
incorporates both Wi-Fi (2.4/5 GHz) and Bluetooth technology. The System-on-Chip
(SoC) provides both simultaneous and independent operation of the following:
• IEEE 802.11n compliant, 1x1 spatial stream with data rates up to MCS7 (150 Mbps)
• Bluetooth 5.2 (includes Bluetooth Low Energy (LE))
The SoC also provides 3-way coexistence for Wi-Fi, Bluetooth, and ZigBee operation,
and indoor location and navigation (802.11mc).
The internal coexistence arbitration and a Mobile Wireless Systems (MWS) serial
transport interface provide the functionality for connecting an external Long Term
Evolution (LTE) or ZigBee device. The device also supports a coexistence interface for
co-located Bluetooth/Wi-Fi device arbitration.
For security, the device supports high performance 802.11i security standards through
the implementation of the Advanced Encryption Standard (AES)/Counter Mode CBC-
MAC Protocol (CCMP), Wired Equivalent Privacy (WEP) with Temporal Key Integrity
Protocol (TKIP), AES/Cipher-Based Message Authentication Code (CMAC), WPA (AES),
and Wi-Fi Authentication and Privacy Infrastructure (WAPI) security mechanisms.
For video, voice, and multimedia applications, 802.11e Quality of Service (QoS) is
supported. The device also features 802.11h Dynamic Frequency Selection (DFS) for
detecting radar pulses when operating in the 5 GHz range.
Host interfaces include SDIO 3.0 and high-speed UART interfaces for connecting Wi-Fi
and Bluetooth technologies to the host processor.
The device is available in QFN and eWLP package options.
Figure 1 shows the functional block diagram of the device.
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
88W8977
SDIO 3.0
Antenna
Wi-Fi 5 GHz Tx/Rx
UART
Diplexer
Wi-Fi 2.4 GHz Tx/Rx and
Bluetooth Tx/Rx
PCM interface
GPIO interface
Supply voltages
Power-down
XTAL_IN
External radio coexistence
XTAL_OUT
Figure 1.ꢁ88W8977 functional block diagram
1.1 Applications
Smart home applications:
• Wireless home audio and video entertainment systems
• Wearables
• Internet of Things (IoT) gateways
• Mobile routers
Mobile applications:
• Wi-Fi and Bluetooth enabled smart phones and tablets
• Personal computing systems including notebooks and ultrabooks
1.2 Wi-Fi key features
• Support 802.11 a/b/g/n
• Dual band: 2.4 GHz and 5 GHz
• Single stream 802.11n with 20 MHz and 40 MHz channels
• Up to MCS7 data rates (150 Mbps)
• Support 802.11mc for location
• Security: support WPA/WPA2 mixed mode, WPA2 and WPA3 security standards
1.3 Bluetooth key features
• Bluetooth 5.2 support
• Direction Finding—Connection-oriented Angle of Arrival (AoA)
• PCM audio interface
• Security: AES
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
2 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
1.4 Host interfaces
Wi-Fi and Bluetooth host interface options
Wi-Fi
Bluetooth
UART
SDIO 3.0
SDIO 3.0
SDIO 3.0
1.5 Operating characteristics
• Supply voltage: 2.2V, 1.8V, and 1.05V
• Operating temperature
– Extended: -30 to 85°C
– Industrial: -40 to 85°C
1.6 General features
• Package options
– 68-pin QFN (8 mm x 8 mm)
– 74-bump eWLP (4.674 mm x 3.46 mm)
• Simultaneous Wi-Fi and Bluetooth operation, including Bluetooth Low Energy (LE)
• Dynamic Rapid Channel Switching (DRCS) for simultaneous operation in 2.4 GHz and
5 GHz bands
• Power saving features
– Efficient power management system
– On-chip LDO for 1.05V generation from 1.8V supply
– Sleep and standby modes
– Deep-sleep mode
• Independent ARM-based Wi-Fi and Bluetooth CPUs
• Independent two-channel Direct Memory Access (DMA)
• Memory:
– Internal SRAM
– Boot ROM
– OTP memory to store the MAC address and calibration data
• Peripheral Interface
– General-Purpose I/O (GPIO) interface
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
3 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
1.7 Internal block diagram
Wi-Fi 5 GHz Tx/Rx
Wi-Fi 2.4 GHz Tx
T/R
switch
D
i
p
l
1x1
Wi-Fi 4 MAC/
Baseband (802.11n)
1x1
Wi-Fi 4 RF
(802.11n)
Wi-Fi CPU
SDIO 3.0
2.4G/5G/
Bluetooth Tx/Rx
e
x
e
r
Wi-Fi 2.4 GHz Rx
and Bluetooth Rx
S
P
3
T
UART
PCM
Bluetooth/
Bluetooth LE
Baseband
Bluetooth
CPU
Bluetooth RF
Bluetooth Tx
External radio
coexistence
Supply
voltages
Power regulator
OTP
Coexistence
Figure 2.ꢁ88W8977 internal block diagram
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
4 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
2 Ordering information
88W8977-xx-xxxE/xx
Packing code
Temperature code
E = Extended
I = Industrial
Part number
Revision number
Package code
Figure 3.ꢁPart numbering scheme
Table 1.ꢁPart Order Codes
Part Order Code
Package Type
Packing
88W8977-A1-NMVE/AK
88W8977-A1-NMVE/AZ
88W8977-A1-NMVI/AK
88W8977-A1-NMVI/AZ
88W8977-A1-EADE/AZ
68-pin MQFN - 8 x 8 x 0.85 mm, with 0.4 mm pitch
68-pin MQFN - 8 x 8 x 0.85 mm, with 0.4 mm pitch
68-pin MQFN - 8 x 8 x 0.85 mm, with 0.4 mm pitch
68-pin MQFN - 8 x 8 x 0.85 mm, with 0.4 mm pitch
74-bump eWLP - 4.674 x 3.46 x 0.76 mm, with 0.4 mm pitch
Tray
Tape and Reel
Tray
Tape and Reel
Tape and Reel
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
5 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
3 Wi-Fi subsystem
3.1 IEEE 802.11 standards
• 802.11b data rates of 1 and 2 Mbps
• 802.11b data rates of 5.5 and 11 Mbps
• 802.11a/g data rates 6, 9, 12, 18, 24, 36, 48, and 54 Mbps for multimedia content
transmission
• 802.11g/b performance enhancements
• 802.11n with maximum data rates up to 72 Mbps (20 MHz channel), 150 Mbps (40
MHz channel)
• 802.11d international roaming
• 802.11e quality of service
• 802.11h transmit power control
• 802.11h DFS radar pulse detection
• 802.11i enhanced security
• 802.11k radio resource measurement
• 802.11mc precise indoor location and navigation
• 802.11n block acknowledgement extension
• 802.11r fast hand-off for AP roaming
• 802.11u Hotspot 2.0 (STA mode only)
• 802.11v TIM frame transmission/reception
• 802.11w protected management frames
• Fully supports clients (stations) implementing IEEE Power Save mode
3.2 Wi-Fi MAC
• Simultaneous peer-to-peer and Infrastructure Modes
• RTS/CTS for operation under DCF
• Hardware filtering of 32 multicast addresses and duplicate frame detection for up to 32
unicast addresses
• On-chip transmit and receive FIFO for maximum throughput
• Open System and Shared Key Authentication services
• A-MPDU Rx (de-aggregation) and transmit (aggregation)
• 20/40 MHz coexistence
• Reduced Inter-Frame Spacing (RIFS) receive
• Management information base counters
• Radio resource measurement counters
• Quality of service queues
• Block acknowledgement extension
• Dynamic frequency selection
• TIM frame transmission/reception
• Multiple-BSS/Station
• Transmit rate adaptation
• Transmit power control
• Long and short preamble generation on a frame-by-frame basis for 802.11b frames
• Mobile hotspot
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
6 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
3.3 Wi-Fi baseband
• 802.11n 1x1 SISO
• Backward compatibility with legacy 802.11a/g/b technology
• 2.4 GHz Wi-Fi and Bluetooth share LNA for receive operation
• PHY data rates up to 150 Mbps
• 20 MHz bandwidth/channel, 40 MHz bandwidth/channel, upper/lower 20 MHz packets
in 40 MHz channel, 20 MHz duplicate legacy packets in 40 MHz channel mode
operation
• Modulation and Coding Scheme (MCS)—MCS0~7
• Dynamic frequency selection (radar detection)
– Enhanced radar detection for long and short pulse radar
– Enhanced AGC scheme for DFS channel
– Compliance with Japan DFS requirements for W53 and W56
• Radio resource measurement
• Optional 802.11n SISO features:
– 20/40 MHz coexistence
– One spatial stream STBC reception
– Short guard interval
– RIFS on receive path for 802.11n packets
– 802.11n greenfield Tx/Rx
• Wi-Fi indoor locationing (802.11mc)
• Power save features
3.4 Wi-Fi radio
• Integrated direct-conversion radio
• 20 and 40 MHz channel bandwidths
• Shared Wi-Fi/Bluetooth receive input scheme for 2.4 GHz band
Wi-Fi receive path
• Direct conversion architecture eliminates need for external SAW filter
• On-chip gain selectable LNA with optimized noise figure and power consumption
• High dynamic range AGC function in receive mode
Wi-Fi transmit path
• Internal PA with power control
• Optimized transmit gain distribution for linearity and noise performance
Wi-Fi local oscillator
• Fine channel step
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
7 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
3.5 Wi-Fi encryption
• WEP 64- and 128-bit encryption with hardware TKIP processing (WPA)
• AES/CCMP hardware implementation as part of the 802.11i security standard (WPA2)
• Enhanced AES engine performance
• AES/Cipher-based Message Authentication Code (CMAC) as part of the 802.11w
security standard
• Simultaneous Authentication of Equals (SAE) WPA3
• WLAN Authentication and Privacy Infrastructure (WAPI)
3.6 Wi-Fi host interfaces
• SDIO 3.0
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
8 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
4 Bluetooth subsystem
4.1 Bluetooth
• Bluetooth 5.2
• Bluetooth Class 2
• Bluetooth Class 1
• Single-ended, shared Tx/Rx path for Wi-Fi/Bluetooth
• Shared LNA for Wi-Fi/Bluetooth
• PCM interface for voice applications
• Baseband and radio BDR and EDR packet types—1 Mbps (GFSK), 2 Mbps ( /4-
DQPSK), and 3 Mbps (8DPSK)
• Fully functional Bluetooth baseband—AFH, forward error correction, header error
control, access code correlation, CRC, encryption bit stream generation, and whitening
• Adaptive Frequency Hopping (AFH) using Packet Error Rate (PER)
• Interlaced scan for faster connection setup
• Simultaneous active ACL connection support
• Automatic ACL packet type selection
• Full master and slave piconet support
• Scatternet support
• Standard SDIO and UART HCI transport layer
• HCI layer to integrate with profile stack
• SCO/eSCO links with hardware accelerated audio signal processing and hardware
supported PPEC algorithm for speech quality improvement
• All standard SCO/eSCO voice coding
• All standard pairing, authentication, link key, and encryption operations
• Standard Bluetooth power saving mechanisms (i.e., hold, sniff modes, and sniff-
subrating)
• Enhanced Power Control (EPC)
• Channel Quality Driven Data Rate (CQDDR)
• Wideband Speech (WBS) support (1 WBS link)
• Encryption (AES) support
• LTE/MWS coexistence
4.2 Bluetooth Low Energy (LE)
• Broadcaster, observer, central, and peripheral roles
• Supports link layer topology to be master and slave (connects up to 16 links)
• Wi-Fi/Bluetooth Coexistence Arbiter (BCA) capability
• Shared RF with Bluetooth BDR/EDR
• Encryption (AES) support
• Intelligent Adaptive Frequency Hopping (AFH)
• Bluetooth LE Privacy 1.2
• Bluetooth LE Secure Connection
• Bluetooth LE Data Length Extension
• Bluetooth LE Advertising Extension
• Direction Finding—Connection-oriented Angle of Arrival (AoA)
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
9 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
4.3 Bluetooth host interfaces
• SDIO 3.0
• High-speed UART
4.4 PCM interface
• Master or slave mode
• PCM bit width size of 8 bits or 16 bits
• Up to 4 slots with configurable bit width and start positions
• Short frame and long frame synchronization
• Tri-state PCM interface capability
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
10 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
5 Pin information
5.1 Signal diagram
Note: Signals may be muxed. See Linktext-Section_number-page (BRF_ANT signal is
muxed with RF_TR_2 pin; Bluetooth external coexistence signals are muxed with both
GPIO[11:8] and SD_DAT[3:0] pins).
88W8977
RF_TR_2
Wi-Fi radio interface
RF_TR_5
SD_CLK
BRF_ANT
(shared with RF_TR_2 pin)
SDIO interface
UART interface
SD_CMD
Bluetooth radio interface
SD_DAT[3:0]
RF_CNTL0_N
RF_CNTL1_P
RF_CNTL2_N
RF_CNTL3_P
UART_SIN
RF front-end control
interface
UART_SOUT
UART_RTSn
UART_CTSn
PCM_SYNC
PCM_CLK
PCM_MCLK
PCM_DIN
UART_LTE_SIN
LTE external
coexistence interface
PCM interface
UART_LTE_SOUT
PCM_DOUT
BT_REQ
BT_STATE
BT_FREQ
DVSC[0]
DVSC[1]
Power management
interface
Bluetooth external
coexistence interface
BT_GRANTn
XTAL_IN
GPIO[15:0]
GPIO interface
JTAG interface
XTAL_OUT
SLP_CLK_IN
Clock interface
Power-down
XOSC_EN
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
PDn
Figure 4.ꢁ88W8977 signal diagram
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
11 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
5.2 Pin assignment - 68-pin QFN package option
Note: Pins may have muxed signals. See Section 5.4 "Pin description".
GPIO[6]
GPIO[4]
GPIO[2]
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
34
33
32
NC
NC
NC
31
30
29
28
27
26
25
24
23
22
21
AVDD18
GPIO[3]
GPIO[1]
RF_TR_5
VPA
VPA
NC
VIO
LDO_VIN
LDO_VOUT
VCORE
AVDD18
88W8977
SD_CMD
VIO_SD
RF_TR_2/BRF_ANT
NC
SD_CLK
VCORE
NC
SD_DAT0]
SD_DAT[1]
AVDD18
SD_DAT[2]
SD_DAT[3]
NC
20 NC
19
18
NC
NC
Figure 5.ꢁPin assignement for 68-pin package option (top view)
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
12 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
5.3 Pad locations - 74-bump eWLP
1
2
3
4
5
6
7
8
A
A2
A3
A4
A5
A6
A7
A8
B1
C1
D1
E1
F1
B2
C2
D2
E2
F2
B3
C3
D3
E3
F3
G3
H3
J3
B4
C4
D4
E4
F4
B5
C5
D5
E5
F5
B6
C6
D6
E6
F6
G6
H6
J6
B7
C7
D7
E7
F7
B8
C8
D8
E8
F8
G8
H8
J8
B
C
D
E
F
G5
H5
G7
H7
G
H2
J2
H4
J4
H
J1
J
K
K3
L3
L1
L2
L4
L5
L6
L7
L8
L
Non-bump-side view
Figure 6.ꢁPad locations—74-bump WLCSP (Non-bump-side view, bumps down) [1]
[1] Alphanumeric designations are approximations to the grid.
Table 2.ꢁPad locations—74-bump eWLP[1]
Pin Name
Flip Chip Pad Location Relative to
Die Center (non-bump-side view)
Alpha-Numeric
Designation
X
Y
VIO
A2
A3
A4
-1000.0
-600.0
-200.0
2000.0
2000.0
2000.0
VSS
LDO_VIN
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
13 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Table 2.ꢁPad locations—74-bump eWLP[1]...continued
Flip Chip Pad Location Relative to
Die Center (non-bump-side view)
Alpha-Numeric
Designation
Pin Name
X
Y
VIO_SD
SD_DAT[0]
SD_DAT[1]
VSS
A5
A6
A7
A8
200.0
2000.0
2000.0
2000.0
2000.0
600.0
1000.0
1400.00
GPIO[5]
B1
B2
B3
B4
B5
B6
B7
B8
-1400.0
-1000.0
-600.0
-200.0
200.0
1600.0
1600.0
1600.0
1600.0
1600.0
1600.0
1600.0
1600.0
GPIO[6]
GPIO[3]
LDO_VOUT
VCORE
SD_CLK
SD_DAT[2]
SD_DAT[3]
600.0
1000.0
1400.00
AVDD18
GPIO[7]
GPIO[4]
GPIO[2]
GPIO[1]
SD_CMD
SLP_CLK_IN
VSS
C1
C2
C3
C4
C5
C6
C7
C8
-1400.0
-1000.0
-600.0
-200.0
200.0
1200.0
1200.0
1200.0
1200.0
1200.0
1200.0
1200.0
1200.0
600.0
1000.0
1400.00
AVDD18
AVSS
D1
D2
D3
D4
D5
D6
D7
D8
-1400.0
-1000.0
-600.0
-200.0
200.0
800.0
800.0
800.0
800.0
800.0
800.0
800.0
800.0
PDn
GPIO[14]
GPIO[15]
GPIO[8]
GPIO[0]
VIO
600.0
1000.0
1400.00
XTAL_IN
XTAL_OUT
DNC
E1
E2
E3
E4
E5
E6
-1400.0
-1000.0
-600.0
-200.0
200.0
400.0
400.0
400.0
400.0
400.0
400.0
DNC
UART_LTE_SOUT
GPIO[9]
600.0
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
14 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Table 2.ꢁPad locations—74-bump eWLP[1]...continued
Flip Chip Pad Location Relative to
Die Center (non-bump-side view)
Alpha-Numeric
Designation
Pin Name
X
Y
GPIO[10]
GPIO[13]
E7
E8
1000.0
1400.00
400.0
400.0
AVDD18
AVSS
F1
F2
F3
F4
F5
F6
F7
F8
-1400.0
-1000.0
-600.0
-200.0
200.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
AVDD18
AVSS
UART_LTE_SIN
GPIO[11]
GPIO[12]
VIO_RF
600.0
1000.0
1400.00
AVSS
G3
G5
G6
G7
G8
-600.0
200.0
-400.0
-400.0
-400.0
-400.0
-400.0
RF_CNTL0_N
RF_CNTL1_P
RF_CNTL2_N
RF_CNTL3_P
600.0
1000.0
1400.00
AVDD18
AVSS
H2
H3
H4
H5
H6
H7
H8
-1000.0
-600.0
-200.0
200.0
-800.0
-800.0
-800.0
-800.0
-800.0
-800.0
-800.0
VCORE
AVSS
AVSS
600.0
AVSS
1000.0
1400.0
AVDD18
AVSS
AVSS
AVSS
AVSS
AVSS
AVDD18
J1
J2
J3
J4
J6
J8
-1400.0
-1000.0
-600.0
-200.0
600.0
-1200.0
-1200.0
-1200.0
-1200.0
-1200.0
-1200.0
1400.0
VPA
K3
-600.00
-1600.0
NC
L1
L2
L3
L4
L5
-1400.0
-1000.0
-600.0
-200.0
200.0
-2000.0
-2000.0
-2000.0
-2000.0
-2000.0
RF_TR_5
DNC
RF_TR_2
AVDD18
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
15 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Table 2.ꢁPad locations—74-bump eWLP[1]...continued
Flip Chip Pad Location Relative to
Die Center (non-bump-side view)
Alpha-Numeric
Designation
Pin Name
X
Y
AVDD18
AVSS
NC
L6
L7
L8
600.0
1000.0
1400.0
-2000.0
-2000.0
-2000.0
[1] Alphanumeric designations are approximations to the grid shown in Figure 6.
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
16 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
5.4 Pin description
5.4.1 Pin types
Table 3.ꢁPin types
Pin type
Description
I/O
I
Digital input/output
Digital input
Digital output
Analog input
Analog output
No connect
Do not connect
Power
O
A, I
A,O
NC
DNC
Power
Ground
Ground
5.4.2 Pin states
The pin state information provided in this section is defined as follows:
• After firmware is downloaded, pads like GPIO and RF control are programmed in
functional mode per the functionality of the pins
• The Hardware State (HW State) at power-on may differ based on the pin muxing/strap
setting. The HW State is the pin state at power-on after boot code finishes and before
firmware download begins (firmware may change the pin state). For example, for
UART_RTSn and UART_SOUT, the boot code will enable the UART interface, making
the HW states output high and output low, respectively.
• PD State denotes the power-down state in default configuration. Many pads have
programmable power-down values, which can be set by firmware.
• PD Prog denotes whether the power-down state is programmable or not
• PU denotes whether the pull-up is programmable or not
• PD denotes whether the pull-down is programmable or not
• Pull-up and pull-down are only effective when the pad is in input mode.
• For SDIO, once the command is received from the host, the pads are configured
accordingly
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
17 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
5.4.3 General Purpose I/O (GPIO)/LED interface
Table 4.ꢁGeneral purpose I/O/LED interface
Pin Name
Supply
No Pad Power Reset
HW State PD State PD Prog Internal PU/ PU
PD
PD
State
State
GPIO[15]
VIO
tristate
input
input
tristate
yes
nominal PU
yes
yes
GPIO Mode: GPIO[15] (input/output)
JTAG Mode: JTAG_TMS, JTAG controller select (input)
GPIO[14] VIO tristate input
GPIO Mode: GPIO[14] (input/output)
JTAG Mode: JTAG_TCK, JTAG test clock (input)
GPIO[13] VIO tristate
GPIO Mode: GPIO[13] (input/output)
GPIO[12] VIO tristate
GPIO Mode: GPIO[12] (input/output)
GPIO[11] VIO tristate
input
tristate
yes
nominal PU
yes
yes
input
input
input
input
input
input
tristate
tristate
tristate
yes
yes
yes
nominal PU
nominal PU
weak PU
yes
yes
no
yes
yes
no
GPIO Mode: GPIO[11] (input/output)
UART Mode: UART_RTSn (output) (active low)
Bluetooth External Coexistence Mode: BT_REQ. See Section 5.4.6 "Bluetooth external coexistence interface".
GPIO[10] VIO tristate input input tristate yes nominal PU yes
yes
GPIO Mode: GPIO[10] (input/output)
UART Mode: UART_CTSn (input) (active low)
Bluetooth External Coexistence Mode: BT_GRANTn. See Section 5.4.6 "Bluetooth external coexistence interface".
GPIO[9] VIO tristate input input tristate yes nominal PU no
no
no
no
GPIO Mode: GPIO[9] (input/output)
UART Mode: UART_SIN (input)
Bluetooth External Coexistence Mode: BT_STATE. See Section 5.4.6 "Bluetooth external coexistence interface".
GPIO[8] VIO tristate input input tristate yes weak PU no
GPIO Mode: GPIO[8] (input/output)
UART Mode: UART_SOUT (output)
Bluetooth External Coexistence Mode: BT_FREQ. See Section 5.4.6 "Bluetooth external coexistence interface"
GPIO[7]
VIO
tristate
input
input
input
input
input
input
tristate
tristate
tristate
yes
yes
yes
nominal PU
nominal PU
weak PU
no
GPIO Mode: GPIO[7] (input/output)
PCM Mode: PCM_SYNC (input/output)
• Output if master
• Input if slave
GPIO[6]
VIO
tristate
yes
yes
yes
yes
GPIO Mode: GPIO[6] (input/output)
PCM Mode: PCM_CLK (input/output)
• Output if master
• Input if slave
GPIO[5]
VIO
tristate
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
18 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Table 4.ꢁGeneral purpose I/O/LED interface...continued
Pin Name Supply No Pad Power Reset
HW State PD State PD Prog Internal PU/ PU
PD
PD
State
State
input
input
GPIO Mode: GPIO[5] (input/output)
PCM Mode: PCM_DOUT (output)
GPIO[4]
VIO
tristate
input
input
tristate
tristate
yes
yes
nominal PU
weak PU
no
no
GPIO Mode: GPIO[4] (input/output)
PCM Mode: PCM_DIN (input)
GPIO[3]
VIO
tristate
yes
yes
GPIO Mode: GPIO[3] (input/output)
Power Management Mode: DVSC[1]
Digital voltage scaling control (output)
JTAG Mode: JTAG_TDO, JTAG test data (output)
GPIO[2]
VIO
tristate
input
input
tristate
tristate
yes
yes
weak PU
yes
yes
GPIO Mode: GPIO[2] (input/output)
Power Management Mode: DVSC[0]
Digital voltage scaling control (output)
JTAG Mode: JTAG_TDI, JTAG test data (input)
GPIO[1]
GPIO Mode: GPIO[1] (input/output)
GPIO[0] VIO tristate
GPIO Mode: GPIO[0] (input/output)
VIO
tristate
input
input
weak PU
weak PU
no
no
no
output
output
drive low yes
yes
Oscillator Mode: XOSC_EN/CLK_REQ (output) (active high)
0 = disable external oscillator
1 = enable external oscillator
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
19 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
5.4.4 RF front-end control interface
Table 5.ꢁRF front-end control interface
No Pad
Reset
State
Internal
PU/PD
Pin Name
Supply
Power
State
HW State PD State
PD Prog
yes
PU
no
PD
no
RF_CNTL0_N
VIO_RF
tristate
input
output
drive low
weak PU
RF Control 0—RF Control Output Low (output)
This pin is used as a configuration pin: CON[0] (input)
See Section 5.5 "Configuration pins".
RF_CNTL1_P
RF Control 1—RF Control Output High (output)
RF_CNTL2_N VIO_RF tristate input
VIO_RF
tristate
input
output
output
drive high
drive low
yes
yes
weak PU
weak PU
no
no
no
no
RF Control 2—RF Control Output Low (output)
This pin is used as a configuration pin: CON[1] (input)
See Section 5.5 "Configuration pins".
RF_CNTL3_P
VIO_RF
tristate
input
output
drive high
yes
weak PU
no
no
RF Control 3—RF Control Output High (output)
5.4.5 Wi-Fi/Bluetooth radio interface
Table 6.ꢁWi-Fi/Bluetooth radio interface
Pin Name
Type
Supply
AVDD18
Description
RF_TR_2 /
A, I/O
Wi-Fi: Wi-Fi Transmit/Receive (2.4 GHz)
Bluetooth: Bluetooth Transmit/Receive
BRF_ANT
RF_TR_5
A, I/O
AVDD18
Wi-Fi Transmit/Receive (5 GHz)
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
20 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
5.4.6 Bluetooth external coexistence interface
Table 7.ꢁBluetooth external coexistence interface
Pin Name
Supply
No Pad Power
State
Reset
State
HW
State
PD State
PD Prog Internal PU/ PU
PD
PD
BT_GRANTn
VIO
tristate
input
input
tristate
yes
nominal PU yes
nominal PU yes
nominal PU yes
nominal PU yes
yes
Coexistence Mode: BT_GRANTn input (active low)
SDIO Mode: SD_DAT[0]. See Section 5.4.7 "SDIO host interface".
GPIO Mode: GPIO[10]. See Section 5.4.3 "General Purpose I/O (GPIO)/LED interface".
BT_STATE VIO tristate output output tristate yes
Coexistence Mode: BT_STATE output
SDIO Mode: SD_DAT[2]. See Section 5.4.7 "SDIO host interface".
GPIO Mode: GPIO[9]. See Section 5.4.3 "General Purpose I/O (GPIO)/LED interface".
BT_REQ VIO tristate output output tristate yes
Coexistence Mode: BT_REQ output
SDIO Mode: SD_DAT[3]. See Section 5.4.7 "SDIO host interface".
GPIO Mode: GPIO[11]. See Section 5.4.3 "General Purpose I/O (GPIO)/LED interface".
BT_FREQ VIO tristate output output tristate yes
Coexistence Mode: BT_FREQ output
SDIO Mode: SD_DAT[1]. See Section 5.4.7 "SDIO host interface".
GPIO Mode: GPIO[8]. See Section 5.4.3 "General Purpose I/O (GPIO)/LED interface".
NOTE: Bluetooth external coexistence pin functions are unavailable when the SDIO interface signals are used.
yes
yes
yes
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
21 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
5.4.7 SDIO host interface
Table 8.ꢁSDIO host interface
Pin Name
Supply
No Pad Power
State
Reset
State
HW State PD State PD Prog Internal PU/ PU
PD
PD
SD_CLK
VIO_SD
tristate
input
input
input
input
tristate
tristate
tristate
no
no
no
nominal PU
nominal PU
nominal PU
yes
yes
yes
yes
SDIO 4-bit Mode: Clock input
SDIO 1-bit Mode: Clock input
SD_CMD
VIO_SD
tristate
input
yes
yes
SDIO 4-bit Mode: Command/response (input/output)
SDIO 1-bit Mode: Command line
SD_DAT[3]
VIO_SD
tristate
input
SDIO 4-bit Mode: Data line Bit[3]
SDIO 1-bit Mode: Reserved
Bluetooth External Coexistence Mode: BT_REQ. See Section 5.4.6 "Bluetooth external coexistence interface".
SD_DAT[2] VIO_SD tristate input input tristate no nominal PU yes
yes
yes
yes
SDIO 4-bit Mode: Data line Bit[2] or read wait (optional)
SDIO 1-bit Mode: Read wait (optional)
Bluetooth External Coexistence Mode: BT_STATE. See Section 5.4.6 "Bluetooth external coexistence interface".
SD_DAT[1] VIO_SD tristate input input tristate no nominal PU yes
SDIO 4-bit Mode: Data line Bit[1]
SDIO 1-bit Mode: Interrupt
Bluetooth External Coexistence Mode: BT_FREQ. See Section 5.4.6 "Bluetooth external coexistence interface".
SD_DAT[0] VIO_SD tristate input input tristate no nominal PU yes
SDIO 4-bit Mode: Data line Bit[0]
SDIO 1-bit Mode: Data line
Bluetooth External Coexistence Mode: BT_GRANT. See Section 5.4.6 "Bluetooth external coexistence interface".
NOTE: SDIO pin functions are unavailable when the Bluetooth external coexistence interface signals are used.
5.4.8 UART host interface
Table 9.ꢁUART host interface (MFP)
NOTE: Pins may be Multi-Functional Pins (MFP). See pin descriptions for functional modes.
Pin Name
Type
Supply
VIO
Description
UART_SIN
UART_SOUT
UART_RTSn
I
UART serial input signal - GPIO[9] input/output
UART serial output signal - GPIO[8] input/output
O
O
VIO
VIO
UART request-to-send output signal . Active low - GPIO[11] input/
output
UART_CTSn
I
VIO
UART clear-to-send input signal - Active low - GPIO[10] input/output
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
22 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
5.4.9 LTE external coexistence interface
Table 10.ꢁLTE interface
Pin Name
Supply
No Pad
Reset
HW
PD
PD Prog Internal PU
PU
PD
Power State State
State
State
UART_LTE_SIN
VIO
tristate
tristate
input
input
input
input
tristate
tristate
yes
yes
weak PU
weak PU
yes
yes
UART_LTE_SIN (input)
UART_LTE_SOUT
VIO
yes
yes
UART_LTE_SOUT (output)
5.4.10 PCM interface
Table 11.ꢁPCM interface pins (MFP)
NOTE: Pins may be Multi-Functional Pins (MFP). See pin descriptions for functional modes.
Pin Name
Type
I
Supply
VIO
Description
PCM_DIN
Receive PCM input. GPIO[4] input/output
Transmit PCM output. GPIO[5] input/output
PCM_DOUT
PCM_SYNC
O
VIO
I/O
VIO
PCM frame sync. GPIO[7] input/output
• Output if master
• Input if slave
PCM_CLK
I/O
VIO
PCM data clock. GPIO[6] input/output
• Output if master
• Input if slave
5.4.11 Power management interface
Table 12.ꢁPower management interface pins (MFP)
NOTE: Pins may be Multi-Functional Pins (MFP). See pin descriptions for functional modes.
Pin Name
DVSC[1]
DVSC[0]
Type
O
Supply
VIO
Description
Digital voltage scaling control output signal. GPIO[3] input/output
Digital voltage scaling control output signal. GPIO[2] input/output
O
VIO
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
23 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
5.4.12 Power supply and ground pins
Table 13.ꢁPower supply and ground pins
Pin Name
VCORE
VIO
Type
Description
Power
Power
Power
Power
Power
Power
Power
Power
Ground
Ground
NC
1.05V Core Power Supply
1.8V/2.5V/3.3V Digital I/O Power Supply
1.8V/3.3V Digital I/O SDIO Power Supply
1.8V/3.3V Analog I/O RF Power Supply
1.8V Analog Power Supply
2.2V Analog Power Supply
LDO Voltage Input (1.8V)
LDO Voltage Output
VIO_SD
VIO_RF
AVDD18
VPA
LDO_VIN
LDO_VOUT
AVSS
Ground
VSS
Ground
NC
No Connected
DNC
DNC
Do Not Connect
Do not connect these pins. Leave these pins floating.
5.4.13 Clock interface
Table 14.ꢁClock interface
Pin Name
Supply
No Pad Power Reset
HW
State
PD
PD Prog Internal PU/
PD
PU
PD
State
State
XTAL_IN
AVDD18
--
--
--
--
--
--
--
--
Crystal / Crystal Oscillator / System Clock Input
Accepts 26 MHz reference clock signal. See Section 9.10 "Clock specifications".
XTAL_OUT
Crystal / Crystal Oscillator Output
Connect this pin to ground when an external oscillator is used.
SLP_CLK_IN VIO tristate input input
Sleep Clock Input (optional)
Used for Wi-Fi and Bluetooth low-power modes.
• An external sleep clock is recommended for minimal current consumption.
AVDD18
--
--
--
--
--
--
--
--
tristate
no
nominal PU
yes
yes
• If no sleep clock input is provided, an internal sleep clock (derived from reference clock) will be used. This will cause
an approximate ~50 uA current increase on the 3.3V rail, since the reference clock cannot be shut down during device
sleep. If SLP_CLK_IN is not connected, the internal circuit will detect no signal, and firmware will initialize the sleep clock
based on the reference clock.
• To reduce further leakage, do not ground the SLP_CLK_IN pin / keep it floating (DNC) for cases where a sleep clock
derived from the reference clock will be used.
XOSC_EN
VIO
--
--
--
--
--
--
--
--
XOSC_EN/CLK_REQ (output)
NOTE: Muxed with GPIO[0].
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
24 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
5.4.14 Power-down pin
Table 15.ꢁPower-down pin
Pin Name
Supply
No Pad
Power
State
Reset
State
HW
State
PD State
PD Prog
Internal PU/
PD
PU
PD
PDn
AVDD18
--
--
--
--
--
--
--
--
Full Power-Down (input) (active low)
0 = full power-down mode
1 = normal mode
• PDn can accept an input of 1.8V to 4.5V
• PDn may be driven by the host
• PDn must be high for normal operation
No internal pull-up on this pin.
5.4.15 JTAG interface
Table 16.ꢁJTAG interface pins (MFP)
NOTE: Pins may be Multi-Functional Pins (MFP). See pin descriptions for functional modes.
Pin Name
JTAG_TDO
JTAG_TDI
JTAG_TMS
JTAG_TCK
Type
Supply
VIO
Description
O
I
JTAG test data output signal. GPIO[3] input/output
JTAG test data input signal. GPIO[2] input/output
VIO
I
VIO
JTAG test mode select input signal. GPIO[15] input/output
JTAG test clock input signal. GPIO[14] input/output
I
VIO
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
25 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
5.5 Configuration pins
Table 17 shows the pins used as configuration inputs to set the parameters following
a reset. The definition of these pins changes immediately after reset to their usual
function. To set a configuration bit to 0, attach a 100 kΩ resistor from the pin to ground.
No external circuitry is required to set a configuration bit to 1.
Table 17.ꢁConfiguration pins
Configuration Bits
CON[1]
Pin Name
Configuration Function
RF_CNTL2_N
RF_CNTL0_N
Firmware Boot Options
No hardware impact. Software reads and boots
accordingly. See Table 18
CON[0]
Note: Boot code needs to use this host boot strap
status to decide the correct boot sequence.
Table 18.ꢁFirmware boot options
Strap value
Wi-Fi
Bluetooth/
Bluetooth LE
Firmware
download
Firmware
download mode
Number of SDIO
functions
00
01
10
11
--
--
--
--
--
--
--
--
--
--
SDIO
SDIO
UART
SDIO
SDIO + UART
SDIO + SDIO
Parallel/Serial
Parallel/Serial
1 (Wi-Fi)
2 (Wi-Fi,
Bluetooth)
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
26 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
6 Power information
The table in Section 5.4.12 "Power supply and ground pins " shows the required voltage
levels for each rail and PDn input signal.
6.1 Leakage optimization
For applications not using Wi-Fi and Bluetooth, the device can be put into a low-leakage
mode of operation. Methods include:
• Using the power-down (PDn) pin
The power-down state provides the lowest leakage mode of operation. Assert PDn low
to enter power-down. If the firmware is not downloaded, the device must be kept in
power-down mode to reduce leakage.
• All rails powered off
Alternatively, all power rails can be powered off. In this case, the state of PDn pin is
irrelevant.
6.2 Power-up
The 88W8977 VCORE is supplied through either an external PMIC or the internal LDO.
In both cases, the PDn pin of the 88W8977 is tied to 1.8V.
The power configurations include:
• Section 6.2.1 "Configuration—PMIC supplies VCORE"
• Section 6.2.2 "Configuration—Internal LDO supplies VCORE"
In either configuration, the ramp-up is controlled by the Host using the PMIC_EN pin.
• PMIC_EN represents the input enable pin (EN) of the power regulator.
• PMIC_EN ramps up from Host 3.3V
• PMIC_EN ramps up from Host GPIO pin
Section 6.2.3 "Power-up sequence" shows the power-up sequence for both
configurations.
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
27 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
6.2.1 Configuration—PMIC supplies VCORE
• PMIC suppplies VCORE
• PMIC_EN ramps up from the host 3.3V or the host GPIO pin
• AVDD18 supplies PDn (follow AVDD18; PDn is connected to 1.8V supply)
• PMIC supplies the external VPA and AVDD18 power supply pins
• The host (1.8V/3.3V) supplies the external VIO/VIO_REF power supply pins
PMIC
88W8977
2.2V
1.8V
VPA
VIN
AVDD18/PDn
VCORE
Host
1.05V
3.3V/
Power-down from Host
GPIO
EN (PMIC_EN)
1.8V/3.3V (from GPIOs)
DVSC[1:0]
1.8V/3.3V
VIO/VIO_RF
Figure 7.ꢁConfiguration—VCORE from PMIC[1]
[1] A minimum time of 100 ms is required after PMIC_EN is deasserted (=0) and before it is asserted (=1).
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
28 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
6.2.2 Configuration—Internal LDO supplies VCORE
• LDO_VOUT supplies VCORE
• PMIC_EN ramps up from Host 3.3V or Host GPIO pin
• AVDD18 supplies PDn (follow AVDD18; PDn connected to 1.8V supply)
• PMIC supplies the external VPA and AVDD18/LDO_VIN power supply pins
• The host (1.8V/3.3V) supplies the external VIO/VIO_REF power supply pins
88W8977
PMIC
2.2V
1.8V
VPA
VIN
AVDD18/PDn/LDO_VIN
Host
LDO_VOUT
VCORE
3.3V/
Power-Down from Host
GPIO
EN (PMIC_EN)
1.05V
1.8V/3.3V (from GPIOs)
DVSC[1:0]
1.8V/3.3V
VIO/VIO_RF
Figure 8.ꢁConfiguration—VCORE from Internal LDO[1]
[1] A minimum time of 100 ms is required after PMIC_EN is deasserted (=0) and before it is asserted (=1).
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
29 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
6.2.3 Power-up sequence
• VPA must be good (90%) before AVDD18 starts ramping up.
• AVDD18 must be good (90%) before VCORE starts ramping up.
Figure 9 shows the power-up sequence.
VIN/VIO
EN
(PMIC_EN)
Power_good (90%)
2.2V
VPA
AVDD18
PDn
Power_good (90%)
1.8V
1.8V
1.1V
VCORE
Internal POR
XTAL_IN
Strap/
Internal
Boot ROM execution starts and firmware
download begins
RESETn
Figure 9.ꢁPower-up sequence
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
30 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
6.3 Power-down
6.3.1 Recommended power-down sequence
In the recommended power-down sequence, VPA ramps down before AVDD18 in order
for the RF PA to turn the logic off (depends on the control logic generated from AVDD18).
Also, when the PMIC VBAT is removed, the PMIC cannot guarantee a ramp-down
requirement.
Figure 10 shows the recommended (but not required) power-down sequence.
VPA (2.2V)
AVDD18 (1.8V)
VCORE (1.1V)
Figure 10.ꢁRecommended power-down sequence
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
31 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
6.3.2 Power-down using PMIC_EN host pin
The maximum ramp-down time for VCORE from PMIC_EN assertion is 10 ms. PMIC_EN
must be asserted a minimum of 100 ms to guarantee that VCORE and AVDD18 are
discharged to less than 0.2V for the POR to generate properly after PMIC_EN is
deasserted.
Figure 11 shows the sequence.
min 100 ms
EN
(PMIC_EN)
VPA (2.2V)
AVDD18 (1.8V)/
PDn
VCORE (1.1V)
Internal POR
max 10 ms
Figure 11.ꢁPower-down using PMIC_EN host pin - PMIC and 88W8977 both in power-down mode
6.4 Deep sleep
When a programmable power regulator is used to supply VCORE, 88W8977 may use
the power management interface to reduce VCORE to approximately 0.8V to reduce the
power consumption in deep sleep mode.
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
32 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
7 Absolute maximum ratings
Note: The absolute maximum ratings table defines the limitations for electrical and
thermal stresses. These limits prevent permanent damage to the device. Exposure to
conditions at or beyond these ratings is not guaranteed and can damage the device.
Table 19.ꢁAbsolute Maximum Ratings
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCORE
Power supply voltage
with respect to VSS
--
--
1.05
1.21
V
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
1.8
2.5
3.3
1.8
3.3
1.8
3.3
1.8
2.2
3.0
4.0
2.2
4.0
2.2
4.0
1.98
V
V
V
V
V
V
V
V
Power supply voltage
with respect to VSS
VIO
VIO_SD
Power supply voltage
with respect to VSS
Power supply voltage
with respect to VSS
VIO_RF
AVDD18
Power supply voltage
with respect to VSS
VPA
Power supply voltage
with respect to VSS
--
--
--
--
2.2
1.8
2.3
2.0
V
V
LDO_VIN Power supply voltage
with respect to VSS
TSTORAGE Storage temperature
--
-55
-1
--
--
--
+125
+1
°C
kV
V
VESD
Electrocstatic discharge voltage
human body model (HBM)[1]
charged device model (CDM)[2]
-500
+500
[1] According to JESD22-A114F
[2] According to JESD22-C101E
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
33 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
8 Recommended operating conditions
Note: Operation beyond the recommended operating conditions is neither
recommended nor guaranteed.
Table 20.ꢁRecommended Operating Conditions
Symbol
Parameter
Condition
Min
1.00
1.62
2.25
2.97
1.62
2.97
1.62
2.97
1.71
2.09
1.71
-30
Typ
1.05
1.8
2.5
3.3
1.8
3.3
1.8
3.3
1.8
2.2
1.8
--
Max
1.15
1.98
2.75
3.47
1.98
3.47
1.98
3.47
1.89
2.26
1.89
85
Unit
V
VCORE
1.05V core power supply
--
--
V
VIO
1.8V/2.5V/3.3V digital I/O power supply
--
V
--
V
--
V
VIO_SD
VIO_RF
1.8V/3.3V digital I/O SDIO power supply
1.8V/3.3V I/O power supply
--
V
--
V
--
V
AVDD18
VPA
1.8V analog power supply
2.2V analog power supply
--
V
--
V
LDO_VIN LDO input voltage supply
--
V
Extended
Industrial
--
°C
°C
°C
TA
TJ
Ambient operating temperature
Maximum junction temperature
-40
--
85
--
--
125
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
34 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
9 Electrical specifications
9.1 GPIO/LED interface specifications
The GPIO pins are powered by the VIO voltage supply.
9.1.1 VIO DC characteristics
9.1.1.1 1.8V operation
Table 21.ꢁDC electricals—1.8V operation (VIO)
Symbol
VIH
Parameter
Condition
Min
0.7*VIO
-0.4
Typ
--
Max
VIO+0.4
0.3*VIO
--
Unit
V
Input high voltage
Input low voltage
Input hysteresis
Output high voltage
Output low voltage
--
--
--
--
--
VIL
--
V
VHYS
VOH
100
--
mV
V
VIO-0.4
--
--
--
VOL
--
0.4
V
9.1.1.2 2.5V operation
Table 22.ꢁDC electricals—2.5V operation (VIO)
Symbol
VIH
Parameter
Condition
Min
0.7*VIO
-0.4
Typ
--
Max
VIO+0.4
0.3*VIO
--
Unit
V
Input high voltage
Input low voltage
Input hysteresis
Output high voltage
Output low voltage
--
--
--
--
--
VIL
--
V
VHYS
VOH
100
--
mV
V
VIO-0.4
--
--
--
VOL
--
0.4
V
9.1.1.3 3.3V operation
Table 23.ꢁDC electricals—3.3V operation (VIO)
Symbol
VIH
Parameter
Condition
Min
0.7*VIO
-0.4
Typ
--
Max
VIO+0.4
0.3*VIO
--
Unit
V
Input high voltage
Input low voltage
Input hysteresis
Output high voltage
Output low voltage
--
--
--
--
--
VIL
--
V
VHYS
VOH
100
--
mV
V
VIO-0.4
--
--
--
VOL
--
0.4
V
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
35 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
9.1.2 LED mode
Table 24.ꢁLED mode data
Over the full range of values specified in the Recommended Operating Conditions unless otherwise specified.
Symbol
Parameter
Condition
Typ
Unit
IOH
Switching current high
Tristate on pad
Tristate when driving high
mA
(requires pull-up on board)
IOL
Switching current low
at 0.4V
10
mA
Vcc
250
250
Buffer
10 pF
Figure 12.ꢁSlew rate measurement diagram
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
36 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
9.2 RF front-end control interface specifications
The RF front-end control pins are supplied by VIO_RF.
9.2.1 VIO_RF DC characteristics
9.2.1.1 1.8V operation
Table 25.ꢁDC electricals—1.8V operation (VIO_RF)
Symbol
VIH
Parameter
Condition
Min
0.7*VIO_RF
-0.4
Typ
--
Max
Unit
V
Input high voltage
Input low voltage
Input hysteresis
Output high voltage
Output low voltage
--
--
--
--
--
VIO_RF+0.4
VIL
--
0.3*VIO_RF
V
VHYS
VOH
100
--
--
--
mV
V
VIO_RF-0.4
--
--
VOL
--
0.4
V
9.2.1.2 3.3V operation
Table 26.ꢁDC electricals—3.3V operation (VIO_RF)
Symbol
VIH
Parameter
Condition
Min
0.7*VIO_RF
-0.4
Typ
--
Max
Unit
V
Input high voltage
Input low voltage
Input hysteresis
Output high voltage
Output low voltage
--
--
--
--
--
VIO_RF+0.4
VIL
--
0.3*VIO_RF
V
VHYS
VOH
100
--
--
--
mV
V
VIO_RF-0.4
--
--
VOL
--
0.4
V
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
37 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
9.3 Wi-Fi radio specifications
9.3.1 Wi-Fi radio performance measurement
The Wi-Fi transmit/receive performance is measured either at the antenna port or at the
chip output port.
88W8977
Wi-Fi 5G Tx/Rx
Filter
Filter
Diplexer
Wi-Fi 2.4G Tx/Rx
Antenna
port
Chip port
Figure 13.ꢁRF performance measurement points
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
38 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
9.3.2 2.4 GHz Wi-Fi receiver performance
Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and at the
chip port.
Table 27.ꢁ2.4 GHz Wi-Fi receiver performance
Parameter
Conditions
Min
2400
--
Typ
--
Max
2500
--
Unit
MHz
dBm
RF frequency range
2.4 GHz—IEEE 802.11n/g/b
Receiver input IP3
Receiver input IP3 when LNA in high
gain mode (24 dB) at chip input
-20
at RF high gain (in-band)
1 Mbit/s
2 Mbit/s
5.5 Mbit/s
11 Mbit/s
6 Mbit/s
9 Mbit/s
12 Mbit/s
18 Mbit/s
24 Mbit/s
36 Mbit/s
48 Mbit/s
54 Mbit/s
MCS0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-100
-96
-95
-91
-92
-92
-91
-89
-86
-83
-79
-77
-92
-90
-88
-85
-82
-77
-76
-74
-89
-88
-85
-83
-79
-75
-73
-72
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
Receiver sensitivity 802.11b
Receiver sensitivity 802.11g
Receiver sensitivity 802.11n, HT20
(with BCC)
MCS1
MCS2
MCS3
MCS4
MCS5
MCS6
MCS7
Receiver sensitivity 802.11n, HT40
(with BCC)
MCS0
MCS1
MCS2
MCS3
MCS4
MCS5
MCS6
MCS7
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
39 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Table 27.ꢁ2.4 GHz Wi-Fi receiver performance...continued
Parameter
Conditions
802.11b
Min
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Typ
-1
Max
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Unit
dBm
dBm
dBm
dB
Receiver maximum input level 802.11
802.11g
-1
MCS0-7
-1
Receiver adjacent channel interference 1 Mbit/s
rejection (ACI) 802.11b
38
39
43
47
33
33
32
30
29
27
22
19
33
32
30
27
24
19
18
17
2 Mbit/s
dB
5.5 Mbit/s
11 Mbit/s
dB
dB
Receiver adjacent channel interference 6 Mbit/s
rejection (ACI) 802.11g
dB
9 Mbit/s
dB
12 Mbit/s
dB
18 Mbit/s
dB
24 Mbit/s
dB
36 Mbit/s
dB
48 Mbit/s
54 Mbit/s
dB
dB
Receiver adjacent channel interference MCS0
rejection (ACI) 802.11n, HT20
dB
MCS1
dB
MCS2
MCS3
MCS4
MCS5
MCS6
MCS7
dB
dB
dB
dB
dB
dB
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
40 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
9.3.3 5 GHz Wi-Fi receiver performance
Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, averaged
over one channel per sub-band, averaged over the antenna path, and at the chip port.
Table 28.ꢁ5 GHz Wi-Fi receiver performance
Parameter
Conditions
Min
4900
--
Typ
--
Max
5925
--
Unit
MHz
dBm
RF frequency range
5 GHz—IEEE 802.11n/a
Receiver input IP3
at RF high gain (in-band)[1]
Receiver Input IP3 when LNA in
high gain mode (24 dB) at chip input
-20
Receiver sensitivity 802.11a
6 Mbit/s
9 Mbit/s
12 Mbit/s
18 Mbit/s
24 Mbit/s
36 Mbit/s
48 Mbit/s
54 Mbit/s
MCS0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-92
-92
-91
-89
-86
-83
-79
-77
-92
-90
-88
-85
-82
-77
-76
-74
-89
-87
-86
-83
-79
-75
-73
-72
-3
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dB
Receiver sensitivity 802.11n HT20
(with BCC)
MCS1
MCS2
MCS3
MCS4
MCS5
MCS6
MCS7
Receiver sensitivity 802.11n HT40
(with BCC)
MCS0
MCS1
MCS2
MCS3
MCS4
MCS5
MCS6
MCS7
Receiver maximum input level 802.11
802.11a
MCS0-7
-3
Receiver adjacent channel interference 6 Mbit/s
rejection (ACI) 802.11a
30
9 Mbit/s
29
dB
12 Mbit/s
18 Mbit/s
29
dB
26
dB
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
41 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Table 28.ꢁ5 GHz Wi-Fi receiver performance...continued
Parameter Conditions
Min
--
Typ
26
19
16
13
30
28
26
24
18
14
13
9
Max
--
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Receiver adjacent channel interference 24 Mbit/s
rejection (ACI) 802.11a
36 Mbit/s
--
--
(continued)
48 Mbit/s
54 Mbit/s
--
--
--
--
Receiver adjacent channel interference MCS0
--
--
rejection (ACI) 802.11n HT20
MCS1
--
--
MCS2
MCS3
MCS4
MCS5
MCS6
MCS7
--
--
--
--
--
--
--
--
--
--
--
--
[1] Excludes an external LNA nominal gain of 16 dB. Gain can be extended if external LNA is not used.
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
42 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
9.3.4 2.4 GHz Wi-Fi transmitter performance
Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and at the
chip port.
Table 29.ꢁ2.4 GHz Wi-Fi transmitter performance
Parameter
Conditions
Min
2400
--
Typ
--
Max
2500
--
Unit
MHz
dBm
dB
RF frequency range
2.4 GHz—IEEE 802.11n/g/b
Saturation power at chip output port
Carrier suppression at chip output port
I/Q suppression at chip output port
Transmit output saturation
Transmit carrier suppression (CW)
27
--
-36
-45
--
Transmit I/Q suppression with IQ
calibration
--
--
dBc
Transmit power (EVM and mask
compliant) 20 MHz per chain
802.11b
--
--
--
--
--
--
20
20
20
20
19
18
--
--
--
--
--
--
dBm
dBm
dBm
dBm
dBm
dBm
OFDM BPSK
OFDM QPSK
OFDM 16-QAM
OFDM 64-QAM (MCS7)
OFDM 64-QAM (MCS7)
Transmit power (EVM and mask
compliant) 40 MHz per chain
Transmit output power level control
range
--
--
--
20[1]
--
dB
Transmit output power control step
Transmit Carrier suppression
--
--
1[2]
37
--
--
dB
dB
802.11b, 11 Mbit/s at 19 dBm,
bandwidth = 20 MHz
[1] 0-20 dB
[2] Hardware capability = 0.5 dB, software capability = 1 dB
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
43 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
9.3.5 5 GHz Wi-Fi transmitter performance
Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and at the
chip port.
Table 30.ꢁ5 GHz Wi-Fi transmitter performance
Parameter
Conditions
Min
4900
--
Typ
--
Max
5925
--
Unit
MHz
dBm
dB
RF frequency range
5 GHz—IEEE 802.11n/a
Saturation power at chip output
Carrier suppression at chip output
I/Q suppression at chip output
Transmit output saturation
Transmit carrier suppression (CW)
27
--
-36
-45
--
Transmit I/Q suppression with IQ
calibration
--
--
dBc
Transmit power (EVM and mask
compliant) 20 MHz per chain
OFDM BPSK
--
--
--
--
--
19
19
19
18
17
--
--
--
--
--
dBm
dBm
dBm
dBm
dBm
OFDM QPSK
OFDM 16-QAM
OFDM 64-QAM (MCS7)
OFDM 64-QAM (MCS7)
Transmit power (EVM and mask
compliant) 40 MHz per chain
Transmit output power level control
range
--
--
20[1]
--
dB
Transmit output power control step
Transmit carrier suppression
--
--
--
1[2]
46
--
--
dB
802.11n MCS7 HT40, at 15 dBm
dBc
[1] 0-20 dBm
[2] Hardware capability = 0.5 dB, software capability = 1 dB
9.3.6 Local oscillator
Table 31.ꢁLocal oscillator
Parameter
Condition
Min
Typ
Max
Unit
Measured at 2.438 GHz at 100 kHz
offset
--
-103
--
dBc/Hz
Phase noise
Measured at 5.501 GHz at 100 kHz
offset
--
--
-100
0.35
--
--
dBc/Hz
Reference clock frequency = 26 MHz
(2.4 GHz)
degrees
Integrated RMS phase noise at RF
output (from 10 kHz–10 MHz)
Reference clock frequency = 26 MHz
(5 GHz)
--
0.65
--
--
--
degrees
kHz
Frequency resolution
--
0.02
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
44 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
9.4 Bluetooth radio specifications
The Bluetooth radio interface pin is powered by AVDD18 voltage supply.
9.4.1 Bluetooth/Bluetooth LE receiver performance
Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and at
chip port.
Table 32.ꢁBluetooth/Bluetooth LE receiver performance
Parameter
Conditions
Min
2.4
--
Typ
--
Max
2.5
--
Unit
GHz
MHz
dBm
dB
RF frequency range
IF frequency
--
--
--
1.5
-19
10
Input IP3 (at maximum gain of 72 dB)
--
--
GFSK
--
--
C/I (Co-channel)
C/I (1 MHz)
--
--
--
--
--
--
-4
--
--
--
--
--
--
dB
dB
dB
dB
dB
dB
C/I (2 MHz)
-45
-49
-21
-32
10
C/I (3 MHz)
C/I (Image)
C/I (Image ±1 MHz)
Pi/4-DQPSK
C/I (Co-channel)
C/I (1 MHz)
--
--
--
--
--
--
-9
--
--
--
--
--
--
dB
dB
dB
dB
dB
dB
C/I (2 MHz)
-47
-51
-19
-35
16
In-band blocking
C/I (3 MHz)
C/I (Image)
C/I (Image ±1 MHz)
8-DPSK
C/I (Co-channel)
C/I (1 MHz)
--
--
--
--
--
--
--
--
--
--
-6
-42
--
--
--
--
--
--
--
--
--
0
dB
dB
C/I (2 MHz)
C/I (3 MHz)
-48
dB
C/I (Image)
-12
dB
C/I (Image ±1 MHz)
30–2000 MHz
2–2.399 GHz
2.484–3 GHz
3–12.75 GHz
Resolution = 1 dB
-33
dB
-12.5
-12.4
-18
dBm
dBm
dBm
dBm
dBm
Out-of-band blocking
RSSI Range
-2.6
-90
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
45 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Table 32.ꢁBluetooth/Bluetooth LE receiver performance...continued
Parameter
Conditions
DH5
Min
--
Typ
-96
-96
-89
-99
Max
--
Unit
dBm
dBm
dBm
dBm
Sensitivity
2DH5
--
--
(RCV/CA/01/C, RCV/CA/02/C, and
RCV/CA/07/C)
3DH5
--
--
Sensitivity (RCV-LE/CA/02/C)
LE 1 Mbit/s
--
--
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
46 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
9.4.2 Bluetooth/Bluetooth LE transmitter performance
Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and
across frequency.
Table 33.ꢁBluetooth/Bluetooth LE transmitter performance
Parameter
Conditions
Min
2.4
--
Typ
--
Max
2.5
--
Unit
GHz
dBm
dBm
dB
RF frequency range
--
Class 1 without external PA—BDR
+13
+10
30
0.5
--
Output power @pin
Class 1 without external PA—EDR
--
--
Class 1 without external PA
--
--
--
Gain range
Gain resolution
--
--
dB
±500 kHz
--
-20
-20
-40
-26
-20
-40
-41.25
-41.25
-25
dBc
dBm
dBm
dBc
dBm
dBm
Spurious emission (BDR) (in-band)
Spurious emission (EDR) (in-band)
±2 MHz
--
-33
-45
--
±3 MHz
--
±1 MHz
--
±1.5 MHz
±2.5 MHz
30–88 MHz
88–960 MHz
--
--
--
--
--
-65
-65
-35
--
0.96–20 GHz
--
All frequencies in this range
Spurious emission (out-of-band)
dBm
< -41.25 dBm, except at 2x Bluetooth
channel frequency.
Measured at pin without external filter.
Restricted—2.38–2.39 GHz
Restricted—2.4835–2.6 GHz
GSM850 (869–894 MHz)
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-55
-50
-41.25
-41.25
-140
-140
-135
-135
-140
-130
-140
13
--
--
--
--
--
--
--
--
--
--
--
--
GSM900 (925–960 MHz)
GSM DCS (1805–1880 MHz)
GSM PCS (1930–1990 MHz)
GPS (1575.42 ±1.023 MHz)
WCDMA Band I (2110–2170 MHz)
WCDMA Band V (869–894 MHz)
Out-of-band/
dBm/Hz
Cellular band noise
Transmit output power (TRM/CA/01/C) DH5
dBm
dB
Power control (TRM/CA/03/C)
--
4
Frequency range (TRM/CA/04/C)
Freq Low
Freq High
DH5
2400.9
2481.1
955
MHz
MHz
MHz
-20 dB bandwidth (TRM/CA/05/C)
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
47 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Table 33.ꢁBluetooth/Bluetooth LE transmitter performance...continued
Parameter
Conditions
Min
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Typ
165
100
0.9
145
2
Max
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Unit
kHz
%
Modulation characteristics
(TRM/CA/07/C)
Delta F1 avg
Delta F2 max Threshold
Delta F2/Delta F1
Delta F2 avg
--
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
dB
ICFT (TRM/CA/08/C)
DH1
Carrier frequency drift (TRM/CA/09/C)
Max Drift - DH1
Drift Rate - DH1
Max Drift - DH3
Drift Rate - DH3
Max Drift - DH5
Drift Rate - DH5
2DH5 (DPSK/GFSK)
3DH5 (DPSK/GFSK)
2DH5 Peak DEVM
2DH5 RMS DEVM
3DH5 Peak DEVM
3DH5 RMS DEVM
2DH5
-3.5
1
-4.5
1.5
-5
1.5
-0.1
-0.1
13
EDR relative power (TRM/CA/10/C)
dB
EDR carrier frequency stability and
modulation accuracy (TRM/CA/11/C)
%
5
%
15
%
6
%
Diff. phase encoding (TRM/CA/12/C)
100
100
5
%
3DH5
%
Bluetooth LE output power
(TRM/-LE/CA/01/C)
Bluetooth LE 1 Mbit/s
dBm
Bluetooth LE modulation characteristics Delta F1 avg - Bluetooth LE 1 Mbit/s
--
--
244
0.9
--
--
kHz
kHz
(TRM-LE/CA/05/C)
Delta F2/Delta F1
Bluetooth LE 1 Mbit/s
Delta F2 avg - Bluetooth LE 1 Mbit/s
--
--
--
--
222
1.5
1
--
--
--
--
kHz
kHz
kHz
kHz
Bluetooth LE carrier frequency drift
(TRM-LE/CA/06/C)
Max Drift - Bluetooth LE 1 Mbit/s
Drift Rate - Bluetooth LE 1 Mbit/s
Bluetooth LE 1 Mbit/s
Frequency accuracy
-3.5
(TRM-LE/CA/BV-06-C)
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
48 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
9.5 Current consumption
Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, across
frequency, and at chip output port for transmit data is collected from SDIO-SDIO host
interface configuration.
Table 34.ꢁCurrent consumption
Mode
Conditions
2.2V
0
1.8V
0.002
0.01
0.01
0.01
1.1V
0.001
0.291
0.195
0.153
Unit
mA
mA
mA
mA
Power down
Wi-Fi and Bluetooth in deep sleep mode
Bluetooth only in deep sleep mode
Bluetooth LE only in deep sleep mode
0.001
0.001
0.001
Sleep mode
Bluetooth LE link
0.001
0.001
0.064
16
0.232
30
mA
mA
(master mode, interval=1.28s)
Bluetooth LE peak tranmsit (at 0 dBm),
1 Mbit/s
Bluetooth LE
Bluetooth LE peak receive, 1 Mbit/s
Bluetooth LE advertise(interval=1.28s)
0.001
0.001
18
15
mA
mA
(Wi-Fi in deep sleep mode)
0.047
0.197
Bluetooth LE scan
0.001
0.154
0.28
mA
(interval = 1.28s, window = 11.25 ms)
Bluetooth page scan
0.001
0.001
0.203
0.353
0.495
0.622
mA
mA
Bluetooth page and inquiry scan
Bluetooth ACL link, master sniff mode,
(interval = 1.28s)
0.001
0.001
0.078
0.193
0.427
0.604
mA
mA
Bluetooth ACL link, master sniff mode,
(interval=500ms)
Bluetooth
Bluetooth ACL (data pump) DH1
Bluetooth ACL (data pump) 3-DH5
0.001
0.001
10
23
17
14
mA
mA
(Wi-Fi in deep sleep mode)
Bluetooth SCO HV3 peak transmit
(at device maximum power)
0.001
0.001
0.001
88
18
17
14
15
37
mA
mA
mA
Bluetooth SCO HV3 peak Rx
Bluetooth SCO HV3 Peak transmit (at 4
dBm)
IEEE-PS_2GHz-Legacy (DTIM-1)
IEEE-PS_2GHz-Legacy (DTIM-3)
IEEE-PS_2GHz-Legacy (DTIM-5)
802.11b, 11 Mbit/s, 1x1
0.001
0.001
0.001
0.005
0.005
0.005
0.005
0.005
0.005
0.916
0.42
0.274
36
0.886
0.502
0.439
24
mA
mA
mA
mA
mA
mA
mA
mA
mA
IEEE power save
(Beacon interval: 100 msec)
2.4 GHz Wi-Fi receive
802.11g, 54 Mbit/s, 1x1
37
32
(Bluetooth in deep sleep mode)
802.11n, HT20 MCS7, 1x1
802.11a, 54 Mbit/s, 1x1
35
40
53
32
5 GHz Wi-Fi receive
802.11n, HT20 MCS7, 1x1
802.11n, HT40 MCS7, 1x1
52
40
(Bluetooth in deep sleep mode)
60
53
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
49 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Table 34.ꢁCurrent consumption...continued
Mode
Conditions
2.2V
225
185
164
186
185
168
1.8V
93
1.1V
83
Unit
mA
mA
mA
mA
mA
mA
802.11b, 11 Mbit/s at 16 dBm, 1x1
802.11g, 54 Mbit/s at 15 dBm, 1x1
802.11n, HT20 MCS7 at 14 dBm, 1x1
802.11a, 54 Mbit/s at 15 dBm, 1x1
802.11n, HT20 MCS7 at 15 dBm, 1x1
802.11n, HT40 MCS7 at 14 dBm, 1x1
2.4 GHz Wi-Fi transmit
91
95
90
97
147
148
148
98
5 GHz Wi-Fi transmit
105
114
Current consumption during
device initialization
Max current consumption during device
initialization
950
254
150
mA
9.6 Coexistence specifications
The 88W8977 MWS coexistence interface pins are powered by VIO voltage supply.
Refer to the MWS standard for additional interface specifications.
See Section 9.1.1 "VIO DC characteristics" for specifications.
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
50 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
9.7 SDIO host interface specifications
The SDIO host interface pins are powered by VIO_SD voltage supply.
The SDIO electrical specifications are identical for 4-bit SDIO and 1-bit SDIO transfer
modes.
9.7.1 VIO_SD DC characteristics
9.7.1.1 1.8V operation
Table 35.ꢁDC electricals—1.8V operation (VIO_SD)
Symbol
VIH
Parameter
Condition
Min
0.7*VIO_SD
-0.4
Typ
--
Max
Unit
V
Input high voltage
Input low voltage
Input hysteresis
Output high voltage
Output low voltage
--
--
--
--
--
VIO_SD+0.4
VIL
--
0.3*VIO_SD
V
VHYS
VOH
100
--
--
--
mV
V
VIO_SD-0.4
--
--
VOL
--
0.4
V
9.7.1.2 3.3V operation
Table 36.ꢁDC electricals—3.3V operation (VIO_SD)
Symbol
VIH
Parameter
Condition
Min
0.7*VIO_SD
-0.4
Typ
--
Max
Unit
V
Input high voltage
Input low voltage
Input hysteresis
Output high voltage
Output low voltage
--
--
--
--
--
VIO_SD+0.4
VIL
--
0.3*VIO_SD
V
VHYS
VOH
100
--
--
--
mV
V
VIO_SD-0.4
--
--
VOL
--
0.4
V
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
51 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
9.7.2 Default speed mode and high-speed mode
fPP
TWL
TWH
Clock
Input
TISU
TIH
TODLY
Output
Figure 14.ꢁSDIO protocol timing diagram—Default speed mode (3.3V)
fPP
TWL
TWH
Clock
Input
TISU
TIH
TODLY
TOH
Output
Figure 15.ꢁSDIO protocol timing diagram—High-speed mode (3.3V)
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
52 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Table 37.ꢁSDIO timing data—Default speed mode and high-speed modes (3.3V)[1], [2]
Over full range of values specified in the Recommended Operating Conditions unless otherwise specified.
Symbol
Parameter
Condition
Normal
Min
0
Typ
--
Max
25
50
--
Unit
MHz
MHz
ns
fPP
Clock frequency
High-speed
Normal
0
--
10
7
--
TWL
TWH
TISU
TIH
Clock low time
Clock high time
Input setup time
Input hold time
High-speed
Normal
--
--
ns
10
7
--
--
ns
High-speed
Normal
--
--
ns
5
--
--
ns
High-speed
Normal
6
--
--
ns
5
--
--
ns
High-speed
Normal
2
--
--
ns
Output delay time
CL ≤ 40 pF (1 card)
Output hold time
--
--
14
14
--
ns
TODLY
TOH
High-speed
High-speed
--
--
ns
2.5
--
ns
[1] For SDIO 2.0 running at 50 MHz clock frequency, only 1.8V is supported.
[2] For SDIO 2.0 running at 25 MHz clock frequency, 1.8V or 3.3V is supported.
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
53 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
9.7.3 SDR12, SDR25, SDR50 modes (up to 100 MHz) (1.8V)
TCLK
fPP
Clock
Input
TCR
TCF
TIS
TIH
TODLY
TOH
Output
Figure 16.ꢁSDIO protocol timing diagram—SDR12, SDR25, SDR50 modes (up to 100 MHz)
(1.8V)
Table 38.ꢁSDIO timing data——SDR12, SDR25, SDR50 modes (up to 100 MHz) (1.8V)
Over full range of values specified in the Recommended Operating Conditions unless otherwise specified.
Symbol
fPP
Parameter
Condition
Min
25
3
Typ
--
Max
Unit
MHz
ns
Clock frequency
Input setup time
Input hold time
Clock time
SDR12/25/50
SDR12/25/50
SDR12/25/50
SDR12/25/50
100
TIS
--
--
--
TIH
0.8
10
--
--
ns
TCLK
TCR, TCF
--
40
ns
Rise time, fall time
--
0.2*TCLK
ns
TCR, TCF < 2 ns (max) at 100 MHz SDR12/25/50
CCARD = 10 pF
TODLY
Output delay time
CL ≤ 30 pF
SDR12/25/50
--
--
--
7.5
--
ns
ns
TOH
Output hold time
CL = 15 pF
SDR12/25/50
1.5
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
54 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
9.7.4 DDR50 Mode (50 MHz) (1.8V)
TCLK
Clock
TCR
TCF
TIS
TIH
CMD input
TOHLD
TODLY
CMD output
Figure 17.ꢁSDIO CMD timing diagram—DDR50 Mode (50 MHz)
TCLK
Clock
TIS2x
TIS2x
TIH2x
TIH2x
DAT[3:0]
Input
TODLY2x (max)
TODLY2x (max)
DAT[3:0]
Output
TODLY2x (min)
TODLY2x (min)
Figure 18.ꢁSDIO DAT[3:0] timing diagram—DDR50 mode[1] (50 MHz)
[1] In DDR50 mode, DAT[3:0] lines are sampled on both edges of the clock (not applicable for CMD line).
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
55 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Table 39.ꢁSDIO timing data—DDR50 mode (50 MHz)
Over full range of values specified in the Recommended Operating Conditions unless otherwise specified.
Symbol
Clock
TCLK
Parameter
Condition
Min
Typ
Max
Unit
Clock time
DDR50
DDR50
20
--
--
--
--
ns
ns
50 MHz (max) between rising edges
TCR, TCF
Rise time, fall time
0.2*TCLK
TCR, TCF < 4.00 ns (max) at 50 MHz
CCARD = 10 pF
Clock Duty --
DDR50
45
--
55
%
CMD Input (referenced to clock rising edge)
TIS
Input setup time
DDR50
DDR50
6
--
--
--
--
ns
ns
CCARD ≤ 10 pF (1 card)
TIH
Input hold time
0.8
CCARD ≤ 10 pF (1 card)
CMD Output (referenced to clock rising edge)
TODLY Output delay time during data transfer mode DDR50
--
--
--
13.7
--
ns
ns
CL ≤ 30 pF (1 card)
TOHLD
Output hold time
DDR50
1.5
CL ≥ 15 pF (1 card)
DAT[3:0] Input (referenced to clock rising and falling edges)
TIS2x
Input setup time
DDR50
3
--
--
--
--
ns
ns
CCARD ≤ 10 pF (1 card)
TIH2x
Input hold time
DDR50
0.8
CCARD ≤ 10 pF (1 card)
DAT[3:0] Output (referenced to clock rising and falling edges)
TODLY2x
Output delay time during data transfer mode DDR50
CL ≤ 25 pF (1 card)
--
--
--
7.0
--
ns
ns
(max)
TODLY2x
Output hold time
DDR50
1.5
(min)
CL ≥ 15 pF (1 card)
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
56 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
9.8 UART interface specifications
The UART transmit and receive pins are powered by VIO voltage supply.
TBAUD
UART Tx
UART Rx
Figure 19.ꢁFigure Caption
Table 40.ꢁUART timing data[1]
Over full range of values specified in the Recommended Operating Conditions unless otherwise specified.
Symbol
Parameter
Condition
Min
Typ
Max
Unit
TBAUD
Baud rate
26 MHz input clock
250
--
--
ns
[1] The acceptable deviation from the UART Rx target baud rate is ±3%.
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
57 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
9.9 PCM interface specifications
The PCM pins are powered by VIO voltage supply.
See Section 9.1.1 "VIO DC characteristics" for specifications.
Table 41.ꢁPCM timing specification diagram for data signals—Master mode
TBCLK
PCM_CLK
TDO
PCM_DOUT
TDISU
TDIHO
PCM_DIN
Table 42.ꢁPCM timing specification diagram for sync signal—Master mode
TBCLK
PCM_CLK
TBF
TBF
PCM_SYNC
Table 43.ꢁPCM timing specification data—Master mode
Symbol
Parameter
Condition
Min
--
Typ
2/2.048
0.5
Max
Unit
MHz
--
FBCLK
Bit clock frequency
Bit clock duty cycle
PCM_CLK rise/fall time
--
--
--
--
--
0.6
--
Duty CycleBCLK
TBCLK rise/fall
TDO
0.4
--
3
ns
Delay from PCM_CLK rising edge to PCM_DOUT rising
edge
--
--
15
ns
TDISU
TDIHO
TBF
Setup time for PCM_DIN before PCM_CLK falling edge
Hold time for PCM_DIN after PCM_CLK falling edge
--
--
20
15
--
--
--
--
--
--
ns
ns
ns
Delay from PCM_CLK rising edge to PCM_SYNC rising edge --
15
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
58 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Table 44.ꢁPCM timing specification diagram for data signals—Slave mode
TBCLK
PCM_CLK
TDO
PCM_DOUT
TDISU
TDIHO
PCM_DIN
Table 45.ꢁPCM timing specification diagram for sync signal—Slave mode
TBCLK
PCM_CLK
TBFSU
TBFHO
TBF
PCM_SYNC
Table 46.ꢁPCM timing specification data—Slave mode
Symbol
Parameter
Condition
Min
--
Typ
2/2.048
0.5
Max
Unit
MHz
--
FBCLK
Bit clock frequency
Bit clock duty cycle
PCM_CLK rise/fall time
--
--
--
--
--
0.6
--
Duty CycleBCLK
TBCLK rise/fall
TDO
0.4
--
3
ns
Delay from PCM_CLK rising edge to PCM_DOUT rising
edge
--
--
30
ns
TDISU
TDIHO
TBFSU
TBFHO
Setup time for PCM_DIN before PCM_CLK falling edge
Hold time for PCM_DIN after PCM_CLK falling edge
Setup time for PCM_SYNC before PCM_CLK falling edge
Hold time for PCM_SYNC after PCM_CLK falling edge
--
--
--
--
15
10
15
10
--
--
--
--
--
--
--
--
ns
ns
ns
ns
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
59 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
9.10 Clock specifications
9.10.1 Single-ended clock input modes
9.10.1.1 2.4 GHz mode
Table 47.ꢁCMOS mode[1]
Symbol
VIH
Parameter
Condition
Min
Typ
Max
1.98
0.4
Unit
V
Input high voltage
Input low voltage
--
--
AVDD18 - 0.5 AVDD18
VIL
0
0
V
[1] Typical input capacitance is approximately 2 pF and input resistance is >20 kΩ.
Table 48.ꢁLow-Swing Mode[1]
Symbol
VLS_IH
VLS_IL
Parameter
Condition
Min
--
Typ
--
Max
1.8
--
Unit
V
Single-ended high-level voltage
Single-ended low-level voltage
--
--
0
--
V
VLS_Amp Low-swing clock amplitude (pk-pk) --
0.5
100
45
--
--
V
VLS_Slope Low-swing mid-point slope
Duty Duty cycle
--
--
--
--
MV/s
%
50
55
[1] AC-coupling capacitor is integrated into the SoC.
Table 49.ꢁPhase Noise—2.4 GHz operation
Parameter
Condition
Min
Typ
Max
Unit
Offset = 1 kHz
--
--
-126
dBc/
Hz
Offset = 10 kHz
Offset = 100 kHz
Offset > 1 MHz
--
--
--
--
--
--
-137
-145
-145
dBc/
Hz
Fref = 26 MHz
dBc/
Hz
dBc/
Hz
9.10.1.2 2.4 GHz and 5 GHz dual-band mode
Table 50.ꢁPhase noise—Dual-band operation
Parameter
Test Conditions
Offset = 1 kHz
Offset = 10 kHz
Offset = 100 kHz
Offset > 1 MHz
Min
--
Typ
Max
Unit
--
--
--
--
-130
-150
-156
-156
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
--
Fref = 26 MHz
--
--
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
60 / 81
NXP Semiconductors
9.10.2 Crystal
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Table 51.ꢁCrystal specifications
Parameter
Condition
Typical
26
Unit
MHz
ppm
ppm
mm
pF
Fundamental frequencies
Frequency tolerance
--
Over operating temperature
< ±10
< ±10
<1.2
5
Over process at 25ºC
SMD and AT cut height
Load Capacitance
--
--
--
--
Maximum series resistance
Resonance mode
45
Ω
A1,
--
Fundamental
9.10.3 Sleep clock
Table 52.ꢁExternal sleep clock timing
Limited to within 10°C variance.
Symbol
Parameter
Min
Typ
Max
Unit
CLK
Clock frequency range/accuracy
• CMOS input clock signal type
• ±250 ppm (initial, aging, temperature)
--
32.768
--
kHz
VIH
VIL
PN
Input levels, where VIO = 1.8, 2.5, 3.3V
0.7*VIO
-0.4
--
--
VIO+0.4
0.3*VIO
--
V
V
For VIH, VIL, see Section Section 9.1.1 "VIO DC characteristics".
Phase noise requirement (at 100 kHz)
Cycle jitter
--
-125
dBc/
Hz
Jc
--
1.5
--
ns
(RMS)
SR
DC
Slew rate limit (10-90%)
Duty cycle tolerance
--
--
--
100
80
ns
%
20
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
61 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
9.11 JTAG interface specifications
The JTAG interface pins are powered by VIO voltage supply.
See Section 9.1.1 "VIO DC characteristics" for specifications.
TP_TCK
TL_TCK
TH_TCK
JTAG_TCK
THD_TDI
TSU_TDI
JTAG_TDI
JTAG_TMS
TDLY_TDO
JTAG_TDO
Figure 20.ꢁJTAG timing diagram
Table 53.ꢁJTAG timing data[1]
Over full range of values specified in the Recommended Operating Conditions unless otherwise specified.
Symbol
TP_TCK
TH_TCK
TL_TCK
Parameter
Condition
Min
40
12
12
10
10
0
Typ
--
Max
--
Unit
ns
TCK period
--
--
--
--
--
--
TCK high
--
--
ns
TCK low
--
--
ns
TSU_TDI
THD_TDI
TDLY_TDO
TDI, TMS to TCK setup time
TDI, TMS to TCK hold time
TCK to TDO delay
--
--
ns
--
--
ns
--
15
ns
[1] Does not apply to JTAG enabled by the JTAG_TMS pin.
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
62 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
10 Package information
10.1 Package thermal conditions
10.1.1 QFN package thermal conditions
Table 54.ꢁThermal conditions of QFN package
Symbol
Parameter
Condition
Typ
Unit
θJA
Thermal resistance
JEDEC 3 in. x 4.5 in.
4-layer PCB
28.4
°C/W
Junction to ambient of package.
θJA = (TJ - TA)/ P
no air flow
P = total power dissipation
JEDEC 3 in. x 4.5 in.
4-layer PCB
27.6
26.1
25.3
0.44
°C/W
°C/W
°C/W
°C/W
1 meter/sec air flow
JEDEC 3 in. x 4.5 in.
4-layer PCB
2 meter/sec air flow
JEDEC 3 in. x 4.5 in.
4-layer PCB
3 meter/sec air flow
ψJT
ψJB
θJC
Thermal characteristic parameter
Junction to top-center of package.
ψJT = (TJ - TTOP)/P
JEDEC 3 in. x 4.5 in.
4-layer PCB
no air flow
TTOP = temperature on top-center of package
Thermal characteristic parameter
Junction to bottom surface, center of PCB.
ψJB = (TJ - TB)/P
JEDEC 3 in. x 4.5 in.
4-layer PCB
15.4
13.0
°C/W
°C/W
no air flow
TB = surface temperature of PCB
Thermal resistance
JEDEC 3 in. x 4.5 in.
4-layer PCB
Junction to case of the package.
θJC = (TJ - TC)/ PTOP
no air flow
TC = temperature on top-center of package
PTOP = power dissipation from top of package
θJB
Thermal resistance
JEDEC 3 in. x 4.5 in.
4-layer PCB
15.6
°C/W
Junction to board of package.
θJB = (TJ - TB)/ PBOTTOM
no air flow
PBOTTOM = power dissipation from bottom of package to PCB
surface
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
63 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
10.1.2 eWLP package thermal conditions
Table 55.ꢁThermal conditions of eWLP package
Symbol
Parameter
Condition
Typ
Unit
θJA
Thermal resistance
JEDEC 4 in. x 4.5 in.
4-layer PCB
44.22
°C/W
Junction to ambient of package.
θJA = (TJ - TA)/ P
no air flow
P = total power dissipation
ψJT
Thermal characteristic parameter
Junction to top-center of package.
ψJT = (TJ - TTOP)/P
JEDEC 4 in. x 4.5 in.
4-layer PCB
0.56
°C/W
°C/W
no air flow
TTOP = temperature on top-center of package
ψJB
Thermal characteristic parameter
Junction to bottom-center of PCB.
ψJB = (TJ - TBOTTOM)/P
JEDEC 4 in. x 4.5 in.
4-layer PCB
13.93
no air flow
TB = temperature on bottom-center of package
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
64 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
10.2 Package mechanical data
10.2.1 68-pin QFN package mechanical drawing
Figure 21.ꢁ68-pin QFN package mechanical drawing
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
65 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
10.2.2 74-bump eWLP package mechanical drawing
Figure 22.ꢁ74-bump package mechanical drawing
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
66 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
10.3 Package marking
10.3.1 68-pin QFN package marking
Part Number, Package Code,
Environmental Code
xxx = package code
88W8977-NMV2
Lot Number
YYWW xx#
Country of Origin
Date code, Die revision, Assembly Plant
YYWW = Date Code
(YY = Year, WW = Work Week)
xx = Revision number
Country of Origin
(Contained in the mold ID or
marked as the last line on the
package)
E005
# = Assembly Plant Code
Temperature/Band code
E005 = Extended temperature
I005 = Industrial temperature
Pin 1 Location
Note: The above drawing is not drawn to scale. The location of markings is approximate.
Figure 23.ꢁ68-pin QFN package marking and pin 1 location
10.3.2 74-bump eWLP package marking
Part Number, Package Code,
Environmental Code
xxx = package code
Date code, Die revision, Assembly Plant
YYWW = Date Code
W8977EAD
Lot Number
YYWW xx#
Country of Origin
(Contained in the mold ID or
marked as the last line on the
package)
Country of Origin E005
(YY = Year, WW = Work Week)
xx = Revision number
# = Assembly Plant Code
Pin 1 Location
Temperature/Band code
E005 = Extended temperature (2.4/5 GHz)
None = Extended temperature (2.4 GHz)
Note: The above drawing is not drawn to scale. The location of markings is approximate.
Figure 24.ꢁ74-bump eWLP package marking and pin 1 location
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
67 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
11 Acronyms and abbreviations
Table 56.ꢁAcronyms and abbreviations
Acronym
A2DP
ABR
ACK
ADAS
ADC
AES
AFC
AFH
AGC
AIFS
AoA
Definition
Advanced Audio Distribution Profiles
Automatic Baud Rate
Acknowledgment
Advanced Driver Assistance Systems
Analog-to-Digital Converter
Advanced Encryption Standard
Automatic Frequency Correction
Adaptive Frequency Hopping
Automatic Gain Control
Arbitration Interframe Space
Angle of Arrival
AoD
Angle of Departure
AP
Access Point
APB
API
Advanced Peripheral Bus
Application Program Interface
Advanced Quad Flat Non-leaded Package
Advanced RISC Machine
Announcement Traffic Indication Message
Base Address Mask Register
Base Address Register
Baseband Processor Unit
Benzocyclobutene (flip chip bump process)
Basic Data Rate
aQFN
ARM
ATIM
BAMR
BAR
BBU
BCB
BDR
BER
BOM
BR
Bit Error Rate
Bill of Materials
Baud Rate
BSS
BSSID
BTU
BRF
BWQ
CBC
CBP
CCA
Basic Service Set
Basic Service Set Identifier
Bluetooth Baseband Unit
Bluetooth RF Unit
Bandwidth Queue
Cipher Block Chaining
Contention-Based Period
Clear Channel Assessment
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
68 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Table 56.ꢁAcronyms and abbreviations...continued
Acronym
Definition
CCK
Complementary Code Keying
Counter Mode CBC-MAC Protocol
Close Descriptor Enable
CCMP
CDE
CFP
Contention-Free Period
CFQ
Contention-Free Queue
CID
Connection Identifier
CIS
Card Information Structure
CPU Interface Unit
CIU
CMD
CMQ
CRC
CS
Command
Control Management Queue
Cyclic Redundancy Check
Card Select
CSMA/CA
CSMA/CD
CSU
Carrier Sense Multiple Access / Collision Avoidance
Carrier Sense Multiple Access / Collision Detection
Clocked Serial Unit
CTS
Clear to Send
DAC
Digital-to-Analog Converter
Differential Binary Phase Shift Keying
Device Controller Driver
DBPSK
DCD
DCE
Data Communication Equipment
Distributed Coordination Function
Direct Current Level Adjustment
Digital Contactless Bridge
DMA Controller Unit
DCF
DCLA
DCLB
DCU
DFS
Dynamic Frequency Selection
Distributed Interframe Space
Direct Memory Access
DIFS
DMA
dQH
Device Queue Head
DQPSK
DSM
DSP
Differential Quadrature Phase Shift Keying
Distribution System Medium
Digital Signal Processor
DSRC
dTD
Dedicated Short Range Communications
Linked List Transfer Descriptors
Delivery Traffic Indication Message
Digital Voltage Scaling Control
Extensible Authentication Protocol
DTIM
DVSC
EAP
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
69 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Table 56.ꢁAcronyms and abbreviations...continued
Acronym
Definition
EBRAM
ED
Extended Block Random Access Memory
Energy Detect
EDCA
EEPROM
EIFS
EMC
ERP-OFDM
ETSI
eWLP
FAE
Enhanced Distributed Channel Access
Electrically Erasable Programmable Read Only Memory
Extended Interframe Space
Electromagnetic Compatibility
Extended Rate PHY-Orthogonal Frequency Division Multiplexing
European Telecommunications Standards Institute
Embedded Wafer Level Package
Field Application Engineer
Federal Communications Commission
First In First Out
FCC
FIFO
FIPS
FIQ
Federal Information Processing Standards
Fast Interrupt Request
FW
Firmware
GATT
GCMP
GI
Generic Attribute Profile
Galois/Counter Mode Protocol
Guard Interval
GPIO
GPL
GPU
HID
General Purpose Input/Output
General Public License
General Purpose Input/Output Unit
Human Interface Device
HIU
Host Interface Unit
HOGP
HSP
HT
HID Over GATT Profile
Hands-Free Profile
High Throughput
HW
Hardware
I/Q
Inphase/Quadrature
IB
InBand
IBSS
ICE
Independent Basic Service Set
In-Circuit Emulator (or Emulation)
Interrupt Cause Register
ICR
ICU
Interrupt Controller Unit
ICV
Integrity Check Value
IE
Information Element
IEEE
Institute of Electrical and Electronics Engineers
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
70 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Table 56.ꢁAcronyms and abbreviations...continued
Acronym
Definition
IEMR
I/F
Interrupt Event Mask Register
Interface
IFS
Interframe Space
IMR
IPG
Interrupt Mask Register
Inter-Packet Gap
IPsec
IR
Internet Protocol Security
Infrared
IRQ
Interrupt Request
ISA
Instruction Set Architecture
Integrated Services Digital Network
Industrial, Scientific, and Medical
Interrupt Status Mask Register
Interrupt Status Register
Joint Electronic Device Engineering Council
Joint Test Action Group
Low Density Parity Check
Low Energy
ISDN
ISM
ISMR
ISR
JEDEC
JTAG
LDPC
LE
LED
LME
LNA
LPM
LQFN
LSb
Light Emitting Diode
Layer Management Entity
Low Noise Amplifier
Low Power Management
Low Quad Flat Non-leaded
Least Significant bit
LSB
LSP
LTE
Least Significant Byte
Low-Speed Peripheral
Long Term Evolution
MAC
MC
Media/Medium Access Controller
Memory Controller
MCS
MCU
MDI
MIB
Modulation and Coding Scheme
MAC Control Unit
Modem Data Interface
Management Information Base
Message Integrity Code
Media Independent Interface
Multiple Input Multiple Output
Million Instructions Per Second
MIC
MII
MIMO
MIPS
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
71 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Table 56.ꢁAcronyms and abbreviations...continued
Acronym
Definition
MLME
MMI
MAC Sublayer Management Entity
Modem Management Interface
MAC Management Protocol Data Unit
Memory Management Unit
MAC Protocol Data Unit
Most Significant bit
MMPDU
MMU
MPDU
MSb
MSB
Most Significant Byte
MSDU
MU-MIMO
MU-PPDU
MWS
MAC Service Data Unit
Multi-User MIMO
Multi-User PPDU
Mobile Wireless System
Multimedia Wireless System
NAV
NDP
NL
Network Allocation Vector
Null Data Packet
No Load
NPTR
OCB
OFDM
OID
Next Descriptor Pointer
Outside the Context of a BSS
Orthogonal Frequency Division Multiplexing
Object Identifier
OOB
OTP
P2P
PA
Out of Band
One Time Programmable
Peer-to-Peer
Power Amplifier
PAD
PBU
PC
Packet Assembler/Disassembler
Peripheral Bus Unit
Point Coordinator
PCB
PCF
PCI
Printed Circuit Board
Point Coordination Function
Peripheral Component Interconnect
PCI Express
PCIe
PCM
PDn
PDU
PEAP
PHY
PIFS
Pulse Code Modulation
Power Down
Protocol Data Unit
Protected EAP
Physical Layer
Priority Interframe Space
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
72 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Table 56.ꢁAcronyms and abbreviations...continued
Acronym
Definition
PLL
Phase-Locked Loop
PLME
PMU
POST
PPDU
PPK
PPM
PSK
PTA
Physical Layer Management Entity
Power Management Unit
Power-On Self Test
PHY Protocol Data Unit
Per-Packet Key
Pulse Position Modulation
Pre-Shared Keys
Packet Traffic Arbitration
Pairwise Key
PWK
QAM
QFN
QoS
RA
Quadrature Amplitude Modulation
Quad Flat Non-leaded Package
Quality of Service
Receiver Address
RBDS
RDS
RF
Radio Broadcast Data System
Radio Data System
Radio Frequency
RFID
RIFS
RISC
ROM
RSSI
RTS
RTU
RU
Radio Frequency Identification
Reduced Interframe Space
Reduced Instruction Set Computer
Read Only Memory
Receiver Signal Strength Indication
Request to Send
General Purpose Timer Unit
Resource Unit
SA
Source Address
SAP
SCLK
SDA
SE
Service Access Point
Serial Interface Clock
Serial Interface Data
Secure Element
SFD
SIFS
SISO
SIU
Start of Frame Delimiter
Short Interframe Space
Single Input Single Output
Serial Interface Unit (UART)
System/Software JTAG Controller Unit
Switch Module
SJU
SM
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
73 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Table 56.ꢁAcronyms and abbreviations...continued
Acronym
Definition
SMI
Serial Management Interface
Signal-to-Noise Ratio
SNR
SO
Serial Out
SoC
System-on-Chip
SPDT
SPI
Single Pole Double Throw
Serial Peripheral Interface
Internal SRAM Unit
SQU
SRWB
SS
Serial Interface Read Write
Service Set
SSID
STA
Service Set Identifier
Station
STBC
SWD
SWP
TA
Space-Time Block Code
Serial Wire Debug
Single Wire Protocol
Transmitter Address
TBG
TBTT
TCM
TCP/IP
TCQ
TIM
Time Base Generator
Target Beacon Transmission Time
Tightly Coupled Memory
Transmission Control Protocol/Internet Protocol
Traffic Category Queue
Traffic Indication Map
TKIP
TPC
TQFP
TRPC
TSC
TSF
Temporal Key Integrity Protocol
Transmit Power Control
Thin Quad Flat Pack
Transmit Rate-based Power Control
TKIP Sequence Counter
Timing Synchronization Function
Target Wait Time
TWT
UART
UBM
UDP
UNII
VCO
VIF
Universal Asynchronous Receiver/Transmitter
Under Bump Metal
User Datagram Protocol
Unlicensed National Information Infrastructure
Voltage Controlled Oscillator
Voice Interface
VHT
WAP
Very High Throughput
Wireless Application Protocol
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
74 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Table 56.ꢁAcronyms and abbreviations...continued
Acronym
Definition
WAVE
WCI-2
WEP
Wireless Access in Vehicular Environments
Wireless Coexistence Interface 2
Wired Equivalent Privacy
WI
Wired Interface
Wi-Fi
Hardware implementation of IEEE 802.11 for wireless connectivity
Wireless Local Area Network
Wi-Fi Multimedia
WLAN
WMM
WPA
Wi-Fi Protected Access
WPA2
WPA2-PSK
WPA-PSK
XFQFN
XOSC
Wi-Fi Protected Access 2
Wi-Fi Protected Access 2-Pre-Shared Key
Wi-Fi Protect Access-Pre-Shared Key
Extra-Fine Quad Flat Non-leaded
Crystal Oscillator
12 Revision history
Table 57.ꢁRevision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
88W8977_SDS v3.0
20210513
Product short data
sheet
—
88W8977 v2.0
Modifications
• Updated Bluetooth 5 to Bluetooth 5.2
88W8977_SDS v2.0
20201214
Product short data
sheet
88W8977 v1.0
202007031F01
202007032F01
Modifications
• Replaced 88W8977 document ID with 88W8977_SDS.
• Section 10.3 "Package marking": updated.
• Section 2 "Ordering information": moved to the beginning of the document (no other
changes).
88W8977 v1.0
20200713
Product short data
sheet
-
-
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
75 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
13 Legal information
13.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Product [short] data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
13.2 Definitions
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
13.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
76 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Security — Customer understands that all NXP products may be subject
to unidentified or documented vulnerabilities. Customer is responsible
for the design and operation of its applications and products throughout
their lifecycles to reduce the effect of these vulnerabilities on customer’s
applications and products. Customer’s responsibility also extends to other
open and/or proprietary technologies supported by NXP products for use
in customer’s applications. NXP accepts no liability for any vulnerability.
Customer should regularly check security updates from NXP and follow up
appropriately. Customer shall select products with security features that best
meet rules, regulations, and standards of the intended application and make
the ultimate design decisions regarding its products and is solely responsible
for compliance with all legal, regulatory, and security related requirements
concerning its products, regardless of any information or support that may
be provided by NXP. NXP has a Product Security Incident Response Team
(PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation,
reporting, and solution release to security vulnerabilities of NXP products.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of non-
automotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
applications to automotive specifications and standards, customer (a) shall
use the product without NXP Semiconductors’ warranty of the product for
such automotive applications, use and specifications, and (b) whenever
customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use
of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
13.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
NXP — wordmark and logo are trademarks of NXP B.V.
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
77 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Part Order Codes ..............................................5
Pad locations—74-bump eWLP ...................... 13
Tab. 33. Bluetooth/Bluetooth LE transmitter
performance .................................................... 47
Tab. 34. Current consumption .......................................49
Tab. 35. DC electricals—1.8V operation (VIO_SD) .......51
Tab. 36. DC electricals—3.3V operation (VIO_SD) .......51
Tab. 37. SDIO timing data—Default speed mode
and high-speed modes (3.3V), ........................53
Pin types ......................................................... 17
General purpose I/O/LED interface .................18
RF front-end control interface ......................... 20
Wi-Fi/Bluetooth radio interface ........................20
Bluetooth external coexistence interface .........21
SDIO host interface .........................................22
UART host interface (MFP) .............................22
Tab. 38. SDIO timing data——SDR12, SDR25,
SDR50 modes (up to 100 MHz) (1.8V) ........... 54
Tab. 10. LTE interface ................................................... 23
Tab. 11. PCM interface pins (MFP) ...............................23
Tab. 12. Power management interface pins (MFP) ....... 23
Tab. 13. Power supply and ground pins ........................24
Tab. 14. Clock interface ................................................ 24
Tab. 15. Power-down pin .............................................. 25
Tab. 16. JTAG interface pins (MFP) ..............................25
Tab. 17. Configuration pins ........................................... 26
Tab. 18. Firmware boot options .....................................26
Tab. 19. Absolute Maximum Ratings .............................33
Tab. 20. Recommended Operating Conditions ............. 34
Tab. 21. DC electricals—1.8V operation (VIO) ..............35
Tab. 22. DC electricals—2.5V operation (VIO) ..............35
Tab. 23. DC electricals—3.3V operation (VIO) ..............35
Tab. 24. LED mode data ...............................................36
Tab. 25. DC electricals—1.8V operation (VIO_RF) ....... 37
Tab. 26. DC electricals—3.3V operation (VIO_RF) ....... 37
Tab. 27. 2.4 GHz Wi-Fi receiver performance ...............39
Tab. 28. 5 GHz Wi-Fi receiver performance ..................41
Tab. 29. 2.4 GHz Wi-Fi transmitter performance ...........43
Tab. 30. 5 GHz Wi-Fi transmitter performance ..............44
Tab. 31. Local oscillator ................................................ 44
Tab. 32. Bluetooth/Bluetooth LE receiver
Tab. 39. SDIO timing data—DDR50 mode (50 MHz) .... 56
Tab. 40. UART timing data ............................................57
Tab. 41. PCM timing specification diagram for data
signals—Master mode .....................................58
Tab. 42. PCM timing specification diagram for sync
signal—Master mode ...................................... 58
Tab. 43. PCM timing specification data—Master
mode ............................................................... 58
Tab. 44. PCM timing specification diagram for data
signals—Slave mode .......................................59
Tab. 45. PCM timing specification diagram for sync
signal—Slave mode ........................................ 59
Tab. 46. PCM timing specification data—Slave
mode ............................................................... 59
Tab. 47. CMOS mode ................................................... 60
Tab. 48. Low-Swing Mode .............................................60
Tab. 49. Phase Noise—2.4 GHz operation ................... 60
Tab. 50. Phase noise—Dual-band operation .................60
Tab. 51. Crystal specifications .......................................61
Tab. 52. External sleep clock timing ............................. 61
Tab. 53. JTAG timing data ............................................ 62
Tab. 54. Thermal conditions of QFN package ...............63
Tab. 55. Thermal conditions of eWLP package .............64
Tab. 56. Acronyms and abbreviations ...........................68
Tab. 57. Revision history ...............................................75
performance .................................................... 45
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
88W8977 functional block diagram ................... 2
88W8977 internal block diagram .......................4
Part numbering scheme ....................................5
88W8977 signal diagram ................................ 11
Pin assignement for 68-pin package option
(top view) .........................................................12
Pad locations—74-bump WLCSP (Non-
bump-side view, bumps down) ........................13
Configuration—VCORE from PMIC .................28
Configuration—VCORE from Internal LDO ..... 29
Power-up sequence ........................................ 30
Fig. 14. SDIO protocol timing diagram—Default
speed mode (3.3V) ......................................... 52
Fig. 15. SDIO protocol timing diagram—High-speed
mode (3.3V) .................................................... 52
Fig. 16. SDIO protocol timing diagram—SDR12,
SDR25, SDR50 modes (up to 100 MHz)
(1.8V) ...............................................................54
Fig. 17. SDIO CMD timing diagram—DDR50 Mode
(50 MHz) ......................................................... 55
Fig. 18. SDIO DAT[3:0] timing diagram—DDR50
mode (50 MHz) ............................................... 55
Fig. 19. Figure Caption .................................................57
Fig. 20. JTAG timing diagram .......................................62
Fig. 21. 68-pin QFN package mechanical drawing .......65
Fig. 22. 74-bump package mechanical drawing ...........66
Fig. 23. 68-pin QFN package marking and pin 1
location ............................................................ 67
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10. Recommended power-down sequence ...........31
Fig. 11.
Power-down using PMIC_EN host pin -
PMIC and 88W8977 both in power-down
mode ............................................................... 32
Fig. 12. Slew rate measurement diagram .................... 36
Fig. 13. RF performance measurement points .............38
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
78 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Fig. 24. 74-bump eWLP package marking and pin 1
location ............................................................ 67
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
79 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Contents
1
Product overview ................................................ 1
9
9.1
Electrical specifications ................................... 35
GPIO/LED interface specifications ...................35
VIO DC characteristics .................................... 35
1.8V operation ................................................. 35
2.5V operation ................................................. 35
3.3V operation ................................................. 35
LED mode ........................................................36
RF front-end control interface specifications ....37
VIO_RF DC characteristics ..............................37
1.8V operation ................................................. 37
3.3V operation ................................................. 37
Wi-Fi radio specifications .................................38
Wi-Fi radio performance measurement ........... 38
2.4 GHz Wi-Fi receiver performance ............... 39
5 GHz Wi-Fi receiver performance .................. 41
2.4 GHz Wi-Fi transmitter performance ........... 43
5 GHz Wi-Fi transmitter performance .............. 44
Local oscillator .................................................44
Bluetooth radio specifications ..........................45
Bluetooth/Bluetooth LE receiver
1.1
1.2
1.3
1.4
1.5
1.6
1.7
2
Applications ........................................................2
Wi-Fi key features ............................................. 2
Bluetooth key features .......................................2
Host interfaces ...................................................3
Operating characteristics ...................................3
General features ................................................3
Internal block diagram ....................................... 4
Ordering information .......................................... 5
Wi-Fi subsystem ..................................................6
IEEE 802.11 standards ......................................6
Wi-Fi MAC ......................................................... 6
Wi-Fi baseband ................................................. 7
Wi-Fi radio ......................................................... 7
Wi-Fi encryption .................................................8
Wi-Fi host interfaces ..........................................8
Bluetooth subsystem ..........................................9
Bluetooth ............................................................9
Bluetooth Low Energy (LE) ............................... 9
Bluetooth host interfaces .................................10
PCM interface ..................................................10
Pin information ..................................................11
Signal diagram .................................................11
Pin assignment - 68-pin QFN package
option ............................................................... 12
Pad locations - 74-bump eWLP .......................13
Pin description .................................................17
Pin types ..........................................................17
Pin states .........................................................17
General Purpose I/O (GPIO)/LED interface .....18
RF front-end control interface ..........................20
Wi-Fi/Bluetooth radio interface ........................ 20
Bluetooth external coexistence interface ......... 21
SDIO host interface ......................................... 22
UART host interface ........................................ 22
LTE external coexistence interface ..................23
PCM interface ..................................................23
Power management interface ..........................23
Power supply and ground pins ........................ 24
Clock interface .................................................24
Power-down pin ...............................................25
JTAG interface .................................................25
Configuration pins ............................................26
Power information .............................................27
Leakage optimization .......................................27
Power-up ..........................................................27
Configuration—PMIC supplies VCORE ........... 28
Configuration—Internal LDO supplies
9.1.1
9.1.1.1
9.1.1.2
9.1.1.3
9.1.2
9.2
9.2.1
9.2.1.1
9.2.1.2
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.4
3
3.1
3.2
3.3
3.4
3.5
3.6
4
4.1
4.2
4.3
4.4
5
9.4.1
performance .....................................................45
Bluetooth/Bluetooth LE transmitter
9.4.2
5.1
5.2
performance .....................................................47
Current consumption ....................................... 49
Coexistence specifications .............................. 50
SDIO host interface specifications ...................51
VIO_SD DC characteristics ............................. 51
1.8V operation ................................................. 51
3.3V operation ................................................. 51
Default speed mode and high-speed mode ..... 52
SDR12, SDR25, SDR50 modes (up to 100
MHz) (1.8V) ..................................................... 54
DDR50 Mode (50 MHz) (1.8V) ........................ 55
UART interface specifications ..........................57
PCM interface specifications ........................... 58
Clock specifications ......................................... 60
Single-ended clock input modes ......................60
9.5
9.6
9.7
9.7.1
9.7.1.1
9.7.1.2
9.7.2
9.7.3
5.3
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
5.4.9
5.4.10
5.4.11
5.4.12
5.4.13
5.4.14
5.4.15
5.5
9.7.4
9.8
9.9
9.10
9.10.1
9.10.1.1 2.4 GHz mode ................................................. 60
9.10.1.2 2.4 GHz and 5 GHz dual-band mode .............. 60
9.10.2
9.10.3
9.11
Crystal ..............................................................61
Sleep clock ...................................................... 61
JTAG interface specifications .......................... 62
Package information .........................................63
Package thermal conditions .............................63
QFN package thermal conditions .................... 63
eWLP package thermal conditions .................. 64
Package mechanical data ............................... 65
68-pin QFN package mechanical drawing ....... 65
74-bump eWLP package mechanical
drawing ............................................................ 66
Package marking .............................................67
68-pin QFN package marking ..........................67
74-bump eWLP package marking ................... 67
Acronyms and abbreviations ...........................68
Revision history ................................................ 75
Legal information ..............................................76
10
10.1
6
6.1
6.2
6.2.1
6.2.2
10.1.1
10.1.2
10.2
10.2.1
10.2.2
VCORE ............................................................ 29
Power-up sequence .........................................30
Power-down .....................................................31
Recommended power-down sequence ........... 31
Power-down using PMIC_EN host pin .............32
Deep sleep ...................................................... 32
Absolute maximum ratings ..............................33
Recommended operating conditions .............. 34
6.2.3
6.3
6.3.1
6.3.2
6.4
7
10.3
10.3.1
10.3.2
11
12
13
8
88W8977_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product short data sheet
Rev. 3 — 13 May 2021
80 / 81
NXP Semiconductors
88W8977_SDS
2.4ꢀGHz/5ꢀGHz Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.2 Combo SoC
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2021.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 13 May 2021
Document identifier: 88W8977_SDS
相关型号:
©2020 ICPDF网 联系我们和版权申明