88W8987-A2-EAHE/AZ_技术文档

88W8987_SDS

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2

Solution

Rev. 2 — 21 May 2021

Product short data sheet

1 Product overview

The 88W8987 is a highly integrated Wi-Fi (2.4/5 GHz) and Bluetooth single-chip solution,

specifically designed to support the speed, reliability, and quality requirements of next

generation Very High Throughput (VHT) products.

The System-on-Chip (SoC) provides both simultaneous and independent operation of the

following:

• IEEE 802.11ac (Wave 2), 1x1 with data rates up to MCS9 (433 Mbit/s)

• Bluetooth 5.2 (includes Bluetooth Low Energy (LE))

The SoC also provides:

• Bluetooth Classic and Bluetooth LE dual (Smart Ready) operation

• Wi-Fi indoor location positioning (802.11mc)

For security, the device supports high performance 802.11i security standards through

implementation of the Advanced Encryption Standard (AES)/Counter Mode CBC-

MAC Protocol (CCMP), AES/Galois/Counter Mode Protocol (GCMP), Wired Equivalent

Privacy (WEP) with Temporal Key Integrity Protocol (TKIP), AES/Cipher-Based Message

Authentication Code (CMAC), and WLAN Authentication and Privacy Infrastructure

(WAPI) security mechanisms.

For video, voice, and multimedia applications, 802.11e Quality of Service (QoS) is

supported. The device also supports 802.11h Dynamic Frequency Selection (DFS) for

detecting radar pulses when operating in the 5 GHz range.

Host interfaces include SDIO 3.0 and high-speed UART interfaces for connecting Wi-Fi

and Bluetooth technologies to the host processor.

The device is designed with two front-end configurations to accommodate Wi-Fi and

Bluetooth on either separate or shared paths:

• 2-antenna configuration—1x1 Wi-Fi and Bluetooth on separate paths (QFN)

• 1-antenna configuration—1x1 Wi-Fi and Bluetooth on shared paths (eWLP)

The following figures show the application diagrams for each package option.

NXP Semiconductors

88W8987_SDS

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

Wi-Fi

Antenna

88W8987

SDIO 3.0

Wi-Fi 5 GHz

Diplexer

Bluetooth UART

Wi-Fi 2.4 GHz

PCM

GPIO

Bluetooth

Antenna

Supply voltages

Power-down

Bluetooth Tx/Rx

XTAL_IN

XTAL_OUT

Figure 1.ꢀApplication diagram—QFN package option

88W8987

Antenna

SDIO 3.0

Wi-Fi 5 GHz Rx

Wi-Fi 5 GHz Tx

T/R

switch

Bluetooth UART

Diplexer

PCM

GPIO

Wi-Fi 2.4 GHz Tx/Rx and

Bluetooth Tx/Rx

Supply voltages

Power-down

XTAL_IN

XTAL_OUT

Figure 2.ꢀApplication diagram—eWLP package option

88W8987_SDS

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NXP Semiconductors

88W8987_SDS

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

1.1 Applications

• Wi-Fi and Bluetooth enabled smart phones and tablets

• Personal computing systems including notebooks and ultrabooks

• Wireless home audio and video entertainment systems

• Mobile routers and Internet of Things (IoT) gateways

1.2 Wi-Fi key features

• Support 802.11ac/n/a/g/b

• Dual band: 2.4 GHz and 5 GHz

• Up to MCS9 data rates

• 20/40/80 MHz channel bandwidth

• Security: TKIP, AES, WAPI

1.3 Bluetooth key features

• Bluetooth 5.2 support

• PCM audio interface

• Security: AES

1.4 Host interfaces

Wi-Fi and Bluetooth host interface options

Wi-Fi

Bluetooth

UART

SDIO 3.0

1.5 Operating characteristics

• Supply voltage: 2.2V, 1.8V, and 1.1V

• Operating temperature

– Extended: -30 to 85°C

– Industrial: -40 to 85°C

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88W8987_SDS

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

1.6 General features

• Package options

– 68-pin 8x8 mm QFN with wettable flanks

– 83-bump 4.6x4.2 mm eWLP

• Power management

– Low power dissipation

– Optional lower power operation with external sleep clock

– Sleep and standby modes for low-power operation

• Independent ARM-based Wi-Fi and Bluetooth CPUs

• Supports reference clock signal from external crystal or external crystal oscillator

• Memory

– Internal SRAM

– Boot ROM

– One Time Programmable (OTP) memory to store the MAC address and calibration

data

• Peripheral interfaces

– GPIO interface (up to 21)

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NXP Semiconductors

88W8987_SDS

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

1.7 Internal block diagram

Wi-Fi 5G Tx/Rx

1x1

Wi-Fi 5 RF

(802.11ac)

SDIO 3.0

Wi-Fi CPU

Wi-Fi 5 MAC/Baseband

(802.11ac)

Wi-Fi 2.4G Tx/Rx

UART

PCM

Bluetooth

CPU

Bluetooth/ Bluetooth LE

Baseband

Bluetooth Tx/Rx

Bluetooth RF

Supply voltages

Power regulator

OTP

Coexistence

Figure 3.ꢀInternal block diagram—QFN package option

Wi-Fi 5G Tx/Rx

1x1

Wi-Fi

1x1

Wi-Fi 5 RF

(802.11ac)

Wi-Fi 5 MAC/

SDIO 3.0

CPU

Wi-Fi 2.4G Tx/Rx

Bluetooth Tx/Rx

Baseband (802.11ac)

Wi-Fi 2.4 GHz Tx

Wi-Fi 2.4 GHz Rx

and Bluetooth Rx

S

P

3

T

UART

PCM

Bluetooth

CPU

Bluetooth/ Bluetooth

LE Baseband

Bluetooth

RF

Bluetooth Tx

Supply

voltages

Power regulator

OTP

Coexistence

Figure 4.ꢀInternal block diagram—eWLP package option

88W8987_SDS

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NXP Semiconductors

88W8987_SDS

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

2 Ordering information

88W8987-xx-xxxx/xx

Packing code

Temperature code

E = Extended

I = Industrial

Part number

Revision number

Package code

Figure 5.ꢀPart numbering scheme

Table 1.ꢀPart order codes

Part order code

Package type

Packing

88W8987-A2-NYEE/AK

88W8987-A2-NYEE/AZ

88W8987-A2-NYEI/AK

88W8987-A2-NYEI/AZ

88W8987-A2-EAHE/AZ

68-pin HVQFN - 8 x 8 x 0.85 mm, with 0.4 mm pitch

83-terminal eWLP - 4.6 x 4.2 x 0.75 mm, with 0.4 mm pitch

Tray

Tape and reel

Tray

Tape and reel

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88W8987_SDS

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

3 Wi-Fi subsystem

3.1 IEEE 802.11 standards

• 802.11 data rates of 1 and 2 Mbit/s

• 802.11b data rates of 5.5 and 11 Mbit/s

• 802.11a/g data rates 6, 9, 12, 18, 24, 36, 48, and 54 Mbit/s for multimedia content

transmission

• 802.11g/b performance enhancements

• 802.11ac / 802.11n with maximum data rates up to 86.7 Mbit/s (20 MHz channel), 200

Mbit/s (40 MHz channel), 433 Mbit/s (80 MHz channel)

• 802.11d international roaming

• 802.11e quality of service

• 802.11h transmit power control

• 802.11h DFS radar pulse detection

• 802.11i enhanced security

• 802.11k radio resource measurement

• 802.11mc precise indoor location positioning

• 802.11n block acknowledgment extension

• 802.11r fast hand-off for AP roaming

• 802.11u Hotspot 2.0 (STA mode only)

• 802.11v TIM frame transmission/reception

• 802.11w protected management frames

• Fully supports clients (stations) implementing IEEE Power Save mode

88W8987_SDS

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88W8987_SDS

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

3.2 Wi-Fi MAC

• Simultaneous peer-to-peer and Infrastructure Modes

• RTS/CTS for operation under DCF

• Hardware filtering of 32 multicast addresses and duplicate frame detection for up to 32

unicast addresses

• On-chip Tx and Rx FIFO for maximum throughput

• Open System and Shared Key Authentication services

• A-MPDU Rx (de-aggregation) and Tx (aggregation) (supports 802.11ac single-MPDU

A-MPDU)

• 20/40/80 MHz coexistence

• Reduced Inter-Frame Spacing (RIFS) receive

• Management information base counters

• Radio resource measurement counters

• Quality of service queues

• Block acknowledgment extension

• Dynamic frequency selection

• Beamforming

– 802.11ac Explicit Beamformee, supports immediate feedback generation using

802.11ac compressed steering matrix feedback

– 802.11ac Multi-User Beamformee

– 802.11n Explicit Beamformee, supports immediate feedback generation using

uncompress and compress steering matrix or delayed feedback of all feedback types

• TIM frame transmission/reception

• Multiple-BSS/Station

• Transmit rate adaptation

• Transmit power control

• Long and short preamble generation on a frame-by-frame basis for 802.11b frames

• Mobile hotspot

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88W8987_SDS

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

3.3 Wi-Fi baseband

• 802.11ac (on-chip RF radio)

• Backward compatibility with legacy 802.11n/a/g/b technology

• Simultaneous Wi-Fi and Bluetooth receive in single-antenna mode (eWLP only)

• PHY data rates up to 433 Mbit/s

• 20 MHz bandwidth/channel, 40 MHz bandwidth/channel, upper/lower 20 MHz packets

in 40 MHz channel, 20 MHz duplicate legacy packets in 40 MHz channel mode

operation

• 80 MHz bandwidth/channel, 4 positions of 20 MHz packets in 80 MHz channel, upper/

lower 40 MHz packets in 80 MHz channel, 20 MHz quadruplicate legacy packets in

80 MHz channel mode operation

• Modulation and Coding Scheme (MCS)

– 802.11ac—MCS 0~9 Nsts = 1

– 802.11n—MCS 0~7 and MCS 32 (duplicate 6 Mbit/s)

• Dynamic frequency selection (radar detection)

– Enhanced radar detection for long and short pulse radar

– Enhanced AGC scheme for DFS channel

– Japan DFS requirements for W53 and W56 frequency bands

• Radio resource measurement

• Optional 802.11ac and 802.11n features:

– 20/40/80 MHz coexistence with middle-packet detection (GI detection) for enhanced

CCA

– 1 spatial stream STBC reception

– LDPC transmission and reception for both 802.11n and 802.11ac

– 256 QAM (MCS 8, 9) modulation, optional support for 802.11ac MCS 9 in 20 MHz

using LDPC

– Short guard interval

– RIFS on receive path for 802.11n packets

– 802.11n greenfield Tx/Rx

– Explicit beamformee support

– 802.11ac multi-user beamformee

– MU-PPDUs (receive)

• Wi-Fi indoor locationing (802.11mc)

• Power save features

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NXP Semiconductors

88W8987_SDS

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

3.4 Wi-Fi radio

• Integrated direct-conversion radio

• 20, 40, and 80 MHz channel bandwidths

• Shared Wi-Fi/Bluetooth receive input scheme for 2.4 GHz band (eWLP only)

Wi-Fi Rx path

• Direct conversion architecture eliminates need for external SAW filter

• On-chip gain selectable LNA with optimized noise figure and power consumption

• High dynamic range AGC function in receive mode

Wi-Fi Tx path

• Internal PA with power control

• Optimized Tx gain distribution for linearity and noise performance

Wi-Fi local oscillator

• Fractional-N for multiple reference clock support

• Fine channel step

3.5 Wi-Fi encryption

• Temporal Key Integrity Protocol (TKIP) /

Wired Equivalent Privacy (WEP)

• Advanced Encryption Standard (AES) / Counter-Mode/CBC-MAC Protocol (CCMP)

• Advanced Encryption Standard (AES) /

Cipher-Based Message Authentication Code (CMAC)

• Advanced Encryption Standard (AES) / Galois/Counter Mode Protocol (GCMP)

• WLAN Authentication and Privacy Infrastructure (WAPI)

3.6 Wi-Fi host interfaces

• SDIO 3.0 device interface (4-bit SDIO and 1-bit SDIO) transfer modes at full clock

range up to 208 MHz

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88W8987_SDS

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

4 Bluetooth subsystem

4.1 2.4 GHz Bluetooth Tx/Rx

• Bluetooth 5.2

• Bluetooth Class 2

• Bluetooth Class 1

• Single-ended, shared Tx/Rx path for Bluetooth (QFN package option)

• Simultaneous Wi-Fi and Bluetooth receive in single-antenna mode (eWLP package

option)

• PCM interface for voice applications

• Baseband and radio BDR and EDR packet types—1 Mbit/s (GFSK), 2 Mbit/s ( /4-

DQPSK), and 3 Mbit/s (8DPSK)

• Fully functional Bluetooth baseband—AFH, forward error correction, header error

control, access code correlation, CRC, encryption bit stream generation, and whitening

• Adaptive Frequency Hopping (AFH) using Packet Error Rate (PER)

• Interlaced scan for faster connection setup

• Simultaneous active ACL connection support

• Automatic ACL packet type selection

• Full master and slave piconet support

• Scatternet support

• Standard SDIO and UART HCI transport layer

• HCI layer to integrate with profile stack

• SCO/eSCO links with hardware accelerated audio signal processing and hardware

supported PPEC algorithm for speech quality improvement

• All standard SCO/eSCO voice coding

• All standard pairing, authentication, link key, and encryption operations

• Standard Bluetooth power saving mechanisms

(sniff modes, and sniff sub-rating)

• Enhanced Power Control (EPC)

• Channel Quality Driven Data Rate (CQDDR)

• Wideband Speech (WBS) support (1 WBS link)

• Encryption (AES) support

4.2 Bluetooth Low Energy (LE)

• Broadcaster, Observer, Central, and Peripheral roles

• Supports link layer topology to be master and slave (connects up to 16 links)

• Wi-Fi/Bluetooth coexistence protocol support

• Shared RF with BDR/EDR

• Encryption (AES) support

• Intelligent Adaptive Frequency Hopping (AFH)

• Bluetooth LE Privacy 1.2

• Bluetooth LE Secure Connection

• Bluetooth LE Data Length Extension

• Bluetooth LE Advertising Extension

• 2 Mbit/s Bluetooth LE

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NXP Semiconductors

88W8987_SDS

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

4.3 Bluetooth host interfaces

• SDIO 3.0

• High-speed UART

4.4 Coexistence

• Internal coexistence arbitration for Wi-Fi/Bluetooth

4.5 PCM interface

• Master or slave mode

• PCM bit width size of 8 bits or 16 bits

• Up to 4 slots with configurable bit width and start positions

• PCM short frame and long frame¹synchronization

• Tri-state PCM interface capability

1

In PCM Master mode, PCM long frame synchronization is 1 clock wide. In PCM Slave mode, PCM

Master’s long frame synchronization pattern is supported.

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88W8987_SDS

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

5 Pin information

5.1 Signal diagrams

5.1.1 Signal diagram for QFN package option

Figure 6 shows the signals for the QFN package of the device.

Note: Signals may be muxed. See Section 5.5 "Pin description".

88W8987

RF_TR_2

Wi-Fi radio

interface

SD_CLK

SD_CMD

RF_TR_5

SDIO interface

SD_DAT[3:0]

Bluetooth radio

interface

BRF_ANT

UART_SIN

RF_CNTL0_N

RF_CNTL1_P

RF_CNTL2_N

RF_CNTL3_P

UART_SOUT

RF front-end control

interface

UART interface

UART_RTSn

UART_CTSn

CONFIG_HOST[0]

PCM_SYNC

PCM_CLK

PCM_DIN

Host configuration

CONFIG_HOST[1]

PCM interface

CONFIG_AUTO_REF_DET

PCM_DOUT

DVSC[0]

DVSC[1]

Power management

interface

GPIO[20:0]

LED_OUT_BT

GPIO/LED interface

LED_OUT_WLAN

XTAL_IN

XTAL_OUT

SLP_CLK_IN

Clock interface

Power-down

XOSC_EN

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

JTAG interface

PDn

Figure 6.ꢀSignal diagram—QFN

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88W8987_SDS

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

5.1.2 Signal diagram for eWLP package option

Figure 7 shows the signals for eWLP package option.

Note: Signals may be muxed. See Section 5.5 "Pin description".

88W8987

SD_CLK

SD_CMD

RF_TR_2 / BRF_ANT

SDIO interface

Wi-Fi radio interface

RF_TX_5

RF_RX_5

SD_DAT[3:0]

RF_CNTL0_N

RF_CNTL1_P

RF_CNTL2_N

RF_CNTL3_P

UART_SIN

UART_SOUT

RF front-end control

interface

UART interface

UART_RTSn

UART_CTSn

CONFIG_HOST[0]

PCM_SYNC

PCM_CLK

PCM_DIN

Host configuration

CONFIG_HOST[1]

CONFIG_AUTO_REF_DET

PCM interface

PCM_DOUT

DVSC[0]

DVSC[1]

Power management

interface

GPIO[20:0]

LED_OUT_BT

GPIO/LED interface

JTAG interface

XTAL_IN

LED_OUT_WLAN

XTAL_OUT

SLP_CLK_IN

Clock interface

Power-down

XOSC_EN

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

PDn

Figure 7.ꢀSignal diagram—eWLP

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88W8987_SDS

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

5.2 Pin types

Table 2.ꢀPin types

Pin type

Description

I/O

Digital input/output

Digital input

I

O

Digital output

Analog input

Analog output

Analog input/output

No connect

A, I

A, O

A, I/O

NC

DNC

Power

Ground

Do not connect

Power

Ground

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88W8987_SDS

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

5.3 Pin assignment—68-pin QFN

GPIO[7] 52

VIO 53

34 AVDD18

33 AVSS

32 RF_TR_5

SLP_CLK_IN 54

GPIO[1] 55

GPIO[16] 56

GPIO[17] 57

GPIO[18] 58

GPIO[19] 59

GPIO[20] 60

VCORE 61

VIO_SD 62

SD_CLK 63

SD_CMD 64

31 VPA

30 VPA

29 AVDD18

28 RF_TR_2

27 AVSS

26 AVSS

88W8987

25 VCORE

24 BRF_ANT

23 AVDD18

22 AVSS

SD_DAT[0]

SD_DAT[1]

SD_DAT[2]

SD_DAT[3]

65

66

67

68

21 AVDD18

20 AVDD18

19 RF_CNTL2_N

18 RF_CNTL3_P

Figure 8.ꢀPin assignment—68-pin QFN package option^[1]

[1] EPAD on pin 69.

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88W8987_SDS

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

5.3.1 Pin list by number

The following table shows the pin list sorted by pin number.

Table 3.ꢀPin list by number

Pin number

Pin name

GPIO[8]

GPIO[9]

GPIO[10]

VIO

Power

Type

I/O

1

VIO

2

VIO

I/O

3

VIO

I/O

4

--

Power

I/O

5

GPIO[11]

VCORE

GPIO[12]

GPIO[13]

GPIO[14]

GPIO[15]

GPIO[2]

GPIO[3]

PDn

VIO

6

--

Power

I/O

7

VIO

8

VIO

I/O

9

VIO

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

VIO

I/O

VIO

I/O

VIO

I/O

AVDD18

I

AVDD18

VIO_RF

RF_CNTL0_N

RF_CNTL1_P

RF_CTLN3_P

RF_CTLN2_N

AVDD18

AVSS

--

Power

O

--

VIO_RF

O

VIO_RF

O

VIO_RF

O

--

Power

Ground

Power

A, I/O

Power

Ground

A, I/O

Power

A, I/O

Ground

Power

--

AVDD18

BRF_ANT

VCORE

AVSS

--

AVDD18

--

AVSS

--

RF_TR_2

AVDD18

VPA

AVDD18

--

VPA

--

RF_TR_5

AVSS

AVDD18

--

AVDD18

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88W8987_SDS

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

Table 3.ꢀPin list by number...continued

Pin number

35

Pin name

AVSS

Power

--

Type

Ground

Power

I

36

AVSS

--

37

AVDD18

--

38

AVDD18

--

39

AVDD18

--

40

XTAL_IN

AVDD18

--

41

XTAL_OUT

AVDD18

O

42

Power

--

43

AVDD18

--

44

DNC

--

45

CONFIG_HOST[0]

CONFIG_HOST[1]

CONFIG_AUTO_REF_DET

GPIO[0]

AVDD18

VIO

I

46

I

47

I

48

I/O

49

GPIO[4]

VIO

I/O

50

GPIO[5]

VIO

I/O

51

GPIO[6]

VIO

I/O

52

GPIO[7]

VIO

I/O

53

VIO

--

Power

I

54

SLP_CLK_IN

GPIO[1]

VIO

55

VIO

I/O

56

GPIO[16]

GPIO[17]

GPIO[18]

GPIO[19]

GPIO[20]

VCORE

VIO

I/O

57

VIO

I/O

58

VIO

I/O

59

VIO

I/O

60

VIO

I/O

61

--

Power

I

62

VIO_SD

--

63

SD_CLK

VIO_SD

64

SD_CMD

SD_DAT[0]

SD_DAT[1]

SD_DAT[2]

SD_DAT[3]

I/O

65

I/O

66

I/O

67

I/O

68

I/O

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88W8987_SDS

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

5.4 Pad locations—83-bump eWLP

1

2

3

4

5

6

7

8

9

10

A

A1

A2

A3

A4

A5

A6

A8

A9

A10

B

C

B1

C1

B3

C3

B4

C4

B5

C5

B6

C6

B7

C7

B8

C8

B9

C9

B10

C10

C2

D2

E2

D

D1

E1

D3

D4

E4

D5

D6

D7

D8

D9

D10

E

F

E3

F3

E5

F5

E7

F7

E8

F8

E9

F9

E10

F10

G

H

G2

H2

G3

H3

G4

H4

G5

H5

G6

G7

H7

G8

G9

G10

H10

H1

J

J3

J8

J9

J10

K

K1

K2

K3

K4

K5

K6

K7

K8

K9

K10

Non-Bump-Side View

Alphanumeric designations are approximations to the grid.

Figure 9.ꢀPad locations—83-bump eWLP (non-bump-side view, bumps down)

Table 4 indicates the pad locations in 83-bump eWLP package.

Note: Alphanumeric designations are approximations to the grid shown in Figure 9

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Table 4.ꢀPad locations—83-bump eWLP

Signal name

Alpha-numeric

designation

Pad location relative to die

center (non-bump-side view)

X

Y

NC

A1

A2

A3

A4

A5

A6

A8

A9

A10

-1800.0

-1400.0

-1000.0

-600.0

-200.0

200.0

1800.0

GPIO[18]

VSS

GPIO[19]

VCORE

VIO_SD

VSS

1000.0

1400.0

1800.0

SD_DAT[3]

VSS

VIO

B1

B3

B4

B5

B6

B7

B8

B9

B10

-1800.0

-1000.0

-600.0

-200.0

200.0

1400.0

SLP_CLK_IN

GPIO[16]

GPIO[17]

GPIO[20]

SD_CLK

600.0

SD_DAT[0]

SD_DAT[1]

SD_DAT[2]

1000.0

1400.0

1800.0

AVDD18

AVSS

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

-1800.0

-1400.0

-1000.0

-600.0

-200.0

200.0

1000.0

GPIO[0] / XOSC_EN

GPIO[6]

GPIO[7]

GPIO[1]

SD_CMD

GPIO[10]

GPIO[8]

600.0

1000.0

1400.0

1800.0

VIO

XTAL_IN

D1

D2

D3

D4

D5

D6

-1800.0

-1400.0

-1000.0

-600.0

-200.0

200.0

600.0

XTAL_OUT

DNC

CONFIG_HOST[0]

GPIO[4]

GPIO[5]

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Table 4.ꢀPad locations—83-bump eWLP...continued

Signal name

Alpha-numeric

designation

Pad location relative to die

center (non-bump-side view)

X

Y

GPIO[12]

GPIO[9]

GPIO[11]

VCORE

D7

D8

600.0

1000.0

1400.0

1800.0

600.0

D9

D10

AVDD18

E1

E2

E3

E4

E5

E7

E8

E9

E10

-1800.0

-1400.0

-1000.0

-600.0

-200.0

600.0

200.0

AVSS

AVDD18

AVSS

CONFIG_AUTO_REF_DET

GPIO[13]

GPIO[3]

1000.0

1400.0

1800.0

GPIO[15]

GPIO[14]

AVSS

F3

F5

-1000.0

-200.0

600.0

-200.0

CONFIG_HOST[1]

GPIO[2]

PDn

F7

F8

1000.0

1400.0

1800.0

AVDD18

VSS

F9

F10

AVDD18

G2

G3

G4

G5

G6

G7

G8

G9

G10

-1400.0

-1000.0

-600.0

-200.0

200.0

-600.0

AVSS

VCORE

AVSS

RF_CNTL0_N

RF_CNTL1_P

RF_CNTL3_P

RF_CNTL2_N

VIO_RF

600.0

1000.0

1400.0

1800.0

AVSS

H1

H2

H3

H4

H5

H7

-1800.0

-1400.0

-1000.0

-600.0

-200.0

600.0

-1000.0

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Table 4.ꢀPad locations—83-bump eWLP...continued

Signal name

Alpha-numeric

designation

Pad location relative to die

center (non-bump-side view)

X

Y

AVSS

H10

1800.0

-1000.0

VPA

J3

J8

-1000.0

1000.0

1400.0

1800.0

-1400.0

AVSS

J9

J10

NC

K1

K2

K3

K4

K5

K6

K7

K8

K9

K10

-1800.0

-1400.0

-1000.0

-600.0

-200.0

200.0

-1800.0

RF_RX_5

RF_TX_5

RF_TR_2 / BRF_ANT

AVDD18

AVSS

AVDD18

NC

600.0

1000.0

1400.0

1800.0

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5.5 Pin description

5.5.1 Pin states

The pin states information provided in the tables includes:

• No Pad Power State indicates the state when there is no power

• PwrDwn State denotes the power-down state in default configuration. Many pads have

programmable power-down values, which can be set by firmware.

• Reset State is the state after the power-on-reset state and before the hardware state

(HW State)

• HW State (hardware state) is the state after boot code finishes and before firmware

download begins (firmware may change the pin state). HW State may differ based on

the pin muxing/strap setting. For example, for UART_RTSn and UART_SOUT, the boot

code will enable the UART interface when the device is in SDIO-UART mode, making

the HW states output high and output low, respectively.

• PwrDwn Prog indicates if the power-down state can be programmed

• Internal PU/PD columns indicates the following:

– Type of PU/PD (weak vs nominal)

– The polarity (PU vs. PD)

The internal pull-up or pull-down applies when the pin is in input mode

• PU denotes whether the pull-up can be programmed or not

• PD denotes whether the pull-down can be programmed or not

• Pull-up and pull-down are only effective when the pad is in input mode

• After firmware is downloaded, the pads (GPIO, RF control, and so on) are programmed

in functional mode per the functionality of the pins

5.5.2 General purpose I/O (GPIO)

Table 5.ꢀGeneral purpose I/O (GPIO)^[1](MFP)

Pins may be Multi-Functional Pins (MFP).

Pin Name Supply

No Pad

Power

State^[2]

Reset

State

HW State

PwrDwn PwrDwn Internal PU/

PU

PD

State

Prog

PD

GPIO[20] VIO

tristate

output

output high^[3]

tristate

yes

weak PU

yes

GPIO Mode: GPIO[20] (input/output).

This pin can be used for Bluetooth to host wake-up (out-of-band wake-up signal)

GPIO[19] VIO tristate output output high tristate yes

GPIO Mode: GPIO[19] (input/output)

Power Management Mode: DVSC[1] digital voltage scaling control (output)

GPIO[18] VIO tristate output output high tristate yes

GPIO Mode: GPIO[18] (input/output)

Power Management Mode: DVSC[0] digital voltage scaling control (output)

GPIO[17] VIO tristate input input tristate yes

GPIO Mode: GPIO[17] (input/output)

JTAG Mode: JTAG_TDO, JTAG test data (output)

This pin is used as a configuration pin: CON[9] (input). See Section 5.6 "Configuration pins".

weak PU

yes

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Table 5.ꢀGeneral purpose I/O (GPIO)^[1](MFP)...continued

Pins may be Multi-Functional Pins (MFP).

Pin Name Supply

No Pad

Power

State^[2]

Reset

State

HW State

PwrDwn PwrDwn Internal PU/

PU

PD

State

Prog

PD

GPIO[16] VIO

tristate

input

tristate

yes

nominal PU

yes

GPIO Mode: GPIO[16] (input/output)

JTAG Mode: JTAG_TDI, JTAG test data (input)

GPIO[15] VIO tristate input input

output

high

yes

nominal PU

yes

GPIO Mode: GPIO[15] (input/output).

This pin can also be used as Bluetooth independent reset.

JTAG Mode: JTAG_TMS, JTAG controller select (input)

GPIO[14] VIO

tristate

input

tristate

yes

nominal PU

yes

GPIO Mode: GPIO[14] (input/output)

This pin can also be used as Wi-Fi independent reset.

JTAG Mode: JTAG_TCK, JTAG test clock (input)

GPIO[13] VIO

tristate

input

input^[4]

output^[5]

output

high

GPIO Mode: GPIO[13] (input/output)

This pin can also be used for host to 88W8987 Wi-Fi wake-up (out-of-band wake-up signal).

GPIO[12] VIO tristate input input tristate yes nominal PU

GPIO Mode: GPIO[12] (input/output)

This pin can also be used for host to 88W8987 Bluetooth wake-up (out-of-band wake-up signal)

yes

GPIO[11] VIO

tristate

input

input^[4]

output^[5]

output

high

yes

weak PU

GPIO Mode: GPIO[11] (input/output)

UART Mode: UART_RTSn (output) (active low)

This pin is used as a configuration pin: CON[8] (input). See Section 5.6 "Configuration pins".

GPIO[10] VIO

tristate

input

tristate

yes

nominal PU

weak PU

yes

GPIO Mode: GPIO[10] (input/output)

UART Mode: UART_CTSn (input) (active low)

GPIO[9]

VIO

tristate

input

tristate

yes

GPIO Mode: GPIO[9] (input/output)

UART Mode: UART_SIN (input)

GPIO[8]

VIO

tristate

input

input^[4]

output^[5]

output low yes

GPIO Mode: GPIO[8] (input/output)

UART Mode: UART_SOUT (output)

This pin is used as a configuration pin: CONFIG_XOSC_SEL (input). See Section 5.6 "Configuration pins".

GPIO[7]

VIO

tristate

input

tristate

yes

nominal PU

yes

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Table 5.ꢀGeneral purpose I/O (GPIO)^[1](MFP)...continued

Pins may be Multi-Functional Pins (MFP).

Pin Name Supply

No Pad

Power

State^[2]

Reset

State

HW State

PwrDwn PwrDwn Internal PU/

PU

PD

State

Prog

PD

GPIO Mode: GPIO[7] (input/output)

PCM Mode: PCM_SYNC (input/output)

• Output if master

• Input if slave

GPIO[6]

VIO

tristate

input

tristate

yes

nominal PU

weak PU

yes

GPIO Mode: GPIO[6] (input/output)

PCM Mode: PCM_CLK (input/output)

• Output if master

• Input if slave

GPIO[5]

VIO

tristate

input

GPIO Mode: GPIO[5] (input/output)

PCM Mode: PCM_DOUT (output)

This pin is used as a configuration pin: CON[7] (input). See Section 5.6 "Configuration pins".

GPIO[4]

VIO

tristate

input

tristate

yes

nominal PU

weak PU

yes

no

GPIO Mode: GPIO[4] (input/output)

PCM Mode: PCM_DIN (input)

GPIO[3]

VIO

tristate

output

output high^[3]

input

GPIO Mode: GPIO[3] (input/output)

LED Mode: LED_OUT_BT (output)

GPIO[2]

VIO

tristate

output

GPIO Mode: GPIO[2] (input/output)

LED Mode: LED_OUT_WLAN (output)

GPIO[1]

GPIO Mode: GPIO[1] (input/output).

This pin can also be used for 88W8987 Wi-Fi to host wake-up (out-of-band wake-up signal).

GPIO[0] VIO tristate output output high output low yes nominal PU

GPIO Mode: GPIO[0] (input/output)

VIO

tristate

input

Oscillator Enable Mode: XOSC_EN (output) (active high). See Section 5.5.9 "Clock interface".

[1] Not all GPIO pins can be used for Host-to-SoC wakeup signals.

[2] Maximum input voltage is 0.4V when VIO has no power (or in uncertain situations).

[3] The signal may toggle while boot code is executing.

[4] When the device is in SDIO-SDIO mode.

[5] When the device is in SDIO-UART mode.

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5.5.3 Wi-Fi/Bluetooth radio interface

Table 6.ꢀWi-Fi/Bluetooth radio interface - QFN package

Pin Name

RF_TR_2

RF_TR_5

BRF_ANT

Type

A, I/O

Supply

Description

AVDD18

Wi-Fi Transmit/Receive (2.4 GHz)

Wi-Fi Transmit/Receive (5 GHz)

Bluetooth Transmit/Receive

Table 7.ꢀWi-Fi/Bluetooth radio interface - eWLP package option

Pin Name

Type

Supply

Description

RF_TR_2/BRF_ANT

A, I/O

AVDD18

Wi-Fi Transmit/Receive (2.4 GHz)

Bluetooth Transmit/Receive (shared path for Wi-Fi and Bluetooth)

RF_RX_5

RF_TX_5

A, I

AVDD18

Wi-Fi Receive (5 GHz)

Wi-Fi Transmit (5 GHz)

A, O

5.5.4 Wi-Fi RF front-end control interface

Table 8.ꢀWi-Fi RF front-end control interface

Pin Name

Supply

No Pad

Power

State^[1]

Reset

State

HW State PwrDwn

State

PwrDwn

Prog

Internal

PU/PD

PU

PD

RF_CNTL0_N

VIO_RF

tristate

output

drive low

drive high

yes

nominal PU no

no

RF Control 0—RF Control Output Low (output)

RF_CNTL1_P VIO_RF tristate output

RF Control 1—RF Control Output High (output)

This pin is used as a configuration pin: CON[6] (input). See Section 5.6 "Configuration pins".

weak PU

no

RF_CNTL2_N

RF Control 2—RF Control Output Low (output)

RF_CNTL3_P VIO_RF tristate output

RF Control 3—RF Control Output High (output)

VIO_RF

tristate

output

drive low

yes

weak PU

no

output

drive high

yes

[1] Maximum input voltage is 0.4V when VIO_RF has no power (or in uncertain situations).

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5.5.5 SDIO host interface

Table 9.ꢀSDIO host interface

Pin Name

Supply

No Pad

Power

State^[1]

Reset

State

HW

State

PwrDwn

State

PwrDwn

Prog

Internal PU/ PU

PD

SD_CLK

VIO_SD

tristate

input

tristate

no

nominal PU

yes

SDIO 4-bit Mode: Clock input

SDIO 1-bit Mode: Clock input

SD_CMD

VIO_SD

tristate

input

yes

SDIO 4-bit Mode: Command/response (input/output)

SDIO 1-bit Mode: Command line

SD_DAT[3]

VIO_SD

tristate

input

SDIO 4-bit Mode: Data line Bit[3]

SDIO 1-bit Mode: Reserved

SD_DAT[2]

VIO_SD

tristate

input

SDIO 4-bit Mode: Data line Bit[2] or read wait (optional)

SDIO 1-bit Mode: Read wait (optional)

SD_DAT[1]

VIO_SD

tristate

input

SDIO 4-bit Mode: Data line Bit[1]

SDIO 1-bit Mode: Interrupt

SD_DAT[0]

VIO_SD

tristate

input

SDIO 4-bit Mode: Data line Bit[0]

SDIO 1-bit Mode: Data line

[1] Maximum input voltage is 0.4V when VIO_SD has no power (or in uncertain situations).

5.5.6 UART host interface

Table 10.ꢀUART host interface (MFP)

Pins may be Multi-Functional Pins (MFP).

Pin Name

Type

Supply

VIO

Description

UART_SIN

UART_SOUT

UART_RTSn

I

UART serial input signal - GPIO[9] input/output

UART serial output signal - GPIO[8] input/output

O

VIO

UART request-to-send output signal . Active low - GPIO[11] input/

output

UART_CTSn

I

VIO

UART clear-to-send input signal - Active low - GPIO[10] input/output

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5.5.7 Audio interface

Table 11.ꢀAudio interface pins (MFP)

Pins may be Multi-Functional Pins (MFP).

Pin Name

PCM_DIN

PCM_DOUT

PCM_CLK

Type

I

Supply

Description

VIO

Receive PCM input signal. GPIO[4] input/ouput

Transmit PCM output signal. GPIO[5] input/ouput

O

I/O

PCM data clock. GPIO[6] input/output

• Output if master

• Input if slave

PCM_SYNC

I/O

VIO

PCM frame sync. GPIO[7] input/ouput

• Output if master

• Input if slave

5.5.8 Configuration interface

Table 12.ꢀConfiguration interface

Pin Name Supply

No Pad

Power

State

Reset

State

HW

State

PwrDwn

State

PwrDwn

Prog

Internal

PU/PD

PU

PD

CONFIG_HOST[0] AVDD18

tristate

input

tristate

no

weak PU

yes

This pin is used as a configuration pin: CONFIG_HOST[0] (input). See Section 5.6 "Configuration pins".

CONFIG_HOST[1] AVDD18 tristate input input tristate no weak PU

This pin is used as a configuration pin: CONFIG_HOST[1] (input). See Section 5.6 "Configuration pins".

CONFIG_AUTO_

REF_DET

AVDD18

tristate

input

tristate

no

weak PU

This pin is used as a configuration pin: CONFIG_AUTO_REF_DET (input). See Section 5.6 "Configuration pins".

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5.5.9 Clock interface

Table 13.ꢀClock interface (MFP)

Pins may be Multi-Functional Pins (MFP).

Pin Name

Supply

No Pad

Power

State^[1]

Reset

State

HW

State

PwrDwn

State

PwrDwn

Prog

Internal PU/ PU

PD

XTAL_IN

AVDD18

--

Reference Clock Input

Reference clock signal frequency must be 26 MHz or 38.4 MHz from an external crystal or external crystal oscillator.

Power consumption in sleep mode is lower with an external crystal compared to an external crystal oscillator when an

external sleep clock is not used.

See Section 9.9 "Reference clock specifications".

XTAL_OUT

Connect this pin to an external crystal when an external crystal is used.

When an external crystal oscillator is used, connect this pin to ground with resistance less than 5 kΩ.

SLP_CLK_IN VIO tristate input tristate no nominal PU yes

input^[2]

Sleep Clock Input (optional)

Used for lower power operation in sleep mode.

AVDD18

--

yes

• An external sleep clock of 32.768 kHz can be used for lowest current consumption in sleep mode.

• An external sleep clock is required if automatic reference clock frequency detection is used. See Section 5.6

"Configuration pins".

• If no external sleep clock is used, leave this pin floating (DNC).

XOSC_EN

VIO

--

Oscillator Enable (output) (active high)

XOSC_EN signal can be used ONLY when an external sleep clock is used.

Used to enable an external oscillator.

0 = disable external oscillator

1 = enable external oscillator

NOTE: Muxed with GPIO[0].

[1] Maximum input voltage is 0.4V when VIO has no power (or in uncertain situations).

[2] Input mode after reset

5.5.10 Power down (PDn) pin

Table 14.ꢀPower down (PDn) pin

Pin Name

Supply

No Pad

Power

State

Reset

State

HW

State

PwrDwn

State

PwrDwn

Prog

Internal PU/ PU

PD

PDn

AVDD18

--

Full Power-down (input) (active low)

0 = full power-down mode

1 = normal mode

• PDn can accept an input of 1.8V to 4.5V

• PDn may be driven by the host

• PDn must be high for normal operation

No internal pull-up on this pin.

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5.5.11 Power supply and ground

Table 15.ꢀPower supply and ground

Pin Name

VCORE

VIO

Type

Description

Power

Ground

NC

1.10V Core Power Supply

1.8V/3.3V Digital I/O Power Supply

1.8V Digital I/O SDIO Power Supply

1.8V/3.3V Analog I/O RF Power Supply

1.8V Analog Power Supply

2.2V Analog Power Supply

Ground

VIO_SD

VIO_RF

AVDD18

VPA

AVSS

NC

Not Connected

DNC

Do Not Connect

Do not connect these pins. Leave these pins floating.

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5.6 Configuration pins

Table 16 shows the pins used as configuration inputs to set parameters following a reset.

The definition of these pins changes immediately after reset to their usual function.

To set a configuration bit to 0, attach a 50 kΩ–100 kΩ resistor from the pin to ground. No

external circuitry is required to set a configuration bit to 1.

See Section 9.11 "Configuration pin specifications" for the internal pull-up values of the

configuration pins.

Table 16.ꢀConfiguration pins

Configuration Bits

CON[9]

Pin Name

GPIO[17]

GPIO[11]

GPIO[5]

Configuration Function

Reserved

Set to 1.

CON[8]

CON[7]

CON[6]

RF_CNTL1_P

Reserved

Set to 1.

CONFIG_XOSC_SEL

GPIO[8]/UART_SOUT

Reference clock frequency select

Valid when CONFIG_AUTO_REF_DET = 0

0 = 38.4 MHz

1 = 26 MHz (default)

CONFIG_AUTO_REF_ CONFIG_AUTO_REF_ Reference clock frequency detection select

DET

0 = reference clock frequency detection by CONFIG_XOSC_SEL

1 = reference clock frequency detection using external sleep clock

(default)(valid only when external sleep clock is used)

CON[1]

CON[0]

CONFIG_HOST[1]

CONFIG_HOST[0]

Host configuration options

No hardware impact. Software reads and boots accordingly. See

Table 17.

Table 17.ꢀHost configuration options

Strap Value

Wi-Fi

Bluetooth/

Number of SDIO Functions

Bluetooth LE

00 (reserved)

--

01 (reserved)

--

10

11

SDIO

UART

SDIO

1 (Wi-Fi)

2 (Wi-Fi, Bluetooth)

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6 Power information

Section 5.5.11 "Power supply and ground" shows the required voltage levels for each rail

and for PDn input signal.

6.1 Power-up sequence

• VIO/VIO_RF must be good (90%) before or at the same time all other power supplies

start ramping up.

• VIO/VIO_RF must be good (90%) before or at the same time PDn starts ramping up.

• VPA must be good (90%) before or at the same time AVDD18 starts ramping up.

• It is recommended to start ramping up AVDD18 ≤1 ms after VPA ramps up.

• AVDD18 must be good (90%) before or at the same time VCORE starts ramping up.

• Ramp-up time of VIO/VIO_RF must be <100 ms.

• Ramp-up time of VPA must be <100 ms.

• Ramp-up time of AVDD18 must be <100 ms.

• Ramp-up time of VCORE must be <5 ms.

• All supplies must be monotonic.

• If using an external crystal oscillator, the reference clock must be stable before PDn

ramps up.

Figure 10 shows the power-up sequence.

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Power_good (90%)

2.2V

1.8V

VIO/VIO_RF

VPA

Power_good (90%)

AVDD18

PDn

1.1V

VCORE

Internal POR

XTAL_IN

(if external crystal

oscillator is used)

XTAL_IN

(if external crystal

is used)

Boot ROM execution starts

and firmware download

begins

Strap/Internal

RESETn

Figure 10.ꢀPower-up sequence

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6.2 Power-down sequence

It is recommended:

• To ramp down AVDD18 after VPA ramps down

• To discharge all of the power supplies to less than 0.2V to reduce leakage.

PDn must be asserted when powering down the device.

Figure 11 shows the power-down sequence.

VPA (2.2V)

Less than 0.2V

AVDD18 (1.8V)

Less than 0.2V

Figure 11.ꢀPower-down sequence

6.3 Reset

88W8987 is reset to its default operating state under any of the following conditions:

• Internal Power-On Reset (POR): POR is triggered when the device receives power and

VCORE and AVDD18 supplies are good. See Section 6.1 "Power-up sequence".

• Software/Firmware reset: the software or firmware issues a reset.

• External PDn pin assertion: the device is reset when the PDn input pin is <0.2V and

transitions from low to high.

See Section 9.10 "Power-down (PDn) pin specifications" for the electrical specifications.

6.3.1 Lowest power state

The device can be put into the lowest power mode of operation to conserve energy when

Wi-Fi and Bluetooth are not in use.

To put the device in the lowest power mode, assert PDn low to enter power-down mode.

Once PDn is de-asserted, the power sequence must be followed. If the firmware is not

downloaded, the device must be kept in power-down mode to reduce leakage.

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7 Absolute maximum ratings

CAUTION: The absolute maximum ratings table defines the limitations for electrical and

thermal stresses. These limits prevent permanent damage to the device. Exposure to

conditions at or beyond these ratings is not guaranteed and can damage the device.

Table 18.ꢀAbsolute maximum ratings

Symbol

VCORE

VIO

Parameter

Min

--

Max

1.21

2.2^[1]

4.0^[2]

2.2

2.2^[3]

4.0^[4]

1.98

2.3

Units

V

1.10V core power supply

1.8V/3.3V digital I/O power supply

--

V

--

V

VIO_SD

VIO_RF

1.8V digital I/O SDIO power supply

1.8V/3.3V I/O power supply

--

V

--

V

--

V

AVDD18

VPA

1.8V analog power supply

2.2V analog power supply

Storage Temperature

--

V

--

V

T_STORAGE

-55

+125

°C

[1] When using 1.8V digital I/O power supply

[2] When using 3.3V digital I/O power supply

[3] When using 1.8V I/O power supply

[4] When using 3.3V I/O power supply

Table 19.ꢀLimiting values - QFN option

Symbol

Parameter

Condition

Min

Max

Unit

kV

V

V_ESD

Electrostatic discharge

human body model (HBM)^[1]

charged device model (CDM)^[2]

-1.5

+1.5

-500

+500

[1] According to ANSI/ESDA/JEDEC JS-001.

[2] According to ANSI/ESDA/JEDEC JS-002

Table 20.ꢀLimiting values - eWLP option

Symbol

Parameter

Condition

Min

-1.5

-400

Max

+1.5

+400

Unit

kV

V

V_ESD

Electrostatic discharge

human body model (HBM)^[1]

charged device model (CDM)^[2]

[1] According to ANSI/ESDA/JEDEC JS-001.

[2] According to ANSI/ESDA/JEDEC JS-002

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8 Recommended operating conditions

Note: Operation beyond the recommended operating conditions is neither

recommended nor guaranteed.

Table 21.ꢀRecommended operating conditions

Symbol

VCORE

VIO

Parameter

Condition

Min

1.05

1.67

3.07

1.67

3.07

1.71

2.09

-30

Typ

1.10

1.8

3.3

1.8

3.3

1.8

2.2

--

Max

1.15

1.92

3.53

1.92

3.53

1.89

2.26

85

Units

V

1.10V core power supply

--

1.8V/3.3V digital I/O power supply

V

VIO_SD

VIO_RF

1.8V digital I/O SDIO power supply

1.8V/3.3V I/O power supply

--

V

AVDD18

VPA

1.8V analog power supply

2.2V analog power supply

Ambient operating temperature

--

V

--

V

T_A

Extended

Industrial

--

°C

-40

--

85

T_J

Maximum junction temperature

--

125

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9 Electrical specifications

9.1 GPIO/LED interface specifications

9.1.1 VIO DC characteristics

9.1.1.1 1.8V operation

Table 22.ꢀDC electrical characteristics—1.8V operation (VIO)

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

V_IH

Parameter

Input high voltage

Input low voltage

Input hysteresis

Condition

Min

0.7*VIO

-0.4

Typ

--

Max

VIO+0.4

0.3*VIO

--

Unit

V

--

V_IL

--

V

V_HYS

V_OH

V_OL

100

--

mV

V

Output high voltage

Output low voltage

VIO-0.4

--

0.4

V

9.1.1.2 3.3V operation

Table 23.ꢀDC electrical characteristics—3.3V operation (VIO)

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

V_IH

Parameter

Input high voltage

Input low voltage

Input hysteresis

Condition

Min

0.7*VIO

-0.4

Typ

--

Max

VIO+0.4

0.3*VIO

--

Unit

V

--

V_IL

--

V

V_HYS

V_OH

V_OL

100

--

mV

V

Output high voltage

Output low voltage

VIO-0.4

--

0.4

V

9.1.2 LED mode

Table 24.ꢀLED mode data

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

Parameter

Condition

Typ

Unit

I_OH

Switching current high

Tristate on pad (requires pull-up on board)

Tristate when

driving high

mA

I_OL

Switching current low

@ 0.4V

10

mA

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9.2 RF front-end control interface specifications

9.2.1 VIO_RF DC characteristics

9.2.1.1 1.8V operation

Table 25.ꢀDC electrical characteristics—1.8V operation (VIO_RF)

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

V_IH

Parameter

Input high voltage

Input low voltage

Input hysteresis

Condition

Min

0.7*VIO_RF

-0.4

Typ

--

Max

Unit

V

--

VIO_RF+0.4

V_IL

--

0.3*VIO_RF

V

V_HYS

V_OH

V_OL

100

--

mV

V

Output high voltage

Output low voltage

VIO_RF-0.4

--

0.4

V

9.2.1.2 3.3V operation

Table 26.ꢀDC electrical characteristics—3.3V operation (VIO_RF)

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

V_IH

Parameter

Input high voltage

Input low voltage

Input hysteresis

Condition

Min

0.7*VIO_RF

-0.4

Typ

--

Max

Unit

V

--

VIO_RF+0.4

V_IL

--

0.3*VIO_RF

V

V_HYS

V_OH

V_OL

100

--

mV

V

Output high voltage

Output low voltage

VIO_RF-0.4

--

0.4

V

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9.3 Wi-Fi radio specifications

9.3.1 Wi-Fi radio performance measurement

The Wi-Fi transmit/receive performance is measured either at the antenna port or at the

chip port.

88W8987

Wi-Fi 5G Tx/Rx

Filter

Diplexer

Wi-Fi 2.4G Tx/Rx

Antenna

port

Chip port

Figure 12.ꢀRF performance measurement points

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9.3.2 2.4 GHz Wi-Fi receiver performance

Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and at

chip port.

Table 27.ꢀ2.4 GHz Wi-Fi receiver performance

Parameter

Conditions

Min

2400

--

Typ

--

Max

2500

--

Unit

MHz

dBm

RF frequency range

20 MHz and 40 MHz bandwidths

Rx input IP3 at RF high gain (In-Band) Rx input IP3 when LNA in high gain

mode (24 dB) at chip input

-20

Maximum Rx input level

Maximum Rx input level without device

damage

--

2

dBm

1 Mbit/s

2 Mbit/s

5.5 Mbit/s

11 Mbit/s

6 Mbit/s

9 Mbit/s

12 Mbit/s

18 Mbit/s

24 Mbit/s

36 Mbit/s

48 Mbit/s

54 Mbit/s

MCS0

--

-99

-95

-93

-90

-89

-88

-87

-85

-81

-77

-76^[1]

-89

-88

-85

-83

-80

-76

-74

-73

-87

-86

-84

-81

-77

-73

-72

-71

--

dBm

Receiver sensitivity 802.11b

Receiver sensitivity 802.11g

MCS1

MCS2

Receiver sensitivity 802.11n HT20^[1]

BCC waveform

MCS3

MCS4

MCS5

MCS6

MCS7

MCS0

MCS1

MCS2

Receiver sensitivity 802.11n HT40^[1]

BCC waveform

MCS3

MCS4

MCS5

MCS6

MCS7

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Table 27.ꢀ2.4 GHz Wi-Fi receiver performance...continued

Parameter

Conditions

802.11b

802.11g

802.11n MCS0-4

802.11n MCS5-6

802.11n MCS7

1 Mbit/s

2 Mbit/s

5.5 Mbit/s

11 Mbit/s

6 Mbit/s

9 Mbit/s

12 Mbit/s

18 Mbit/s

24 Mbit/s

36 Mbit/s

48 Mbit/s

54 Mbit/s

MCS0

Min

--

Typ

-1

Max

--

Unit

dBm

dB

-2

Receiver maximum input level

-1

-2

-5

54

49

47

45

37

35

39

36

33

27

24

37

36

30

28

26

21

20

33

32

29

27

26

22

19

17

dB

Receiver adjacent channel interference

rejection (ACI) 802.11b

dB

Receiver adjacent channel interference

rejection (ACI) 802.11g

dB

MCS1

dB

MCS2

dB

MCS3

dB

Receiver adjacent channel interference

rejection (ACI) 802.11n, HT20

MCS4

dB

MCS5

dB

MCS6

dB

MCS7

dB

MCS0

dB

MCS1

dB

MCS2

dB

MCS3

dB

Receiver adjacent channel interference

rejection (ACI) 802.11n, HT40,

MCS4

dB

MCS5

dB

MCS6

dB

MCS7

dB

[1] De-sense of ~2 dB at 2472 MHz

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9.3.3 5 GHz Wi-Fi receiver performance

Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and at the

chip port.

Table 28.ꢀ5 GHz Wi-Fi receiver performance

Parameter

Conditions

Min

4900

—

Typ

--

Max

5925

—

Unit

MHz

dBm

RF frequency range

5 GHz—IEEE 802.11ac/n/a

Rx input IP3 at RF high gain (In-Band) Rx Input IP3 when LNA in high gain

mode (24 dB) at chip input

-20

Maximum Rx input level

Maximum Rx input level without device

damage

—

2

dBm

6 Mbit/s

9 Mbit/s

12 Mbit/s

18 Mbit/s

24 Mbit/s

36 Mbit/s

48 Mbit/s

54 Mbit/s

MCS0

--

-92

-91

-89

-86

-83

-78

-77

-92

-90

-87

-84

-81

-76

-75

-73

-88

-87

-84

-81

-78

-74

-73

-71

--

dBm

Receiver sensitivity 802.11a

MCS1

MCS2

MCS3

Receiver sensitivity 802.11n HT20

BCC waveform

MCS4

MCS5

MCS6

MCS7

MCS0

MCS1

MCS2

MCS3

Receiver sensitivity 802.11n HT40 BCC

waveform

MCS4

MCS5

MCS6

MCS7

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Table 28.ꢀ5 GHz Wi-Fi receiver performance...continued

Parameter

Conditions

MCS0

Min

--

Typ

-92

-90

-88

-85

-83

-80

-78

-76

-72

-88

-87

-85

-82

-80

-76

-75

-74

-70

-68

-84

-82

-79

-78

-73

-72

-71

-66

-64

-3

Max

--

Unit

dBm

MCS1

MCS2

MCS3

Receiver sensitivity 802.11ac VHT20

BCC waveform

MCS4

MCS5

MCS6

MCS7

MCS8

MCS0

MCS1

MCS2

MCS3

MCS4

Receiver sensitivity 802.11ac VHT40

BCC waveform

MCS5

MCS6

MCS7

MCS8

MCS9

MCS0

MCS1

MCS2

MCS3

MCS4

Receiver sensitivity 802.11ac VHT80

BCC waveform

MCS5

MCS6

MCS7

MCS8

MCS9

802.11a 6-36 Mbit/s

802.11a 48-54 Mbit/s

802.11n MCS0-4

802.11n MCS5

802.11n MCS6

802.11n MCS7-9

-5

-3

Receiver maximum input level

-4

-5

-8

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Table 28.ꢀ5 GHz Wi-Fi receiver performance...continued

Parameter

Conditions

6 Mbit/s

9 Mbit/s

12 Mbit/s

18 Mbit/s

24 Mbit/s

36 Mbit/s

48 Mbit/s

54 Mbit/s

MCS0

Min

--

Typ

34

32

33

32

29

24

17

32

31

26

22

20

17

15

29

28

22

23

19

18

16

Max

--

Unit

dB

Receiver adjacent channel interference

rejection (ACI) 802.11a

MCS1

MCS2

MCS3

Receiver adjacent channel interference

rejection (ACI) 802.11n, HT20

MCS4

MCS5

MCS6

MCS7

MCS0

MCS1

MCS2

MCS3

Receiver adjacent channel interference

rejection (ACI) 802.11n, HT40

MCS4

MCS5

MCS6

MCS7

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9.3.4 2.4 GHz Wi-Fi transmitter performance

Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and at the

chip port.

Table 29.ꢀ2.4 GHz Wi-Fi transmitter performance

Parameter

Conditions

Min

Typ

Max

Unit

RF frequency range

2.4 GHz—IEEE 802.11n/g/b

2400

--

2500

MHz

2.4 GHz—IEEE 802.11ac, bandwidth

20 MHz and bandwidth 40 MHz

Transmitter output saturation

Saturation power at chip output

Carrier suppression at chip output

I/Q suppression at chip output

--

27

-36

-45

--

dBm

dB

Transmit carrier suppression (CW)

Transmit I/Q suppression with IQ

calibration

dBc

802.11b

--

22

21

20

--

dBm

OFDM BPSK

OFDM QPSK

OFDM 16-QAM

OFDM 64-QAM

OFDM BPSK

OFDM QPSK

OFDM 16-QAM

OFDM 64-QAM

Transmit power (EVM and mask

compliant) 20 MHz

Transmit power (EVM and mask

compliant) 40 MHz

Transmit output power level control

range

--

22^[1]

--

dB

Transmit output power control step

Transmit output power accuracy

Transmit carrier suppression

--

1^[2]

1.5

49

--

dB

--

802.11n HT40 MCS7 at 18 dBm

[1] 0-22 dBm

[2] Hardware capability = 0.5 dB, software capability = 1 dB

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9.3.5 5 GHz Wi-Fi transmitter performance

Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and at the

chip port.

Table 30.ꢀ5 GHz Wi-Fi transmitter performance

Parameter

Conditions

Min

4900

—

Typ

--

Max

5925

—

Unit

MHz

dBm

dB

RF frequency range

5 GHz—IEEE 802.11ac/n/a

Saturation power at chip output

Carrier suppression at chip output

I/Q suppression at chip output

Transmit output saturation

Transmit carrier suppression (CW)

27

—

-36

-45

—

Transmit I/Q suppression with IQ

calibration

—

dBc

OFDM BPSK

--

21

20

18

17

15

--

dBm

OFDM QPSK

Transmit power (EVM and mask

compliant) 20 MHz

OFDM 16-QAM

OFDM 64-QAM (MCS7)

OFDM 256-QAM (MCS8)

OFDM BPSK

OFDM QPSK

Transmit power (EVM and mask

compliant) 40 MHz

OFDM 16-QAM

OFDM 64-QAM (MCS7)

OFDM 256-QAM (MCS9)

OFDM BPSK

OFDM QPSK

Transmit power (EVM and mask

compliant) 80 MHz

OFDM 16-QAM

OFDM 64-QAM (MCS7)

OFDM 256-QAM (MCS9)

Transmit output power level control

range

--

21^[1]

--

dB

Transmit output power control step

Transmit output power accuracy

Transmit carrier suppression

--

1^[2]

1.5

51

--

dB

802.11ac MCS9 VHT80, at 15 dBm

dBc

[1] 0-21 dBm

[2] Hardware capability = 0.5 dB, software capability = 1 dB

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9.3.6 Local oscillator

Table 31.ꢀLocal oscillator

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Parameter

Condition

Min

Typ

Max

Units

Phase noise

Measured at 2.438 GHz at 100 kHz

offset

--

-103

--

dBc/Hz

Phase noise

Measured at 5.501 GHz at 100 kHz

offset

—

--

-100

0.3

0.5

—

--

dBc/Hz

degrees

kHz

Integrated RMS phase noise at RF

output (from 1 kHz–10 MHz)

Reference clock frequency = 38.4 MHz

(2.4 GHz)

Integrated RMS phase noise at RF

output (from 10 kHz–10 MHz)

Reference clock frequency = 38.4 MHz

(5 GHz)

—

Frequency resolution

—

0.02

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9.4 Bluetooth radio specifications

The Bluetooth radio interface pin is powered by AVDD18 voltage supply.

9.4.1 Bluetooth and Bluetooth LE receiver performance

Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and at

BRF_ANT pin.

Table 32.ꢀBluetooth and Bluetooth LE receiver performance

Parameter

Conditions

Min

2.4

--

Typ

--

Max

2.5

--

Unit

GHz

MHz

dBm

dB

RF frequency range

IF frequency

--

2

Input IP3 (@ maximum gain of 72 dB)

In-band blocking

--

-19

10

--

GFSK

--

C/I (Co-channel)

C/I (1 MHz)

--

-4

--

dB

C/I (2 MHz)

-45

-49

-21

-32

10

C/I (3 MHz)

C/I (Image)

C/I (Image ±1 MHz)

Pi/4-DQPSK

C/I (Co-channel)

C/I (1 MHz)

--

-9

--

dB

C/I (2 MHz)

-47

-51

-19

-35

16

C/I (3 MHz)

C/I (Image)

C/I (Image ±1 MHz)

8-DPSK

C/I (Co-channel)

C/I (1 MHz)

C/I (2 MHz)

C/I (3 MHz)

C/I (Image)

--

-6

-42

-48

-12

-33

-12.5

-12.4

-18

-2.6

-90

--

dB

--

dB

--

dB

C/I (Image ±1 MHz)

30–2000 MHz

2–2.399 GHz

2.484–3 GHz

3–12.75 GHz

Resolution = 1 dB

--

dB

Out-of-band blocking

--

dBm

dB

--

RSSI range

0

50 Ω return loss

-10

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Table 32.ꢀBluetooth and Bluetooth LE receiver performance...continued

Parameter

Conditions

DH5

Min

--

Typ

Max

--

Unit

dBm

-96^[1]

-95^[2]

-88^[3]

-99^[4]

-96^[4]

Bluetooth sensitivity (RCV/CA/01/C &

RCV/CA/02/C & RCV/CA/07/C)

2DH5

--

3DH5

--

Bluetooth LE 1 Mbit/s

Bluetooth LE 2 Mbit/s

--

Bluetooth LE sensitivity

(RCV-LE/CA/02/C)

--

[1] Desense of ~9.5 dB at CH 2419 MHz, ~6 dB at 2457 MHz, ~9 dB at 2458 MHz due to internal clock harmonics

[2] Desense of ~8.5 dB at CH 2419 MHz, ~3 dB at CH 2432 MHz, ~5 dB at 2457 MHz, ~7.5 dB at 2458 MHz due to internal clock harmonics

[3] Desense of ~9 dB at CH 2419 MHz, ~3.5dB at CH 2432 MHz,~4.5 dB at 2457 MHz, ~7.5 dB at 2458 MHz due to internal clock harmonics

[4] Desense of ~7 dB at CH 2432 MHz and ~9 dB at 2458MHz due to internal clock harmonics

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9.4.2 Bluetooth and Bluetooth LE transmitter performance

Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and at

BRF_ANT pin.

Table 33.ꢀBluetooth and Bluetooth LE transmitter

Parameter

Conditions

--

Min

2.4

--

Typ

--

Max

2.5

Unit

GHz

dB

RF frequency range

Gain range

Class 1 without external PA

--

30

0.5

--

Gain resolution

--

dB

Spurious emission (BDR) (in-band)

±500 kHz

±2 MHz

--

-20

dBc

dBm

dBc

dBm

--

-33

-45

--

-20

±3 MHz

--

-40

Spurious emission (EDR) (in-band)

Spurious emission (out-of-band)

±1 MHz

--

-26

±1.5 MHz

±2.5 MHz

30–88 MHz

88–960 MHz

0.96–20 GHz

--

-20

--

-40

--

-65

-35

-41.25

-25

--

All frequencies in this range < -41.25 dBm,

except at 2x Bluetooth channel frequency.

Measured at pin without external filter.

Restricted—2.38–2.39 GHz

Restricted—2.4835–2.6 GHz

GSM850 (869–894 MHz)

GSM900 (925–960 MHz)

GSM DCS (1805–1880 MHz)

GSM PCS (1930–1990 MHz)

GPS (1575.42 ±1.023 MHz)

WCDMA Band I (2110–2170 MHz)

WCDMA Band V (869–894 MHz)

BDR

--

-55

-50

-41.25

--

Out-of-band/

-140

-135

-140

-130

-140

13

dBm/Hz

Cellular band noise

--

dBm

dB

Transmit output power

(TRM/CA/01/C)

EDR

10

--

Power control (TRM/CA/03/C)

Frequency range (TRM/CA/04/C)

-20dB BW (TRM/CA/05/C)

5

--

Freq Low

2400.9

2481

955

164

100

0.9

--

MHz

kHz

%

Freq High

--

DH5

--

Delta F1 avg

Delta F2 max Threshold

Delta F2/Delta F1

Delta F2 avg

--

Modulation characteristics

(TRM/CA/07/C)

--

Modulation characteristics

(TRM/CA/07/C)

148

--

kHz

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Table 33.ꢀBluetooth and Bluetooth LE transmitter...continued

Parameter

Conditions

Min

--

Typ

19

Max

--

Unit

kHz

dB

ICFT (TRM/CA/08/C)

DH1

Max Drift - DH1

-7

Drift Rate - DH1

-0.9

-7

Max Drift - DH3

Carrier frequency drift

(TRM/CA/09/C)

Drift Rate - DH3

-1

Max Drift - DH5

-7

Drift Rate - DH5

-1.3

-0.1

0.07

0.03

0.08

0.03

100

10

2DH5 (DPSK/GFSK)

3DH5 (DPSK/GFSK)

2DH5 Peak DEVM

EDR relative power (TRM/CA/10/C)

dB

--

2DH5 RMS DEVM

--

EDR carrier frequency stability and

modulation accuracy (TRM/CA/11/C)

3DH5 Peak DEVM

--

3DH5 RMS DEVM

--

2DH5

%

Diff. phase encoding (TRM/CA/12/C)

3DH5

%

Bluetooth LE 1 Mbit/s

Bluetooth LE 2 Mbit/s

Delta F1 avg - Bluetooth LE 1 Mbit/s

Delta F2/Delta F1- Bluetooth LE 1 Mbit/s

Delta F2 avg - Bluetooth LE 1 Mbit/s

Delta F1 avg - Bluetooth LE 2 Mbit/s

Delta F2/Delta F1- 2 Mbit/s

Delta F2 avg- Bluetooth LE 2 Mbit/s

Max Drift - Bluetooth LE 1 Mbit/s

Drift Rate - Bluetooth LE 1 Mbit/s

Max Drift - Bluetooth LE 2 Mbit/s

Drift Rate - Bluetooth LE 2 Mbit/s

Bluetooth LE 1 Mbit/s

Bluetooth LE 2 Mbit/s

dBm

kHz

Bluetooth LE output power

(TRM/-Bluetooth LE/CA/01/C)

10

247

0.9

223

504

1

Bluetooth LE modulation

characteristics

(TRM-Bluetooth LE/CA/05/C)

474

0.5

1.5

-1.5

1

Bluetooth LE carrier frequency drift

(TRM-Bluetooth LE/CA/06/C)

-9

Frequency accuracy

(TRM-LE/CA/BV-06-C)

-10

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9.5 Current consumption

Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, across

frequency and typical value. Data is collected with SDIO-SDIO interface configuration.

The power consumption in transmit mode refers to the device port pin

Table 34.ꢀCurrent consumption

Mode

2.2V

1.8V

1.1V

Unit

Sleep mode current consumption

Power down

0

0.04

0.02

2.8

mA

Wi-Fi and Bluetooth in deep- sleep mode

Wi-Fi only in deep-sleep mode

1.01

1.04

1.14

1.22

0.025

0.024

0.02

Bluetooth only in deep-sleep mode

Bluetooth LE only in deep-sleep mode

Bluetooth LE current consumption^[1]

Bluetooth LE advertise (interval = 1.28s)

Bluetooth LE scan (interval = 1.28s, window = 11.25 ms)

Bluetooth LE link (master mode, interval=1.28s)

Bluetooth LE peak transmit (at 0 dBm), 1 Mbit/s

Bluetooth LE peak transmit (at 5 dBm), 1 Mbit/s

Bluetooth LE peak transmit (at 10 dBm), 1 Mbit/s

Bluetooth LE peak receive, 1 Mbit/s

Bluetooth current consumption^[1]

Bluetooth page scan

0

0.05

0.15

0.07

25

1.1

1.2

21

mA

37

23

53

22

17

21

0

0.18

0.32

0.09

0.18

11.7

17.2

19.3

25

1.2

1.33

1.3

1.7

18

mA

Bluetooth page and inquiry scan

Bluetooth ACL link, master sniff mode, (interval = 1.28s)

Bluetooth ACL link, master sniff mode, (interval = 500 ms)

Bluetooth ACL (data pump) DH1

Bluetooth ACL (data pump) 2-DH3

19.5

20

Bluetooth ACL (data pump) 3-DH5

Bluetooth SCO HV3 peak transmit (at 0 dBm)

Bluetooth SCO HV3 peak transmit (at 5 dBm)

Bluetooth SCO HV3 peak transmit (at 10 dBm)

Bluetooth SCO HV3 peak transmit (at 13 dBm)

Bluetooth SCO HV3 Peak Receive

21

37

23

53

22

67

22

17

21

Bluetooth Peak Transmit (at 0 dBm), DH5

Bluetooth Peak Transmit (at 5 dBm), DH5

Bluetooth Peak Transmit (at 10 dBm), DH5

Bluetooth Peak Transmit (at 13 dBm), DH5

Bluetooth Peak Receive, DH5

25

21

37

23

53

22

67

22

17

21

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Table 34.ꢀCurrent consumption...continued

Mode

2.2V

1.8V

1.1V

Unit

IEEE power save mode^[2]

IEEE-PS_2GHz-Legacy (DTIM-1)

IEEE-PS_2GHz-Legacy (DTIM-3)

IEEE-PS_2GHz-Legacy (DTIM-5)

IEEE-PS_2GHz-Legacy (DTIM-10)

IEEE-PS_5GHz-Legacy (DTIM-1)

IEEE-PS_5GHz-Legacy (DTIM-3)

IEEE-PS_5GHz-Legacy (DTIM-5)

IEEE-PS_5GHz-Legacy (DTIM-10)

2.4 GHz Wi-Fi receive mode^[3]

802.11b, 11 Mbit/s

0

1

3.18

1.88

1.7

mA

0.35

0.2

0.14

0.7

1.27

2.33

1.6

0.25

0.15

0.12

1.43

1.32

0

40

38

95

mA

802.11g, 54 Mbit/s

112

118

802.11n, HT20 MCS7

5 GHz Wi-Fi 5 receive mode^[3]

802.11a, 54 Mbit/s

0

54

55

65

55

65

70

118

120

140

120

140

158

mA

802.11n, HT20 MCS7

802.11n, HT40 MCS7

802.11ac, VHT20 MCS8

802.11ac, VHT40 MCS9

802.11ac, VHT80 MCS9

2.4 GHz Wi-Fi transmit mode^[3]

802.11b, 11 Mbit/s at 20 dBm

802.11g, 54 Mbit/s at 20 dBm

802.11n, HT20 MCS0 at 20 dBm

802.11n, HT20 MCS7 at 20 dBm

5 GHz Wi-Fi transmit mode^[3]

802.11a, 6 Mbit/s at 19 dBm

802.11a, 54 Mbit/s at 19 dBm

802.11n, HT20 MCS0 at 19 dBm

802.11n, HT20 MCS7 at 19 dBm

802.11n, HT40 MCS0 at 17 dBm

802.11n, HT40 MCS7 at 17 dBm

802.11ac, VHT20 MCS0 at 19 dBm

802.11ac, VHT20 MCS8 at 19 dBm

802.11ac, VHT40 MCS0 at 17 dBm

802.11ac, VHT40 MCS9 at 17 dBm

400

377

382

80

79

80

221

220

238

mA

285

290

230

290

230

141

145

138

144

138

215

220

238

239

235

238

mA

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Table 34.ꢀCurrent consumption...continued

Mode

2.2V

190

1.8V

132

1.1V

232

Unit

mA

802.11ac, VHT80 MCS0 at 15 dBm

802.11ac, VHT80 MCS9 at 15 dBm

Peak current consumption during device initialization

Maximum peak current consumption during device initialization

975

198

mA

[1] Wi-Fi core in sleep mode

[2] Beacon interval = 100 ms. Bluetooth not enabled

[3] Bluetooth in deep-sleep mode

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9.6 SDIO host interface specifications

The SDIO host interface pins are powered by VIO_SD voltage supply.

The SDIO electrical specifications are identical for the 4-bit SDIO and 1-bit SDIO modes.

9.6.1 VIO_SD DC characteristics

9.6.1.1 1.8V operation

Table 35.ꢀDC electrical characteristics—1.8V operation (VIO_SD)

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

V_IH

Parameter

Input high voltage

Input low voltage

Input hysteresis

Condition

Min

0.7*VIO_SD

-0.4

Typ

--

Max

Unit

V

--

VIO_SD+0.4

V_IL

--

0.3*VIO_SD

V

V_HYS

V_OH

V_OL

100

--

mV

V

Output high voltage

Output low voltage

VIO_SD-0.4

--

0.4

V

9.6.2 Default speed, high-speed modes

f

PP

T

WH

WL

Clock

Input

T

IH

ISU

T

ODLY

Output

aaa-036116

Figure 13.ꢀSDIO protocol timing diagram—Default speed mode

f

PP

T

WH

WL

Clock

Input

T

IH

ISU

T

OH

ODLY

Output

aaa-036119

Figure 14.ꢀSDIO protocol timing diagram—High-speed mode

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Table 36.ꢀSDIO timing data—Default Speed, High-Speed Modes

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

Parameter

Condition

Normal

Min

0

Typ

--

Max

25

50

--

Unit

MHz

ns

f_PP

Clock frequency

High-speed

Normal

0

--

T_WL

T_WH

T_ISU

T_IH

Clock low time

Clock high time

Input setup time

Input hold time

10

7

--

High-speed

Normal

--

ns

10

7

--

ns

High-speed

Normal

--

ns

5

--

ns

High-speed

Normal

6

--

ns

5

--

ns

High-speed

Normal

2

--

ns

T_ODLY

Output delay time

CL ≤ 40 pF (1 card)

Output hold time

--

14

--

ns

High-speed

--

ns

T_OH

2.5

--

ns

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9.6.3 SDR12, SDR25, SDR50 modes (up to 100 MHz) (1.8V)

T

CLK

f

PP

Clock

Input

T

CR

T

CF

T

IH

IS

T

ODLY

T

OH

Output

aaa-036120

Figure 15.ꢀSDIO protocol timing diagram—SDR12, SDR25, SDR50 Modes (up to 100 MHz) (1.8V)

Table 37.ꢀSDIO timing data——SDR12, SDR25, SDR50 Modes (up to 100 MHz) (1.8V)

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

f_PP

Parameter

Condition

Min

25

3

Typ

--

Max

Units

MHz

ns

Clock frequency

Input setup time

Input hold time

Clock time

SDR12/25/50

100

T_IS

--

T_IH

0.8

10

--

ns

T_CLK

T_CR, T_CF

--

40

ns

Rise time, fall time

--

0.2*T_CLK

ns

T_CR, T_CF< 2 ns (max) at

100 MHz

C_CARD= 10 pF

T_ODLY

Output delay time

C_L≤ 30 pF

SDR12/25/50

--

7.5

--

ns

T_OH

Output hold time

C_L= 15 pF

1.5

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9.6.4 SDR104 mode (208 MHz) (1.8V)

T

CLK

f

PP

Clock

Input

T

CR

T

CF

T

IH

IS

T

OP

T

ODW

Output

aaa-036121

Figure 16.ꢀSDIO protocol timing diagram—SDR104 mode (208 MHz)

Table 38.ꢀSDIO timing data—SDR104 mode (208 MHz)

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

f_PP

Parameter

Condition

SDR104

Min

0

Typ

--

Max

Unit

MHz

ns

Clock frequency

Input setup time

Input hold time

Clock time

208

T_IS

1.4

0.8

4.8

--

T_IH

--

ns

T_CLK

T_CR, T_CF

--

ns

Rise time, fall time

--

0.2*T_CLK

ns

T_CR, T_CF< 0.96 ns (max) at

208 MHz

C_CARD= 10 pF

T_OP

Card output phase

SDR104

0

--

10

--

ns

T_ODW

Output timing of variable

data window

2.88

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9.6.5 DDR50 mode (50 MHz) (1.8V)

T

CLK

Clock

T

CF

T

IS

T

IH

CR

CMD Input

T

OHLD

ODLY

CMD Output

aaa-036117

Figure 17.ꢀSDIO CMD timing diagram—DDR50 mode (50 MHz)

T

CLK

Clock

T

IH2x

T

IS2x

DAT[3:0]

Input

T

ODLY2x(max)

T

ODLY2x(max)

DAT[3:0]

Output

T

ODLY2x(min)

aaa-036118

Figure 18.ꢀSDIO DAT[3:0] timing diagram—DDR50 mode^[1](50 MHz)

[1] In DDR50 mode, DAT[3:0] lines are sampled on both edges of the clock (not applicable for CMD line).

Table 39.ꢀSDIO timing data—DDR50 mode (50 MHz)

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

Clock

T_CLK

Parameter

Condition

Min

Typ

Max

Units

Clock time

DDR50

20

--

ns

50 MHz (max) between

rising edges

T_CR, T_CF

Rise time, fall time

DDR50

--

0.2*T_CLK

ns

T_CR, T_CF< 4.00 ns (max) at

50 MHz

C_CARD= 10 pF

Clock Duty

--

DDR50

45

6

--

55

--

%

CMD Input (referenced to clock rising edge)

T_IS

Input setup time

DDR50

ns

C_CARD≤ 10 pF (1 card)

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Table 39.ꢀSDIO timing data—DDR50 mode (50 MHz)...continued

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

Parameter

Condition

Min

Typ

Max

Units

T_IH

Input hold time

DDR50

0.8

--

ns

C_CARD≤ 10 pF (1 card)

CMD Output (referenced to clock rising edge)

T_ODLY

Output delay time during

data transfer mode

DDR50

--

13.7

--

ns

C_L≤ 30 pF (1 card)

T_OHLD

Output hold time

DDR50

1.5

C_L≥ 15 pF (1 card)

DAT[3:0] Input (referenced to clock rising and falling edges)

T_IS2x

Input setup time

DDR50

3

--

ns

C_CARD≤ 10 pF (1 card)

T_IH2x

Input hold time

DDR50

0.8

C_CARD≤ 10 pF (1 card)

DAT[3:0] Output (referenced to clock rising and falling edges)

T_{ODLY2x (max)}Output delay time during

data transfer mode

DDR50

--

7.0

--

ns

C_L≤ 25 pF (1 card)

T_{ODLY2x (min)}

Output hold time

DDR50

1.5

C_L≥ 15 pF (1 card)

9.6.6 SDIO internal pull-up/pull-down specifications

Table 40.ꢀSDIO internal pull-up/pull-down specifications

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Parameter

Condition

Min

Typ

Max

120

Unit

Internal nominal pull-up/pull-down --

resistance

60

90

kΩ

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9.7 High-speed UART specifications

The UART Tx and Rx pins are powered by VIO voltage supply.

See Section 9.1.1 "VIO DC characteristics" for DC specifications.

T

BAUD

UART Tx

UART Rx

aaa-036128

Figure 19.ꢀUART timing diagram

Table 41.ꢀUART timing data^[1]

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

Parameter

Condition

Min

Typ

Max

--

Unit

T_BAUD

Baud rate

38.4 MHz input clock

250

--

ns

[1] The acceptable deviation from the UART Rx target baud rate is ±3%.

9.8 Audio interface specifications

9.8.1 PCM interface specifications

The PCM pins are powered by VIO voltage supply. See Section 9.1.1 "VIO DC

characteristics" for specifications.

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Master Mode

T_BCLK

PCM_CLK

T_DO

PCM_DOUT

T_DISU

T_DIHO

PCM_DIN

Figure 20.ꢀPCM timing specification diagram for data signals—Master mode

T_BCLK

PCM_CLK

T_BF

PCM_SYNC

Figure 21.ꢀPCM timing specification diagram for PCM_SYNC signal—Master mode

Table 42.ꢀPCM timing specification data—Master mode

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

Parameter

Condition

Min

--

Typ

2/2.048

0.5

Max

--

Unit

MHz

--

F_BCLK

Bit clock frequency

--

Duty Cycle_BCLKBit clock duty cycle

0.4

--

0.6

--

T_{BCLK rise/fall}

T_DO

PCM_CLK rise/fall time

3

ns

Delay from PCM_CLK rising edge to

PCM_DOUT rising edge

--

15

ns

T_DISU

T_DIHO

T_BF

Setup time for PCM_DIN before PCM_ --

CLK falling edge

20

15

--

ns

Hold time for PCM_DIN after PCM_CLK --

falling edge

Delay from PCM_CLK rising edge to

PCM_SYNC rising edge

--

15

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Slave mode

T_BCLK

PCM_CLK

T_DO

PCM_DOUT

T_DISU

T_DIHO

PCM_DIN

Figure 22.ꢀPCM timing specification diagram for data signals—Slave mode

T_BCLK

PCM_CLK

T_BFSU

T_BFHO

T_BF

PCM_SYNC

Figure 23.ꢀPCM timing specification diagram for PCM_SYNC signal—Slave mode

Table 43.ꢀPCM timing specification data—Slave mode

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

Parameter

Condition

Min

--

Typ

2/2.048

0.5

Max

--

Unit

MHz

--

F_BCLK

Bit clock frequency

--

Duty Cycle_BCLKBit clock duty cycle

0.4

--

0.6

--

T_{BCLK rise/fall}

T_DO

PCM_CLK rise/fall time

3

ns

Delay from PCM_CLK rising edge to

PCM_DOUT rising edge

--

30

ns

T_DISU

T_DIHO

T_BFSU

T_BFHO

Setup time for PCM_DIN before PCM_ --

CLK falling edge

15

10

15

10

--

ns

Hold time for PCM_DIN after PCM_CLK --

falling edge

Setup time for PCM_SYNC before

PCM_CLK falling edge

--

Hold time for PCM_SYNC after PCM_

CLK falling edge

--

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9.9 Reference clock specifications

9.9.1 External crystal oscillator specifications

The reference clock from the external crystal oscillator requires a CMOS input signal.

Note: All new designs should use the 38.4 MHz reference clock. For existing designs

the 26 MHz reference clock can still be used.

Table 44.ꢀClock DC specifications^[1]

Parameter

Condition

Min

--

Typ

--

Max

1.8

--

Unit

V

Single-ended high-level voltage

Single-ended low-level voltage

Clock amplitude (pk-pk)

Mid-point slope

--

0

--

V

0.5

125

--

1

V

--

MV/s

[1] The AC-coupling capacitor is integrated into the SoC.

Table 45.ꢀ26 MHz clock timing

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Parameter

Condition

Min

Typ

Max

Unit

XO26 period

--

38.46 -

20 ppm

38.46

38.46 +

20 ppm

ns

XO26 rise time

XO26 fall time

XO26 duty cycle

--

5.00

ns

%

48.05

50

51.95

Table 46.ꢀ38.4 MHz clock timing

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Parameter

Condition

Min

Typ

Max

Unit

XO38_4 period

--

26.04 -

20 ppm

26.04

26.04 +

20 ppm

ns

XO38_4 rise time

XO38_4 fall time

XO38_4 duty cycle

--

2.50

ns

%

47.12

50

52.88

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Table 47.ꢀPhase Noise—2.4 GHz operation

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Parameter

Test Conditions

Offset = 1 kHz

Offset = 10 kHz

Offset = 100 kHz

Offset > 1 MHz

Offset = 1 kHz

Offset = 10 kHz

Offset = 100 kHz

Offset > 1 MHz

Min

--

Typ

--

Max

-126

-137

-145

-123

-134

-142

Unit

Fref = 26 MHz

dBc/Hz

--

Fref = 38.4 MHz

--

Table 48.ꢀPhase Noise—5 GHz operation

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Parameter

Test Conditions

Offset = 1 kHz

Offset = 10 kHz

Offset = 100 kHz

Offset > 1 MHz

Offset = 1 kHz

Offset = 10 kHz

Offset = 100 kHz

Offset > 1 MHz

Min

--

Typ

--

Max

-130

-150

-156

-126

-146

-154

Unit

Fref = 26 MHz

dBc/Hz

--

Fref = 38.4 MHz

--

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9.9.2 External crystal specifications

Note: All new designs should use the 38.4 MHz reference clock. For existing designs

the 26 MHz reference clock can still be used.

Table 49.ꢀExternal crystal specifications

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Parameter

Condition

Min

--

Typ

Max

--

Unit

MHz

--

Fundamental frequencies

Resonance mode

--

26 or 38.4

--

A1,

--

Fundamental

Equivalent differential load

capacitance

--

5

--

pF

Shunt capacitance

Frequency tolerance

Frequency stability

Aging

--

2

--

pF

Over process at 25ºC

±10

±2

ppm

Over operating temperature

--

ppm/

5 years

Series resistance (ESR)

38.4 MHz

26 MHz

at DC 100V

--

60

--

Ω

--

Insulation resistance

Drive level

500

150

MΩ

µW

--

9.9.3 External sleep clock specifications

Table 50.ꢀExternal sleep clock specifications^[1]

Parameter

Min

Typ

Max

Units

Clock frequency range/accuracy

• CMOS input clock signal type

• ±250 ppm (initial, aging, temperature)

--

32.768

--

kHz

Phase noise requirement (@ 100 kHz)

Cycle jitter

--

-125

1.5

--

dBc/Hz

ns (RMS)

ns

Slew rate limit (10-90%)

Duty cycle tolerance

--

100

80

20

--

%

[1] Voltage input levels = 1.8V or 3.3V. See Section 8 "Recommended operating conditions".

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9.10 Power-down (PDn) pin specifications

9.10.1 PDn asserted low—All power supplies good

Figure 24 and Table 51 show the specifications for the PDn signal when it is asserted

(low) while all power supplies to the device are good.

Power

PDn

T

RPW

T

PU_RESET

aaa-036126

Figure 24.ꢀPower-down (PDn) pin timing—The power remains high at PDn assertion

Table 51.ꢀPower-down (PDn) pin specifications—The power remains high at PDn assertion

Unless otherwise specified, the values apply per the Recommended operating conditions

Symbol

Parameter

Condition

Min

Typ

Max

Unit

T_{PU_RESET}

Valid power to PDn de-

asserted

--

0

--

ms

T_RPW

V_IH

PDn pulse width

Input high voltage

Input low voltage

--

1^[1]

1.4

--

µs

V

4.5

0.5

V_IL

-0.4

V

[1] Minimum value guaranteed for a valid reset. Smaller values may put the device in an undefined state.

9.10.2 PDn asserted Low—One or more power supplies ramp down

Figure 25 and Table 52 show the specifications for the PDn signal when it is asserted

(low) while 1 or more of the power supplies (including VCORE) ramps down.

Power

0.2 V

T

RD

PDn

T

PU_RESET

RPW

T

= time from PDn assertion until power supply drops to 0.2 V

aaa-036125

RD

Figure 25.ꢀPower-down (PDn) pin timing—Power ramps down at PDn assertion

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Table 52.ꢀPower-down (PDn) pin secifications—Power ramps down at PDn assertion

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

Parameter

Condition

Min

Typ

Max

Unit

T_{PU_RESET}

Valid power to PDn de-

asserted

--

0

—

ms

[1]

T_RPW

V_IH

PDn pulse width

Input high voltage

Input low voltage

--

T_RD

—

µs

V

1.4

4.5

0.2

V_IL

-0.4

V

[1] Minimum value guaranteed for a valid reset. Smaller values may put the device in an undefined state.

9.11 Configuration pin specifications

For a list of configuration pins, see Section 5.6 "Configuration pins".

Table 53.ꢀConfiguration pin specifications^[1]

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Parameter

Condition

Min

—

Typ

800

100

Max

Unit

Internal weak pull-up resistance

Around 1 ms following any reset

—

kΩ

Internal nominal pull-up resistance Around 1 ms following any reset

—

[1] After approximately 1 ms, the configuration pins become functional pins.

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9.12 JTAG interface specifications

The test interface pins are powered by VIO voltage supply.

See Section 9.1.1 "VIO DC characteristics" for specifications.

T

P_TCK

T

H_TCK

L_TCK

JTAG_TCK

T

HD_TDI

SU_TDI

JTAG_TDI

JTAG_TMS

T

DLY_TDO

JTAG_TDO

aaa-036123

Figure 26.ꢀJTAG timing diagram

Table 54.ꢀJTAG timing data^[1]

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

T_{P_TCK}

T_{H_TCK}

T_{L_TCK}

Parameter

TCK period

TCK high

TCK low

Condition

Min

40

12

10

0

Typ

--

Max

--

Unit

ns

--

ns

--

ns

T_{SU_TDI}

T_{HD_TDI}

T_{DLY_TDO}

TDI, TMS to TCK setup time --

TDI, TMS to TCK hold time --

--

ns

--

ns

TCK to TDO delay

--

15

ns

[1] Does not apply to JTAG enabled by the JTAG_TMS pin.

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10 Package information

10.1 Package thermal conditions

10.1.1 68-pin QFN thermal conditions

Table 55.ꢀThermal conditions—QFN package

Symbol Parameter

Condition

Typ

Unit

θ_JA

Thermal resistance

24 x 30 x 1.05 mm

6-layer PCB

43.00

°C/W

Junction to ambient of package.

θ_JA= (T_J- T_A)/ P

no air flow

P = total power dissipation

24 x 30 x 1.05 mm

6-layer PCB

36.90

32.50

30.30

4.10

°C/W

1 meter/sec air flow

24 x 30 x 1.05 mm

6-layer PCB

2 meter/sec air flow

24 x 30 x 1.05 mm

6-layer PCB

3 meter/sec air flow

ψ_JT

ψ_JB

θ_JC

Thermal characteristic parameter

Junction to top-center of package.

ψ_JT= (T_J- T_TOP)/P

24 x 30 x 1.05 mm

6-layer PCB

no air flow

T_TOP= temperature on top-center of

package

Thermal characteristic parameter

24 x 30 x 1.05 mm

6-layer PCB

13.80

°C/W

Junction to bottom surface, center of

package.

no air flow

ψ_JB= (T_J- T_B)/P

T_B= surface temperature of package

Thermal resistance

24 x 30 x 1.05 mm

6-layer PCB

Junction to case of the package.

θ_JC= (T_J- T_C)/ P_TOP

no air flow

T_C= temperature on top-center of

package

P_TOP= power dissipation from top of

package

θ_JB

Thermal resistance

24 x 30 x 1.05 mm

6-layer PCB

14.10

°C/W

Junction to board of package.

θ_JB= (T_J- T_B)/ P_BOTTOM

no air flow

P_BOTTOM= power dissipation from bottom

of package to PCB surface

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10.1.2 83-bump eWLP thermal conditions

Table 56.ꢀThermal conditions—eWLP package

Symbol Parameter

Condition

Typ

Unit

θ_JA

Thermal resistance

JEDEC 4 in. x 4.5 in.

4-layer PCB with 41 thermal via

no air flow

28.07

°C/W

Junction to ambient of package.

θ_JA= (T_J- T_A)/ P

P = total power dissipation

JEDEC 4 in. x 4.5 in.

4-layer PCB with no thermal via

no air flow

41.96

0.08

°C/W

ψ_JT

Thermal characteristic parameter

Junction to top-center of package.

ψ_JT= (T_J- T_TOP)/P

JEDEC 4 in. x 4.5 in.

4-layer PCB with no thermal via

no air flow

T_TOP= temperature on top-center of

package

ψ_JB

Thermal characteristic parameter

JEDEC 4 in. x 4.5 in.

4-layer PCB with no thermal via

no air flow

15.30

°C/W

Junction to bottom surface, center of

package.

ψ_JB= (T_J- T_B)/P

T_B= surface temperature of package

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10.2 Package mechanical drawing

10.2.1 68-pin QFN mechanical drawing

Figure 27.ꢀ68-pin QFN mechanical drawing

Note: See also Section 10.1.1 "68-pin QFN thermal conditions" and Section 10.3.1 "68-

pin QFN package marking".

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10.2.2 83-bump eWLP mechanical drawing

Figure 28.ꢀ83-bump eWLP mechanical drawing

• Dimensions in mm. Also refer to Section 10.1.2 "83-bump eWLP thermal conditions"

and Section 10.3.2 "83-bump eWLP package marking".

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10.3 Package marking

10.3.1 68-pin QFN package marking

Part number, package code, environmental code

xxx = package code

2 = environmental code

88W8987-xxx2

Lot number

YYWW xx#

Country of origin

Date code, die revision, assembly plant

YYWW = date code

(YY = year, WW = work week)

xx = die revision

Country of origin

(contained in the mold ID or

marked as the last line on the

package)

E

# = assembly plant code

Temperature code

E = extended

Pin 1 location

I = Industrial

Note: The above drawing is not drawn to scale. The location of markings is approximate.

Figure 29.ꢀ68-pin QFN package marking and pin 1 location

10.3.2 83-bump eWLP package marking

Part number, package code, environmental code

EAH = package code

2 = environmental code

W8987EAH2

Lot Number

YYWW xx#

Country of Origin

Date code, die revision, assembly plant

YYWW = date code

(YY = year, WW = work week)

xx = die revision

Country of origin

(contained in the mold ID or

marked as the last line on the

package)

# = assembly plant code

Pin 1 location

Note: The above drawing is not drawn to scale. The location of markings is approximate.

Figure 30.ꢀeWLP package marking and pin 1 location

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11 Acronyms and abbreviations

Table 57.ꢀAcronyms and abbreviations

Acronym

A2DP

ABR

ACK

ADAS

ADC

AES

AFC

AFH

AGC

AIFS

AoA

Definition

Advanced Audio Distribution Profiles

Automatic Baud Rate

Acknowledgment

Advanced Driver Assistance Systems

Analog-to-Digital Converter

Advanced Encryption Standard

Automatic Frequency Correction

Adaptive Frequency Hopping

Automatic Gain Control

Arbitration Interframe Space

Angle of Arrival

AoD

Angle of Departure

AP

Access Point

APB

API

Advanced Peripheral Bus

Application Program Interface

Advanced Quad Flat Non-leaded Package

Advanced RISC Machine

Announcement Traffic Indication Message

Base Address Mask Register

Base Address Register

Baseband Processor Unit

Benzocyclobutene (flip chip bump process)

Basic Data Rate

aQFN

ARM

ATIM

BAMR

BAR

BBU

BCB

BDR

BER

BOM

BR

Bit Error Rate

Bill of Materials

Baud Rate

BSS

BSSID

BTM

BTU

BRF

BWQ

CBC

CBP

Basic Service Set

Basic Service Set Identifier

BSS Transition Management

Bluetooth Baseband Unit

Bluetooth RF Unit

Bandwidth Queue

Cipher Block Chaining

Contention-Based Period

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Table 57.ꢀAcronyms and abbreviations...continued

Acronym

Definition

CCA

Clear Channel Assessment

Complementary Code Keying

Counter Mode CBC-MAC Protocol

Close Descriptor Enable

CCK

CCMP

CDE

CFP

Contention-Free Period

CFQ

Contention-Free Queue

CID

Connection Identifier

CIS

Card Information Structure

CPU Interface Unit

CIU

CMD

CMQ

CRC

CS

Command

Control Management Queue

Cyclic Redundancy Check

Card Select

CSL

Coordinated Sampled Listening

Carrier Sense Multiple Access / Collision Avoidance

Carrier Sense Multiple Access / Collision Detection

Clocked Serial Unit

CSMA/CA

CSMA/CD

CSU

CTS

Clear to Send

DAC

Digital-to-Analog Converter

Differential Binary Phase Shift Keying

Device Controller Driver

DBPSK

DCD

DCE

Data Communication Equipment

Distributed Coordination Function

Direct Current Level Adjustment

Digital Contactless Bridge

DMA Controller Unit

DCF

DCLA

DCLB

DCU

DFS

Dynamic Frequency Selection

Distributed Interframe Space

Direct Memory Access

DIFS

DMA

dQH

Device Queue Head

DQPSK

DSM

DSP

Differential Quadrature Phase Shift Keying

Distribution System Medium

Digital Signal Processor

DSRC

dTD

Dedicated Short Range Communications

Linked List Transfer Descriptors

Delivery Traffic Indication Message

DTIM

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Table 57.ꢀAcronyms and abbreviations...continued

Acronym

Definition

DUP

DVSC

EAP

Duplicated packet

Digital Voltage Scaling Control

Extensible Authentication Protocol

Extended Block Random Access Memory

Energy Detect

EBRAM

ED

EDCA

EEPROM

EIFS

EMC

ERP-OFDM

ETSI

eWLP

FAE

Enhanced Distributed Channel Access

Electrically Erasable Programmable Read Only Memory

Extended Interframe Space

Electromagnetic Compatibility

Extended Rate PHY-Orthogonal Frequency Division Multiplexing

European Telecommunications Standards Institute

Embedded Wafer Level Package

Field Application Engineer

Federal Communications Commission

First In First Out

FCC

FIFO

FIPS

FIQ

Federal Information Processing Standards

Fast Interrupt Request

FW

Firmware

GATT

GCMP

GI

Generic Attribute Profile

Galois/Counter Mode Protocol

Guard Interval

GPIO

GPL

General Purpose Input/Output

General Public License

GPU

HID

General Purpose Input/Output Unit

Human Interface Device

HIU

Host Interface Unit

HOGP

HSP

HT

HID Over GATT Profile

Hands-Free Profile

High Throughput

HW

Hardware

I/Q

Inphase/Quadrature

IB

InBand

IBSS

ICE

Independent Basic Service Set

In-Circuit Emulator (or Emulation)

Interrupt Cause Register

ICR

ICU

Interrupt Controller Unit

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Table 57.ꢀAcronyms and abbreviations...continued

Acronym

Definition

ICV

Integrity Check Value

IE

Information Element

IEEE

IEMR

I/F

Institute of Electrical and Electronics Engineers

Interrupt Event Mask Register

Interface

IFS

Interframe Space

IMR

IPG

Interrupt Mask Register

Inter-Packet Gap

IPsec

IR

Internet Protocol Security

Infrared

IRQ

ISA

Interrupt Request

Instruction Set Architecture

Integrated Services Digital Network

Industrial, Scientific, and Medical

Interrupt Status Mask Register

Interrupt Status Register

Joint Electronic Device Engineering Council

Joint Test Action Group

Low Density Parity Check

Low Energy

ISDN

ISM

ISMR

ISR

JEDEC

JTAG

LDPC

LE

LED

LME

LNA

LPM

LQFN

LSb

LSB

LSP

LTE

Light Emitting Diode

Layer Management Entity

Low Noise Amplifier

Low Power Management

Low Quad Flat Non-leaded

Least Significant bit

Least Significant Byte

Low-Speed Peripheral

Long Term Evolution

MAC

MC

Media/Medium Access Controller

Memory Controller

MCS

MCU

MDI

MIB

MIC

Modulation and Coding Scheme

MAC Control Unit

Modem Data Interface

Management Information Base

Message Integrity Code

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Table 57.ꢀAcronyms and abbreviations...continued

Acronym

Definition

MII

Media Independent Interface

Multiple Input Multiple Output

Million Instructions Per Second

MAC Sublayer Management Entity

Modem Management Interface

MAC Management Protocol Data Unit

Memory Management Unit

MAC Protocol Data Unit

Most Significant bit

MIMO

MIPS

MLME

MMI

MMPDU

MMU

MPDU

MSb

MSB

Most Significant Byte

MSDU

MU-MIMO

MU-PPDU

MWS

MAC Service Data Unit

Multi-User MIMO

Multi-User PPDU

Mobile Wireless System

Multimedia Wireless System

NAV

NBS

NDP

NL

Network Allocation Vector

Narrow band speech

Null Data Packet

No Load

NPTR

Nsts

OCB

OFDM

OID

Next Descriptor Pointer

Number of space time streams

Outside the Context of a BSS

Orthogonal Frequency Division Multiplexing

Object Identifier

OOB

OTP

P2P

PA

Out of Band

One Time Programmable

Peer-to-Peer

Power Amplifier

PAD

PBU

PC

Packet Assembler/Disassembler

Peripheral Bus Unit

Point Coordinator

PCB

PCF

PCI

Printed Circuit Board

Point Coordination Function

Peripheral Component Interconnect

PCI Express

PCIe

PCM

Pulse Code Modulation

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Table 57.ꢀAcronyms and abbreviations...continued

Acronym

Definition

PDn

PDU

PEAP

PHY

PIFS

PLL

Power Down

Protocol Data Unit

Protected EAP

Physical Layer

Priority Interframe Space

Phase-Locked Loop

Physical Layer Management Entity

Power Management Unit

Power-On Self Test

PLME

PMU

POST

PPDU

PPK

PPM

PSK

PTA

PHY Protocol Data Unit

Per-Packet Key

Pulse Position Modulation

Pre-Shared Keys

Packet Traffic Arbitration

Pairwise Key

PWK

QAM

QFN

QoS

RA

Quadrature Amplitude Modulation

Quad Flat Non-leaded Package

Quality of Service

Receiver Address

RBDS

RDS

RF

Radio Broadcast Data System

Radio Data System

Radio Frequency

RFID

RIFS

RISC

ROM

RSSI

RTS

RTU

RU

Radio Frequency Identification

Reduced Interframe Space

Reduced Instruction Set Computer

Read Only Memory

Receiver Signal Strength Indication

Request to Send

General Purpose Timer Unit

Resource Unit

SA

Source Address

SAP

SCLK

SDA

SE

Service Access Point

Serial Interface Clock

Serial Interface Data

Secure Element

SFD

Start of Frame Delimiter

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NXP Semiconductors

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

Table 57.ꢀAcronyms and abbreviations...continued

Acronym

Definition

SIFS

SISO

SIU

Short Interframe Space

Single Input Single Output

Serial Interface Unit (UART)

System/Software JTAG Controller Unit

Switch Module

SJU

SM

SMI

Serial Management Interface

Signal-to-Noise Ratio

SNR

SO

Serial Out

SoC

SPDT

SPI

System-on-Chip

Single Pole Double Throw

Serial Peripheral Interface

Internal SRAM Unit

SQU

SRWB

SS

Serial Interface Read Write

Service Set

SSID

STA

Service Set Identifier

Station

STBC

SWD

SWP

TA

Space-Time Block Code

Serial Wire Debug

Single Wire Protocol

Transmitter Address

TBG

TBTT

TCM

TCP/IP

TCQ

TIM

Time Base Generator

Target Beacon Transmission Time

Tightly Coupled Memory

Transmission Control Protocol/Internet Protocol

Traffic Category Queue

Traffic Indication Map

TKIP

TPC

TQFP

TRPC

TSC

TSF

Temporal Key Integrity Protocol

Transmit Power Control

Thin Quad Flat Pack

Transmit Rate-based Power Control

TKIP Sequence Counter

Timing Synchronization Function

Target Wait Time

TWT

UART

UBM

UDP

Universal Asynchronous Receiver/Transmitter

Under Bump Metal

User Datagram Protocol

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

Table 57.ꢀAcronyms and abbreviations...continued

Acronym

Definition

UNII

Unlicensed National Information Infrastructure

Voltage Controlled Oscillator

Voice Interface

VCO

VIF

VHT

Very High Throughput

WAP

Wireless Application Protocol

Wireless Access in Vehicular Environments

Wide band speech

WAVE

WBS

WCI-2

WEP

Wireless Coexistence Interface 2

Wired Equivalent Privacy

WI

Wired Interface

Wi-Fi

Hardware implementation of IEEE 802.11 for wireless connectivity

Wireless Local Area Network

Wi-Fi Multimedia

WLAN

WMM

WPA

Wi-Fi Protected Access

WPA2

WPA2-PSK

WPA3

WPA-PSK

XFQFN

XOSC

Wi-Fi Protected Access 2

Wi-Fi Protected Access 2-Pre-Shared Key

Wi-Fi Protected Access 3

Wi-Fi Protect Access-Pre-Shared Key

Extra-Fine Quad Flat Non-leaded

Crystal Oscillator

12 Revision history

Table 58.ꢀRevision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

88W8987_SDS v.2.0

20210521

Product short data

sheet

-

88W8987_SDS v.1.0

Modifications

• Updated Bluetooth certification compliance to version 5.2

88W8987_SDS v.1.0

20201008

Product short data

sheet

-

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

13 Legal information

13.1 Data sheet status

Document status^[1][2]

Product status^[3]

Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product

development.

Preliminary [short] data sheet

Product [short] data sheet

Qualification

Production

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

13.2 Definitions

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — A draft status on a document indicates that the content is still

under internal review and subject to formal approval, which may result

in modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included in a draft version of a document and shall have no

liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local NXP

Semiconductors sales office. In case of any inconsistency or conflict with the

short data sheet, the full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes

no representation or warranty that such applications will be suitable

for the specified use without further testing or modification. Customers

are responsible for the design and operation of their applications and

products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications

and products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with

their applications and products. NXP Semiconductors does not accept any

liability related to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications or products, or

the application or use by customer’s third party customer(s). Customer is

responsible for doing all necessary testing for the customer’s applications

and products using NXP Semiconductors products in order to avoid a

default of the applications and the products or of the application or use by

customer’s third party customer(s). NXP does not accept any liability in this

respect.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product

is deemed to offer functions and qualities beyond those described in the

Product data sheet.

13.3 Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, NXP Semiconductors does not

give any representations or warranties, expressed or implied, as to the

accuracy or completeness of such information and shall have no liability

for the consequences of use of such information. NXP Semiconductors

takes no responsibility for the content in this document if provided by an

information source outside of NXP Semiconductors. In no event shall NXP

Semiconductors be liable for any indirect, incidental, punitive, special or

consequential damages (including - without limitation - lost profits, lost

savings, business interruption, costs related to the removal or replacement

of any products or rework charges) whether or not such damages are based

on tort (including negligence), warranty, breach of contract or any other

legal theory. Notwithstanding any damages that customer might incur for

any reason whatsoever, NXP Semiconductors’ aggregate and cumulative

liability towards customer for the products described herein shall be limited

in accordance with the Terms and conditions of commercial sale of NXP

Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to

make changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

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No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Security — Customer understands that all NXP products may be subject

to unidentified or documented vulnerabilities. Customer is responsible

for the design and operation of its applications and products throughout

their lifecycles to reduce the effect of these vulnerabilities on customer’s

applications and products. Customer’s responsibility also extends to other

open and/or proprietary technologies supported by NXP products for use

in customer’s applications. NXP accepts no liability for any vulnerability.

Customer should regularly check security updates from NXP and follow up

appropriately. Customer shall select products with security features that best

meet rules, regulations, and standards of the intended application and make

the ultimate design decisions regarding its products and is solely responsible

for compliance with all legal, regulatory, and security related requirements

concerning its products, regardless of any information or support that may

be provided by NXP. NXP has a Product Security Incident Response Team

(PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation,

reporting, and solution release to security vulnerabilities of NXP products.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor

tested in accordance with automotive testing or application requirements.

NXP Semiconductors accepts no liability for inclusion and/or use of non-

automotive qualified products in automotive equipment or applications. In

the event that customer uses the product for design-in and use in automotive

applications to automotive specifications and standards, customer (a) shall

use the product without NXP Semiconductors’ warranty of the product for

such automotive applications, use and specifications, and (b) whenever

customer uses the product for automotive applications beyond NXP

Semiconductors’ specifications such use shall be solely at customer’s own

risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,

damages or failed product claims resulting from customer design and use

of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

13.4 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

NXP — wordmark and logo are trademarks of NXP B.V.

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

Tables

Tab. 1.

Tab. 2.

Tab. 3.

Tab. 4.

Tab. 5.

Tab. 6.

Part order codes ............................................... 6

Pin types ......................................................... 15

Pin list by number ........................................... 17

Pad locations—83-bump eWLP ...................... 20

General purpose I/O (GPIO) (MFP) ................ 23

Wi-Fi/Bluetooth radio interface - QFN

Tab. 32. Bluetooth and Bluetooth LE receiver

performance .................................................... 48

Tab. 33. Bluetooth and Bluetooth LE transmitter ...........50

Tab. 34. Current consumption .......................................52

Tab. 35. DC electrical characteristics—1.8V

operation (VIO_SD) .........................................55

package ...........................................................26

Wi-Fi/Bluetooth radio interface - eWLP

Tab. 36. SDIO timing data—Default Speed, High-

Speed Modes ..................................................56

Tab. 7.

package option ................................................26

Wi-Fi RF front-end control interface ................ 26

SDIO host interface .........................................27

Tab. 37. SDIO timing data——SDR12, SDR25,

Tab. 8.

Tab. 9.

SDR50 Modes (up to 100 MHz) (1.8V) ........... 57

Tab. 38. SDIO timing data—SDR104 mode (208

MHz) ................................................................58

Tab. 39. SDIO timing data—DDR50 mode (50 MHz) .... 59

Tab. 40. SDIO internal pull-up/pull-down

Tab. 10. UART host interface (MFP) .............................27

Tab. 11. Audio interface pins (MFP) ............................. 28

Tab. 12. Configuration interface .................................... 28

Tab. 13. Clock interface (MFP) ..................................... 29

Tab. 14. Power down (PDn) pin ....................................29

Tab. 15. Power supply and ground ............................... 30

Tab. 16. Configuration pins ........................................... 31

Tab. 17. Host configuration options ...............................31

Tab. 18. Absolute maximum ratings ..............................35

Tab. 19. Limiting values - QFN option ...........................35

Tab. 20. Limiting values - eWLP option ........................ 35

Tab. 21. Recommended operating conditions ...............36

Tab. 22. DC electrical characteristics—1.8V

specifications ...................................................60

Tab. 41. UART timing data ............................................61

Tab. 42. PCM timing specification data—Master

mode ............................................................... 62

Tab. 43. PCM timing specification data—Slave

mode ............................................................... 63

Tab. 44. Clock DC specifications .................................. 64

Tab. 45. 26 MHz clock timing ........................................64

Tab. 46. 38.4 MHz clock timing .....................................64

Tab. 47. Phase Noise—2.4 GHz operation ................... 65

Tab. 48. Phase Noise—5 GHz operation ...................... 65

Tab. 49. External crystal specifications ......................... 66

Tab. 50. External sleep clock specifications ..................66

Tab. 51. Power-down (PDn) pin specifications—The

power remains high at PDn assertion ............. 67

operation (VIO) ................................................37

Tab. 23. DC electrical characteristics—3.3V

operation (VIO) ................................................37

Tab. 24. LED mode data ...............................................37

Tab. 25. DC electrical characteristics—1.8V

operation (VIO_RF) .........................................38

Tab. 52. Power-down (PDn) pin secifications—

Tab. 26. DC electrical characteristics—3.3V

Power ramps down at PDn assertion ..............68

operation (VIO_RF) .........................................38

Tab. 53. Configuration pin specifications .......................68

Tab. 54. JTAG timing data ............................................ 69

Tab. 55. Thermal conditions—QFN package ................ 70

Tab. 56. Thermal conditions—eWLP package .............. 71

Tab. 57. Acronyms and abbreviations ...........................75

Tab. 58. Revision history ...............................................82

Tab. 27. 2.4 GHz Wi-Fi receiver performance ...............40

Tab. 28. 5 GHz Wi-Fi receiver performance ..................42

Tab. 29. 2.4 GHz Wi-Fi transmitter performance ...........45

Tab. 30. 5 GHz Wi-Fi transmitter performance ..............46

Tab. 31. Local oscillator ................................................ 47

Figures

Fig. 1.

Fig. 2.

Application diagram—QFN package option .......2

Application diagram—eWLP package

option .................................................................2

Internal block diagram—QFN package

option .................................................................5

Internal block diagram—eWLP package

option .................................................................5

Part numbering scheme ....................................6

Signal diagram—QFN ..................................... 13

Signal diagram—eWLP ...................................14

Pin assignment—68-pin QFN package

option ...............................................................16

Pad locations—83-bump eWLP (non-

bump-side view, bumps down) ........................19

Fig. 11.

Power-down sequence ....................................34

Fig. 12. RF performance measurement points .............39

Fig. 13. SDIO protocol timing diagram—Default

speed mode .................................................... 55

Fig. 14. SDIO protocol timing diagram—High-speed

mode ............................................................... 55

Fig. 15. SDIO protocol timing diagram—SDR12,

SDR25, SDR50 Modes (up to 100 MHz)

(1.8V) ...............................................................57

Fig. 16. SDIO protocol timing diagram—SDR104

mode (208 MHz) ............................................. 58

Fig. 17. SDIO CMD timing diagram—DDR50 mode

(50 MHz) ......................................................... 59

Fig. 18. SDIO DAT[3:0] timing diagram—DDR50

mode (50 MHz) ............................................... 59

Fig. 3.

Fig. 4.

Fig. 5.

Fig. 6.

Fig. 7.

Fig. 8.

Fig. 9.

Fig. 10. Power-up sequence ........................................ 33

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

Fig. 19. UART timing diagram ......................................61

Fig. 20. PCM timing specification diagram for data

signals—Master mode .....................................62

Fig. 21. PCM timing specification diagram for

PCM_SYNC signal—Master mode ..................62

Fig. 22. PCM timing specification diagram for data

signals—Slave mode .......................................63

Fig. 23. PCM timing specification diagram for

PCM_SYNC signal—Slave mode ................... 63

Fig. 24. Power-down (PDn) pin timing—The power

remains high at PDn assertion ........................67

Fig. 25. Power-down (PDn) pin timing—Power

ramps down at PDn assertion .........................67

Fig. 26. JTAG timing diagram .......................................69

Fig. 27. 68-pin QFN mechanical drawing .....................72

Fig. 28. 83-bump eWLP mechanical drawing ...............73

Fig. 29. 68-pin QFN package marking and pin 1

location ............................................................ 74

Fig. 30. eWLP package marking and pin 1 location ..... 74

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

Contents

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

2

3

3.1

3.2

3.3

3.4

3.5

3.6

4

4.1

4.2

4.3

4.4

4.5

5

5.1

5.1.1

5.1.2

5.2

5.3

5.3.1

5.4

Product overview ................................................ 1

9.2

RF front-end control interface specifications ....38

VIO_RF DC characteristics ..............................38

1.8V operation ................................................. 38

3.3V operation ................................................. 38

Wi-Fi radio specifications .................................39

Wi-Fi radio performance measurement ........... 39

2.4 GHz Wi-Fi receiver performance ............... 40

5 GHz Wi-Fi receiver performance .................. 42

2.4 GHz Wi-Fi transmitter performance ........... 45

5 GHz Wi-Fi transmitter performance .............. 46

Local oscillator .................................................47

Bluetooth radio specifications ..........................48

Bluetooth and Bluetooth LE receiver

Applications ........................................................3

Wi-Fi key features ............................................. 3

Bluetooth key features .......................................3

Host interfaces ...................................................3

Operating characteristics ...................................3

General features ................................................4

Internal block diagram ....................................... 5

Ordering information .......................................... 6

Wi-Fi subsystem ..................................................7

IEEE 802.11 standards ......................................7

Wi-Fi MAC ......................................................... 8

Wi-Fi baseband ................................................. 9

Wi-Fi radio ....................................................... 10

Wi-Fi encryption ...............................................10

Wi-Fi host interfaces ........................................10

Bluetooth subsystem ........................................11

2.4 GHz Bluetooth Tx/Rx .................................11

Bluetooth Low Energy (LE) ..............................11

Bluetooth host interfaces .................................12

Coexistence ..................................................... 12

PCM interface ..................................................12

Pin information ..................................................13

Signal diagrams ...............................................13

Signal diagram for QFN package option ..........13

Signal diagram for eWLP package option ........14

Pin types ..........................................................15

Pin assignment—68-pin QFN ..........................16

Pin list by number ............................................17

Pad locations—83-bump eWLP .......................19

Pin description .................................................23

Pin states .........................................................23

General purpose I/O (GPIO) ............................23

Wi-Fi/Bluetooth radio interface ........................ 26

Wi-Fi RF front-end control interface .................26

SDIO host interface ......................................... 27

UART host interface ........................................ 27

Audio interface .................................................28

Configuration interface .....................................28

Clock interface .................................................29

Power down (PDn) pin .................................... 29

Power supply and ground ................................30

Configuration pins ............................................31

Power information .............................................32

Power-up sequence .........................................32

Power-down sequence .................................... 34

Reset ................................................................34

Lowest power state ......................................... 34

Absolute maximum ratings ..............................35

Recommended operating conditions .............. 36

Electrical specifications ................................... 37

GPIO/LED interface specifications ...................37

VIO DC characteristics .................................... 37

1.8V operation ................................................. 37

3.3V operation ................................................. 37

LED mode ........................................................37

9.2.1

9.2.1.1

9.2.1.2

9.3

9.3.1

9.3.2

9.3.3

9.3.4

9.3.5

9.3.6

9.4

9.4.1

performance .....................................................48

Bluetooth and Bluetooth LE transmitter

9.4.2

performance .....................................................50

Current consumption ....................................... 52

SDIO host interface specifications ...................55

VIO_SD DC characteristics ............................. 55

1.8V operation ................................................. 55

Default speed, high-speed modes ...................55

SDR12, SDR25, SDR50 modes (up to 100

MHz) (1.8V) ..................................................... 57

SDR104 mode (208 MHz) (1.8V) .................... 58

DDR50 mode (50 MHz) (1.8V) ........................ 59

SDIO internal pull-up/pull-down

specifications ................................................... 60

High-speed UART specifications ..................... 61

Audio interface specifications .......................... 61

PCM interface specifications ........................... 61

Reference clock specifications ........................ 64

External crystal oscillator specifications ...........64

External crystal specifications ..........................66

External sleep clock specifications .................. 66

Power-down (PDn) pin specifications .............. 67

PDn asserted low—All power supplies good ... 67

PDn asserted Low—One or more power

supplies ramp down ........................................ 67

Configuration pin specifications .......................68

JTAG interface specifications .......................... 69

Package information .........................................70

Package thermal conditions .............................70

68-pin QFN thermal conditions ........................70

83-bump eWLP thermal conditions ..................71

Package mechanical drawing ..........................72

68-pin QFN mechanical drawing ..................... 72

83-bump eWLP mechanical drawing ............... 73

Package marking .............................................74

68-pin QFN package marking ..........................74

83-bump eWLP package marking ................... 74

Acronyms and abbreviations ...........................75

Revision history ................................................ 82

Legal information ..............................................83

9.5

9.6

9.6.1

9.6.1.1

9.6.2

9.6.3

9.6.4

9.6.5

9.6.6

9.7

9.8

9.8.1

9.9

9.9.1

9.9.2

9.9.3

9.10

9.10.1

9.10.2

5.5

5.5.1

5.5.2

5.5.3

5.5.4

5.5.5

5.5.6

5.5.7

5.5.8

5.5.9

5.5.10

5.5.11

5.6

6

6.1

6.2

6.3

6.3.1

7

8

9

9.1

9.11

9.12

10

10.1

10.1.1

10.1.2

10.2

10.2.1

10.2.2

10.3

10.3.1

10.3.2

11

12

13

9.1.1

9.1.1.1

9.1.1.2

9.1.2

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 21 May 2021

Document identifier: 88W8987_SDS


型号：	88W8987-A2-EAHE/AZ
厂家：	NXP
描述：	2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution
文件：	总88页 (文件大小：1062K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

88W8987-A2-EAHE/AZ [NXP]

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