933334330652 [NXP]
4000/14000/40000 SERIES, 64-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PDIP16, PLASTIC, SOT-38-1, DIP-16;
| 型号： | 933334330652 |
| 厂家： | 
NXP |
| 描述： | 4000/14000/40000 SERIES, 64-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PDIP16, PLASTIC, SOT-38-1, DIP-16 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总7页 (文件大小：76K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4557B
LSI
1-to-64 bit variable length shift
register
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4557B
LSI
1-to-64 bit variable length shift register
purposes. Information on DA or DB is shifted into the first
register position and all the data in the register is shifted
one position to the right on the LOW to HIGH transition of
CP0 while CP1 is LOW or on the HIGH to LOW transition
of CP1 while CP0 is HIGH. A HIGH on master reset (MR)
resets the register and forces O to LOW and O to HIGH,
independent of the other inputs.
DESCRIPTION
The HEF4557B is a static clocked serial shift register
whose length may be programmed to be any number of
bits between 1 and 64. The number of bits selected is
equal to the sum of the subscripts of the enabled length
control inputs (L1, L2, L4, L8, L16 and L32) plus one. Serial
data may be selected from the DA or DB data inputs with
the A/B select input. This feature is useful for recirculation
Fig.1 Functional diagram.
PINNING
HEF4557BP(N):
HEF4557BD(F):
HEF4557BT(D):
16-lead DIL; plastic
(SOT38-1)
DA, DB
A/B
data inputs
select data input
clock input
16-lead DIL; ceramic (cerdip)
(SOT74)
CP0
CP1
clock enable input
asynchronous master reset
bit-length control inputs
buffered outputs
16-lead SO; plastic
(SOT109-1)
MR
L1 to L32
O, O
( ): Package Designator North America
FAMILY DATA, IDD LIMITS category LSI
See Family Specifications
Fig.2 Pinning diagram.
January 1995
2
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Fig.3 Logic diagram.
Philips Semiconductors
Product specification
HEF4557B
LSI
1-to-64 bit variable length shift register
Notes
FUNCTION TABLE
1. The moment Dn appears at O depends on the
bit-length shown in the table below.
INPUTS
OUTPUT
MR A/B
DA
DB
D2
D2
D2
D2
X
CPO
CP1
L
O (1)
D2
D1
D2
D1
L
2. H = HIGH state (the more positive voltage)
3. L = LOW state (the less positive voltage)
4. X = state is immaterial
L
L
L
L
H
L
H
L
D1
D1
D1
D1
X
L
H
H
X
5.
6.
= positive-going transition
= negative-going transition
H
X
7. Dn = either HIGH or LOW
X
BIT-LENGTH SELECT FUNCTION TABLE
L32
L16
L8
L4
L2
L1
REGISTER LENGTH
L
L
L
L
L
L
L
L
L
L
↓
L
L
L
L
L
L
L
L
↓
L
L
L
L
L
H
L
1-bit
2-bits
3-bits
4-bits
5-bits
6-bits
7-bits
8-bits
↓
L
L
H
H
L
L
L
H
L
L
H
H
H
H
↓
L
L
H
L
L
H
H
↓
L
H
↓
↓
L
H
L
L
↓
H
L
L
↓
H
L
H
L
H
L
32-bits
33-bits
34-bits
↓
H
H
↓
L
L
H
↓
↓
↓
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
61-bits
62-bits
63-bits
64-bits
L
H
L
H
H
H
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
3 500 fi + ∑ (foCL) × VDD
where
2
15 000 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
2
37 000 fi + ∑ (foCL) × VDD
VDD = supply voltage (V)
January 1995
4
Philips Semiconductors
Product specification
HEF4557B
LSI
1-to-64 bit variable length shift register
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
TYP. MAX.
Propagation delays
CP0, CP1 → O, O
5
10
15
5
240
90
480
180
130
480
180
130
340
160
120
280
140
110
120
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
213 ns + (0,55 ns/pF) CL
79 ns + (0,23 ns/pF) CL
57 ns + (0,16 ns/pF) CL
213 ns + (0,55 ns/pF) CL
79 ns + (0,23 ns/pF) CL
57 ns + (0,16 ns/pF) CL
143 ns + (0,55 ns/pF) CL
69 ns + (0,23 ns/pF) CL
52 ns + (0,16 ns/pF) CL
113 ns + (0,55 ns/pF) CL
59 ns + (0,23 ns/pF) CL
47 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
HIGH to LOW
tPHL
65
240
90
LOW to HIGH
10
15
5
tPLH
tPHL
tPLH
tTHL
tTLH
65
MR → O
170
80
HIGH to LOW
10
15
5
60
MR → O
140
70
LOW to HIGH
10
15
5
55
Output transition times
HIGH to LOW
60
10
15
5
30
20
40
60
120
60
LOW to HIGH
10
15
30
20
40
Interpolation table (see note next page)
LENGTH CONTROL INPUTS
MINIMUM
NUMBER OF
BITS SELECTED
SET-UP, HOLD,
RECOVERY
TIMES
L1
L2
L4
L8
L16
L32
L
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
1
2
3
specified
six equal steps
specified
H
X
X
X
X
X
X
H
X
X
L
H
X
L
L
L
L
L
5
9
H
17
X
X
X
X
X
H
33
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
January 1995
5
Philips Semiconductors
Product specification
HEF4557B
LSI
1-to-64 bit variable length shift register
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns; see also waveforms Fig.4
VDD
V
SYMBOL MIN.
TYP.
Minimum clock
pulse width;
LOW for CP0 or
HIGH for CP1
Minimum reset
pulse width;
HIGH
5
tWCPL
or
180
90 ns
10
15
5
60
40
30 ns
20 ns
75 ns
35 ns
25 ns
tWCPH
150
70
10
15
tWMRH
50
Set-up times
DA, DB, A/B → CP0,
CP1
5
10
15
5
360
140
90
180 ns
70 ns
45 ns
−20 ns
−10 ns
−5 ns
tsu
L1 to L32 = LOW
40
L32 = HIGH
10
15
tsu
35
30
Hold times
DA, DB, A/B → CP0,
CP1
5
10
15
5
−40
−10
0
−110 ns
−45 ns
−30 ns
30 ns
20 ns
15 ns
250 ns
125 ns
75 ns
50 ns
30 ns
25 ns
thold
thold
tRMR
tRMR
fmax
see note
L1 to L32 = LOW
90
L32 = HIGH
10
15
5
60
50
Recovery times for MR
L1 to L32 = LOW
500
250
150
110
70
10
15
5
L32 = HIGH
10
15
5
60
Minimum clock
pulse frequency
2,5
7
5 MHz
10
15
14 MHz
20 MHz
10
Note
1. The set-up, hold and recovery times vary with the minimum number of bits selected. For other values as specified
one may interpolate as shown in the table (see previous page).
January 1995
6
Philips Semiconductors
Product specification
HEF4557B
LSI
1-to-64 bit variable length shift register
Fig.4 Waveforms showing recovery time for MR and minimum CP0, CP1 and MR pulse widths, set-up and hold
times for DA, DB and A/B to CP0 and CP1. Set-up and hold times are shown as positive values but may
be specified as negative values.
January 1995
7
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