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933372620652 [NXP]

IC 4000/14000/40000 SERIES, TRIPLE 1-INPUT INVERT GATE, PDSO14, PLASTIC, SOT-108-1, SO-14, Gate;
933372620652
型号： 933372620652
厂家： NXP    NXP
描述：

IC 4000/14000/40000 SERIES, TRIPLE 1-INPUT INVERT GATE, PDSO14, PLASTIC, SOT-108-1, SO-14, Gate

栅 输入元件 光电二极管 逻辑集成电路
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INTEGRATED CIRCUITS  
DATA SHEET  
For a complete data sheet, please also download:  
• The IC04 LOCMOS HE4000B Logic  
Family Specifications HEF, HEC  
• The IC04 LOCMOS HE4000B Logic  
Package Outlines/Information HEF, HEC  
HEF4007UB  
gates  
Dual complementary pair and  
inverter  
January 1995  
Product specification  
File under Integrated Circuits, IC04  
Philips Semiconductors  
Product specification  
HEF4007UB  
gates  
Dual complementary pair and inverter  
DESCRIPTION  
The HEF4007UB is a dual complementary pair and an inverter with access to each device. It has three n-channel and  
three p-channel enhancement mode MOS transistors.  
Fig.1 Schematic diagram.  
PINNING  
SP2, SP3  
source connections to 2nd and 3rd  
p-channel transistors  
DP1, DP2 drain connections from the 1st and 2nd  
p-channel transistors  
DN1, DN2 drain connections from the 1st and 2nd  
n-channel transistors  
SN2, SN3 source connections to the 2nd and 3rd  
n-channel transistors  
Fig.2 Pinning diagram.  
DN/P3  
common connection to the 3rd p-channel  
and n-channel transistor drains  
G1 to G3 gate connections to n-channel and  
p-channel of the three transistor pairs  
HEF4007UBP(N): 14-lead DIL; plastic  
(SOT27-1)  
FAMILY DATA, IDD LIMITS category GATES  
HEF4007UBD(F): 14-lead DIL; ceramic (cerdip)  
(SOT73)  
See Family Specifications for VIH/VIL unbuffered stages  
HEF4007UBT(D): 14-lead SO; plastic  
(SOT108-1)  
( ): Package Designator North America  
January 1995  
2
Philips Semiconductors  
Product specification  
HEF4007UB  
gates  
Dual complementary pair and inverter  
AC CHARACTERISTICS  
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns  
VDD  
V
TYPICAL EXTRAPOLATION  
FORMULA  
SYMBOL  
TYP.  
MAX.  
Propagation delays  
Gn → DN ; DP  
HIGH to LOW  
5
40  
20  
15  
40  
20  
15  
60  
30  
20  
60  
30  
20  
80  
40  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
13 ns + (0,55 ns/pF) CL  
9 ns + (0,23 ns/pF) CL  
7 ns + (0,16 ns/pF) CL  
13 ns + (0,55 ns/pF) CL  
9 ns + (0,23 ns/pF) CL  
7 ns + (0,16 ns/pF) CL  
10 ns + (1,0 ns/pF) CL  
9 ns + (0,42 ns/pF) CL  
6 ns + (0,28 ns/pF) CL  
10 ns + (1,0 ns/pF) CL  
9 ns + (0,42 ns/pF) CL  
6 ns + (0,28 ns/pF) CL  
10  
15  
5
tPHL  
tPLH  
tTHL  
tTLH  
30  
75  
LOW to HIGH  
10  
15  
5
40  
30  
Output transition times  
HIGH to LOW  
120  
60  
10  
15  
5
40  
120  
60  
LOW to HIGH  
10  
15  
40  
VDD  
V
TYPICAL FORMULA FOR P (µW)  
2
Dynamic power  
dissipation per  
package (P)  
5
10  
15  
4500 fi + ∑ (foCL) × VDD  
where  
2
20 000 fi + ∑ (foCL) × VDD  
fi = input freq. (MHz)  
fo = output freq. (MHz)  
CL = load capacitance (pF)  
∑(foCL) = sum of outputs  
2
50 000 fi + ∑ (foCL) × VDD  
VDD = supply voltage (V)  
January 1995  
3
Philips Semiconductors  
Product specification  
HEF4007UB  
gates  
Dual complementary pair and inverter  
Fig.3 Typical drain current ID and output voltage VO as  
functions of input voltage; VDD = 5 V; Tamb = 25 °C.  
Fig.4 Typical drain current ID and output voltage VO as  
functions of input voltage; VDD = 10 V; Tamb = 25 °C.  
Fig.5 Typical drain current ID and output voltage VO as  
functions of input voltage; VDD = 15 V; Tamb = 25 °C.  
January 1995  
4
Philips Semiconductors  
Product specification  
HEF4007UB  
gates  
Dual complementary pair and inverter  
APPLICATION INFORMATION  
Some examples of applications for the HEF4007UB are:  
• High input impedance amplifiers  
• Linear amplifiers  
• (Crystal) oscillators  
• High-current sink and source drivers  
• High impedance buffers.  
Fig.6 Voltage gain (Vo/Vi) as a function of supply  
voltage.  
Fig.7 Supply current as a function of supply  
voltage.  
This is also an example of an  
analogue amplifier using one  
HEF4007UB gate.  
Fig.8 Test set-up for measuring graphs of Figs 6  
and 7.  
January 1995  
5
Philips Semiconductors  
Product specification  
HEF4007UB  
gates  
Dual complementary pair and inverter  
Fig.9 Test set-up for measuring forward transconductance gfs = dio/dvi at vo is constant (see also graph Fig.10).  
A: average,  
B: average + 2 s,  
C: average − 2 s, in where ‘s’ is the observed standard deviation.  
Fig.10 Typical forward transconductance gfs as a function of the supply voltage at Tamb = 25 °C.  
January 1995  
6
Philips Semiconductors  
Product specification  
HEF4007UB  
gates  
Dual complementary pair and inverter  
Figures 11 to 14 show some applications in which the HEF4007UB is used.  
Fig.11 4 MHz crystal oscillator.  
Fig.12 High current sink driver.  
Fig.13 High current source driver.  
January 1995  
7
Philips Semiconductors  
Product specification  
HEF4007UB  
gates  
Dual complementary pair and inverter  
FUNCTION TABLE for Fig.14.  
INPUT  
DISABLE  
OUTPUT  
H
L
L
L
L
H
X
H
open  
Notes  
1. H = HIGH state (the more positive voltage)  
L = LOW state (the less positive voltage)  
X = state is immaterial  
NOTE  
Rules for maintaining electrical isolation between  
transistors and monolithic substrate:  
• Pin number 14 must be maintained at the most positive  
(or equally positive) potential with respect to any other  
pin of the HEF4007UB.  
• Pin number 7 must be maintained at the most negative  
(or equally negative) potential with respect to any other  
pin of the HEF4007UB.  
Violation of these rules will result in improper transistor  
operation and/or possible permanent damage to the  
HEF4007UB.  
Fig.14 High impedance buffer.  
January 1995  
8

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