933372700653 [NXP]
IC 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 10-BIT UP RING COUNTER, PDSO16, PLASTIC, SOT-109-1, SO-16, Counter;
| 型号： | 933372700653 |
| 厂家： | 
NXP |
| 描述： | IC 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 10-BIT UP RING COUNTER, PDSO16, PLASTIC, SOT-109-1, SO-16, Counter 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总8页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4017B
MSI
5-stage Johnson counter
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4017B
MSI
5-stage Johnson counter
A HIGH on MR resets the counter to zero
DESCRIPTION
(Oo = O5-9 = HIGH; O1 to O9 = LOW) independent of the
clock inputs (CP0, CP1).
The HEF4017B is a 5-stage Johnson decade counter with
ten spike-free decoded active HIGH outputs (Oo to O9), an
active LOW output from the most significant flip-flop (O5-9),
active HIGH and active LOW clock inputs (CP0, CP1) and
an overriding asynchronous master reset input (MR).
Automatic code correction of the counter is provided by an
internal circuit: following any illegal code the counter
returns to a proper counting mode within 11 clock pulses.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
The counter is advanced by either a LOW to HIGH
transition at CP0 while CP1 is LOW or a HIGH to LOW
transition at CP1 while CP0 is HIGH (see also function
table).
When cascading counters, the O5-9 output, which is LOW
while the counter is in states 5, 6, 7, 8 and 9, can be used
to drive the CP0 input of the next counter.
Fig.1 Functional diagram.
PINNING
CP0
clock input (LOW to HIGH triggered)
clock input (HIGH to LOW triggered)
master reset input
CP1
MR
O0 to O9
O5-9
decoded outputs
carry output (active LOW)
FAMILY DATA, IDD LIMITS category MSI
Fig.2 Pinning diagram.
See Family Specifications
HEF4017BP(N): 16-lead DIL; plastic (SOT38-1)
HEF4017BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF4017BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
January 1995
2
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Fig.3 Logic diagram.
Philips Semiconductors
Product specification
HEF4017B
MSI
5-stage Johnson counter
Notes
FUNCTION TABLE
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
MR
CP0
CP1
OPERATION
H
X
X
O0 = O5-9 = H; O1 to O9 = L
L
L
H
Counter advances
Counter advances
4.
5.
= positive-going transition
= negative-going transition
L
L
L
L
X
H
No change
No change
X
L
L
H
No change
No change
L
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
SYMBOL MIN.
TYP.
MAX.
FORMULA
Propagation delays
CP0, CP1 → O0 to O9
5
140
55
280
110
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
113 ns + (0,55 ns/pF) CL
44 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
98 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
118 ns + (0,55 ns/pF) CL
44 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
98 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
88 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
83 ns + (0,55 ns/pF) CL
34 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
103 ns + (0,55 ns/pF) CL
44 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
HIGH to LOW
10
15
5
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPLH
40
125
50
250
100
80
LOW to HIGH
10
15
5
40
CP0, CP1 → O5-9
145
55
290
110
80
HIGH to LOW
10
15
5
40
125
50
250
100
80
LOW to HIGH
10
15
5
40
MR → O1 to O9
115
50
230
100
70
HIGH to LOW
10
15
5
35
MR → O5-9
110
45
220
90
LOW to HIGH
10
15
5
35
70
MR → O0
130
55
260
105
75
LOW to HIGH
10
15
40
January 1995
4
Philips Semiconductors
Product specification
HEF4017B
MSI
5-stage Johnson counter
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN.
TYP.
MAX.
Output transition
times
5
10
15
5
60
30
20
60
30
20
120
60
ns
ns
ns
ns
ns
ns
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
HIGH to LOW
tTHL
40
120
60
LOW to HIGH
10
15
tTLH
40
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
MIN.
TYP.
MAX.
Hold times
CP0 →CP1
5
90
40
20
80
40
30
45
20
10
40
20
10
ns
ns
ns
ns
ns
ns
10
15
5
thold
CP1 → CP0
10
15
thold
Minimum clock
pulse width:
5
10
15
5
80
40
30
50
30
20
60
30
20
6
40
20
15
25
15
10
30
15
10
12
24
30
ns
tWCPL
tWCPH
=
CP0 = LOW;
ns
see also waveforms
Figs 4 and 5
CP1 = HIGH
ns
Minimum MR
pulse width; HIGH
ns
10
15
5
tWMRH
tRMR
fmax
ns
ns
Recovery time
for MR
ns
10
15
5
ns
ns
Maximum clock
pulse frequency
MHz
MHz
MHz
10
15
12
15
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
500 fi + ∑ (foCL) × VDD
where
2
2200 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load cap. (pF)
∑ (foCL) = sum of outputs
2
6000 fi + ∑ (foCL) × VDD
V
DD = supply voltage (V)
January 1995
5
Philips Semiconductors
Product specification
HEF4017B
MSI
5-stage Johnson counter
Fig.4 Waveforms showing hold times for CP0 to CP1 and CP1 to CP0. Hold times are shown as positive values,
but may be specified as negative values.
Conditions: CP1 = LOW while CP0 is triggered on a LOW to HIGH transition. tWCP and
tRMR also apply when CP0 = HIGH and CP1 is triggered on a HIGH to LOW transition.
Fig.5 Waveforms showing recovery time for MR; minimum CP0 and MR pulse widths.
January 1995
6
Philips Semiconductors
Product specification
HEF4017B
MSI
5-stage Johnson counter
Fig.6 Timing diagram.
January 1995
7
Philips Semiconductors
Product specification
HEF4017B
MSI
5-stage Johnson counter
APPLICATION INFORMATION
Some examples of applications for the HEF4017B are:
• Decade counter with decimal decoding
• 1 out of n decoding counter (when cascaded)
• Sequential controller
• Timer.
Figure 7 shows a technique for extending the number of decoded output states for the HEF4017B. Decoded outputs are
sequential within each stage and from stage to stage, with no dead time (except propagation delay).
Fig.7 Counter expansion.
Note
It is essential not to enable the counter on CP1 when CP0 is HIGH, or on CP0 when CP1 is LOW, as the this would cause
an extra count.
January 1995
8
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