933372800652 [NXP]

IC 4000/14000/40000 SERIES, DECIMAL DECODER/DRIVER, TRUE OUTPUT, PDSO16, PLASTIC, SOT-109-1, SO-16, Decoder/Driver;
933372800652
型号: 933372800652
厂家: NXP    NXP
描述:

IC 4000/14000/40000 SERIES, DECIMAL DECODER/DRIVER, TRUE OUTPUT, PDSO16, PLASTIC, SOT-109-1, SO-16, Decoder/Driver

驱动 光电二极管 输出元件 逻辑集成电路
文件: 总5页 (文件大小:46K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
INTEGRATED CIRCUITS  
DATA SHEET  
For a complete data sheet, please also download:  
The IC04 LOCMOS HE4000B Logic  
Family Specifications HEF, HEC  
The IC04 LOCMOS HE4000B Logic  
Package Outlines/Information HEF, HEC  
HEF4028B  
MSI  
1-of-10 decoder  
January 1995  
Product specification  
File under Integrated Circuits, IC04  
Philips Semiconductors  
Product specification  
HEF4028B  
MSI  
1-of-10 decoder  
DESCRIPTION  
The HEF4028B is a 4-bit BCD to 1-of-10 active HIGH  
decoder. A 1-2-4-8 BCD code applied to inputs A0 to A3  
causes the selected output to be HIGH, the other nine will  
be LOW. If desired, the device may be used as a 1-of-8  
decoder with enable; 3-bit octal inputs are applied to inputs  
A0, A1 and A2 selecting an output O0 to O7. Input A3 then  
becomes an active LOW enable, forcing the selected  
output LOW when A3 is HIGH. The HEF4028B may also  
be used as an 8-output (O0 to O7) demultiplexer with A0 to  
A2 as address inputs and A3 as an active LOW data input.  
The outputs are fully buffered for best performance.  
Fig.1 Functional diagram.  
HEF4028BP(N): 16-lead DIL; plastic  
(SOT38-1)  
HEF4028BD(F): 16-lead DIL; ceramic (cerdip)  
(SOT74)  
HEF4028BT(D): 16-lead SO; plastic  
(SOT109-1)  
( ): Package Designator North America  
PINNING  
Fig.2 Pinning diagram.  
A0 to A3  
O0 to O9  
address inputs, 1-2-4-8 BCD  
outputs (active HIGH)  
FAMILY DATA, IDD LIMITS category MSI  
See Family Specifications  
January 1995  
2
Philips Semiconductors  
Product specification  
HEF4028B  
MSI  
1-of-10 decoder  
Fig.3 Logic diagram.  
January 1995  
3
Philips Semiconductors  
Product specification  
HEF4028B  
MSI  
1-of-10 decoder  
TRUTH TABLE  
INPUTS  
OUTPUTS  
A3  
A2  
A1  
A0  
O0  
O1  
O2  
O3  
O4  
O5  
O6  
O7  
O8  
O9  
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
H
L
L
L
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
(2)  
L
H
L
H
H
H
Notes  
1. H = HIGH state (the more positive voltage)  
L = LOW state (the less positive voltage)  
2. Extraordinary states.  
January 1995  
4
Philips Semiconductors  
Product specification  
HEF4028B  
MSI  
1-of-10 decoder  
AC CHARACTERISTICS  
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns  
VDD  
V
TYPICAL EXTRAPOLATION  
FORMULA  
SYMBOL  
TYP.  
MAX.  
Propagation delays  
An On  
HIGH to LOW  
5
100  
40  
30  
90  
40  
30  
60  
30  
20  
60  
30  
20  
200  
80  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
73 ns  
29 ns  
22 ns  
63 ns  
29 ns  
22 ns  
10 ns  
9 ns  
+
+
+
+
+
+
+
+
+
+
+
+
(0,55 ns/pF) CL  
(0,23 ns/pF) CL  
(0,16 ns/pF) CL  
(0,55 ns/pF) CL  
(0,23 ns/pF) CL  
(0,16 ns/pF) CL  
(1,0 ns/pF) CL  
(0,42 ns/pF) CL  
(0,28 ns/pF) CL  
(1,0 ns/pF) CL  
(0,42 ns/pF) CL  
(0,28 ns/pF) CL  
10  
15  
5
tPHL  
60  
180  
80  
LOW to HIGH  
10  
15  
5
tPLH  
tTHL  
tTLH  
60  
Output transition times  
HIGH to LOW  
120  
60  
10  
15  
5
40  
6 ns  
120  
60  
10 ns  
9 ns  
LOW to HIGH  
10  
15  
40  
6 ns  
VDD  
V
TYPICAL FORMULA FOR P (µW)  
2
Dynamic power  
dissipation per  
package (P)  
5
10  
15  
350 fi + ∑ (foCL) × VDD  
where  
2
2 200 fi + ∑ (foCL) × VDD  
fi = input freq. (MHz)  
2
7 350 fi + ∑ (foCL) × VDD  
fo = output freq. (MHz)  
CL = total load cap. (pF)  
(foCL) = sum of outputs  
VDD = supply voltage (V)  
January 1995  
5

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