933373250653 [NXP]
IC 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, PLASTIC, SOT-109-1, SO-16, Counter;
| 型号： | 933373250653 |
| 厂家： | 
NXP |
| 描述： | IC 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, PLASTIC, SOT-109-1, SO-16, Counter 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总7页 (文件大小：62K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4520B
MSI
Dual binary counter
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4520B
MSI
Dual binary counter
LOW transition of the CP1 input if CP0 is low. Either CP0 or
CP1 may be used as the clock input to the counter and the
other clock input may be used as a clock enable input. A
HIGH on MR resets the counter (O0 to O3 = LOW)
independent of CP0, CP1.
DESCRIPTION
The HEF4520B is a dual 4-bit internally synchronous
binary counter. The counter has an active HIGH clock
input (CP0) and an active LOW clock input (CP1), buffered
outputs from all four bit positions (O0 to O3) and an active
HIGH overriding asynchronous master reset input (MR).
The counter advances on either the LOW to HIGH
transition of the CP0 input if CP1 is HIGH or the HIGH to
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
Fig.2 Pinning diagram.
HEF4520BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4520BD(F):
16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4520BT(D):
16-lead SO; plastic (SOT109-1)
(SOT109-1)
( ): Package Designator North America
Fig.1 Functional diagram.
PINNING
CP0A, CP0B
CP1A, CP1B
MRA, MRB
clock inputs (L to H triggered)
clock inputs (H to L triggered)
master reset inputs
outputs
O
O
0A to O3A
0B to O3B
outputs
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995
2
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Fig.3 Logic diagram (one counter).
FUNCTION TABLE
CP0
CP1
MR
L
MODE
counter advances
counter advances
no change
H
L
L
X
L
L
X
L
no change
L
no change
H
X
L
no change
X
H
O0 to O3 = LOW
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
= negative-going transition
Philips Semiconductors
Product specification
HEF4520B
MSI
Dual binary counter
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN. TYP. MAX.
V
Propagation delays
CP0 , CP1 → On
HIGH to LOW
5
10
15
5
110
50
40
110
50
40
75
35
25
220 ns
100 ns
80 ns
220 ns
100 ns
80 ns
150 ns
70 ns
50 ns
83 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
83 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
48 ns + (0,55 ns/pF) CL
24 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
tPHL
tPLH
tPHL
LOW to HIGH
10
15
5
MR → On
HIGH to LOW
10
15
Output transition
times
5
10
15
5
60
30
20
60
30
20
30
15
10
30
15
10
15
10
8
120 ns
60 ns
40 ns
120 ns
60 ns
40 ns
ns
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
HIGH to LOW
tTHL
LOW to HIGH
10
15
5
tTLH
Minimum CP0
60
30
20
60
30
20
30
20
16
50
30
20
50
30
20
50
30
20
8
pulse width; LOW
10
15
5
tWCPL
tWCPH
tWMRH
tRMR
tsu
ns
ns
Minimum CP1
ns
pulse width; HIGH
10
15
5
ns
ns
Minimum MR
ns
pulse width; HIGH
10
15
5
ns
ns
see also waveforms
Figs 4 and 5
Recovery time
for MR
25
15
10
25
15
10
25
15
10
16
30
40
ns
10
15
5
ns
ns
Set-up times
ns
CP0 → CP1
10
15
5
ns
ns
ns
CP1 → CP0
10
15
5
tsu
ns
ns
Maximum clock
pulse frequency
MHz
MHz
MHz
10
15
fmax
15
20
January 1995
4
Philips Semiconductors
Product specification
HEF4520B
MSI
Dual binary counter
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns
VDD
V
TYPICAL FORMULA FOR P (µW)
2
2
2
Dynamic power
5
850 fi + ∑ (foCL) × VDD
3 800 fi + ∑ (foCL) × VDD
10 200 fi + ∑ (foCL) × VDD
where
dissipation per
package (P)
10
15
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑(foCL) = sum of outputs
VDD = supply voltage (V)
Fig.4 Waveforms showing recovery time for MR; minimum CP0, CP1 and MR pulse widths.
January 1995
5
Philips Semiconductors
Product specification
HEF4520B
MSI
Dual binary counter
Fig.5 Waveforms showing set-up times for CP0 to CP1 and CP1 to CP0, and propagation delays.
January 1995
6
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Fig.6 Timing diagram.
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