933373460652 [NXP]
POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, PLASTIC, SOT-109-1, SO-16;
| 型号： | 933373460652 |
| 厂家： | 
NXP |
| 描述： | POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, PLASTIC, SOT-109-1, SO-16 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总5页 (文件大小：61K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF40174B
MSI
Hex D-type flip-flop
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF40174B
MSI
Hex D-type flip-flop
buffered outputs (O0 to O5). Information on D0 to D5 is
transferred to O0 to O5 on the LOW to HIGH transition of
CP if MR is HIGH. When LOW, MR resets all flip-flops
(O0 to O5 = LOW) independent of CP and D0 to D5.
DESCRIPTION
The HEF40174B is a hex edge-triggered D-type flip-flop
with six data inputs (D0 to D5), a clock input (CP), an
overriding asynchronous master reset input (MR), and six
Fig.1 Functional diagram.
PINNING
D0 to D5
CP
data inputs
clock input (LOW to HIGH; edge-triggered)
master reset input (active LOW)
MR
O0 to O5 buffered outputs
FUNCTION TABLE
INPUTS
Fig.2 Pinning diagram.
OUTPUT
CP
D
MR
O
H
H
H
HEF40174BP(N): 16-lead DIL; plastic
(SOT38-1)
L
X
X
H
H
L
L
no change
L
HEF40174BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
X
HEF40174BT(D): 16-lead SO; plastic
(SOT109-1)
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
( ): Package Designator North America
FAMILY DATA, IDD LIMITS category MSI
= positive-going transition
= negative-going transition
See Family Specifications
January 1995
2
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Fig.3 Logic diagram.
Philips Semiconductors
Product specification
HEF40174B
MSI
Hex D-type flip-flop
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
MIN. TYP. MAX.
Propagation delays
CP → On
HIGH to LOW
5
75
30
20
75
30
20
85
35
25
60
30
20
60
30
20
10
5
155 ns
65 ns
45 ns
155 ns
65 ns
45 ns
175 ns
70 ns
50 ns
120 ns
60 ns
40 ns
120 ns
60 ns
40 ns
ns
48 ns + (0,55 ns/pF) CL
19 ns + (0,23 ns/pF) CL
12 ns + (0,16 ns/pF) CL
48 ns + (0,55 ns/pF) CL
19 ns + (0,23 ns/pF) CL
12 ns + (0,16 ns/pF) CL
58 ns + (0,55 ns/pF) CL
24 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10
15
5
tPHL
LOW to HIGH
10
15
5
tPLH
tPHL
tTHL
tTLH
tsu
MR → On
HIGH to LOW
10
15
5
Output transition times
HIGH to LOW
10
15
5
LOW to HIGH
10
15
5
Set-up time
20
10
10
10
5
Dn → CP
10
15
5
ns
5
ns
Hold time
0
ns
Dn → CP
10
15
5
thold
tWCPL
tWMRL
tRMR
fmax
0
ns
5
0
ns
Minimum clock
70
30
20
70
35
25
45
20
15
5
35
15
10
35
15
10
25
10
5
ns
see also waveforms
Fig.4
pulse width; LOW
10
15
5
ns
ns
Minimum MR pulse
width; LOW
ns
10
15
5
ns
ns
Recovery time
for MR
ns
10
15
5
ns
ns
Maximum clock
pulse frequency
11
30
45
MHz
10
15
15
20
MHz
MHz
January 1995
4
Philips Semiconductors
Product specification
HEF40174B
MSI
Hex D-type flip-flop
VDD
V
TYPICAL FORMULA FOR P(µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
3500 fi + ∑ (foCL) × VDD
where
2
16 000 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
2
42 000 fi + ∑ (foCL) × VDD
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
Fig.4 Waveforms showing minimum pulse widths for CP and MR, MR to CP recovery time, and set-up time and
hold time for Dn to CP. Set-up and hold times are shown as positive values but may be specified as
negative values.
APPLICATION INFORMATION
Some examples of applications for the HEF40174B are:
• Shift registers
• Buffer/storage register
• Pattern generator
January 1995
5
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