933668990652 [NXP]

IC HCT SERIES, TRIPLE 3-INPUT OR GATE, PDIP14, DIP-14, Gate;


型号：	933668990652
厂家：	NXP
描述：	IC HCT SERIES, TRIPLE 3-INPUT OR GATE, PDIP14, DIP-14, Gate 栅输入元件光电二极管逻辑集成电路
文件：	总5页 (文件大小：32K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT4075

Triple 3-input OR gate

December 1990

Product speciﬁcation

File under Integrated Circuits, IC06

Philips Semiconductors

Product speciﬁcation

Triple 3-input OR gate

74HC/HCT4075

FEATURES

GENERAL DESCRIPTION

• Output capability: standard

• I_CCcategory: SSI

The 74HC/HCT4075 are high-speed Si-gate CMOS

devices and are pin compatible with the “4075” of the

“4000B” series. They are specified in compliance with

JEDEC standard no. 7A.

The 74HC/HCT4075 provide the 3-input OR function.

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C; t_r= t_f= 6 ns

TYPICAL

SYMBOL

t_PHL/ t_PLH

PARAMETER

CONDITIONS

UNIT

HCT

propagation delay nA, nB, nC to nY

input capacitance

C_L= 15 pF; V_CC= 5 V

C_I

3.5

C_PD

power dissipation capacitance per gate notes 1 and 2

Notes

1. C_PDis used to determine the dynamic power dissipation (P_Din µW):

P_D= C_PD× V_CC²× f_i+ ∑ (C_L× V_CC²× f_o) where:

f_i= input frequency in MHz

f_o= output frequency in MHz

∑ (C_L× V_CC²× f_o) = sum of outputs

C_L= output load capacitance in pF

V_CC= supply voltage in V

2. For HC the condition is V_I= GND to V_CC

For HCT the condition is V_I= GND to V_CC− 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

Philips Semiconductors

Product speciﬁcation

Triple 3-input OR gate

74HC/HCT4075

PIN DESCRIPTION

PIN NO.

3, 1, 11

4, 2, 12

5, 8, 13

6, 9, 10

SYMBOL

1A to 3A

1B to 3B

1C to 3C

1Y to 3Y

GND

NAME AND FUNCTION

data inputs

data outputs

ground (0 V)

V_CC

positive supply voltage

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

FUNCTION TABLE

INPUTS

OUTPUT

Notes

1. H = HIGH voltage level

L = LOW voltage level

X = don’t care

Fig.4 Functional diagram.

Fig.5 Logic diagram (one gate).

December 1990

Philips Semiconductors

Product speciﬁcation

Triple 3-input OR gate

74HC/HCT4075

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standard

I_CCcategory: SSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HC

SYMBOL PARAMETER

UNIT

WAVEFORMS

V_CC

(V)

+25

−40 to +85 −40 to +125

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

nA, nB, nC to nY

100

125

150

2.0 Fig.6

4.5

6.0

_THL/ t_TLHoutput transition time

110

2.0 Fig.6

4.5

6.0

December 1990

Philips Semiconductors

Product speciﬁcation

Triple 3-input OR gate

74HC/HCT4075

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standard

I_CCcategory: SSI

Note to HCT types

The value of additional quiescent supply current (∆I_CC) for a unit load of 1 is given in the family specifications.

To determine ∆I_CCper input, multiply this value by the unit load coefficient shown in the table below.

INPUT

UNIT LOAD COEFFICIENT

nA, nB, nC

1.50

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

WAVEFORMS

74HCT

SYMBOL PARAMETER

UNIT

V_CC

+25

−40 to +85 −40 to +125

(V)

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

nA, nB, nC to nY

4.5 Fig.6

_THL/ t_TLHoutput transition time

AC WAVEFORMS

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.6 Waveforms showing the input (nA, nB, nC) to output (nY) propagation delays and the output transition times.

PACKAGE OUTLINES

See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

December 1990

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