933669420652 [NXP]
HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP16, SOT-38-1, DIP-16;
| 型号： | 933669420652 |
| 厂家： | 
NXP |
| 描述： | HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP16, SOT-38-1, DIP-16 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总14页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT173
Quad D-type flip-flop; positive-edge
trigger; 3-state
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Quad D-type flip-flop; positive-edge trigger; 3-state
74HC/HCT173
synchronously with the LOW-to-HIGH clock (CP)
FEATURES
transition. When one or both En inputs are HIGH one
set-up time prior to the LOW-to-HIGH clock transition, the
register will retain the previous data. Data inputs and clock
enable inputs are fully edge-triggered and must be stable
only one set-up time prior to the LOW-to-HIGH clock
transition.
• Gated input enable for hold (do nothing) mode
• Gated output enable control
• Edge-triggered D-type register
• Asynchronous master reset
• Output capability: bus driver
• ICC category: MSI
The master reset input (MR) is an active HIGH
asynchronous input. When MR is HIGH, all four flip-flops
are reset (cleared) independently of any other input
condition.
GENERAL DESCRIPTION
The 3-state output buffers are controlled by a 2-input NOR
gate. When both output enable inputs (OE1 and OE2) are
LOW, the data in the register is presented to the Qn
outputs. When one or both OEn inputs are HIGH, the
outputs are forced to a high impedance OFF-state. The
3-state output buffers are completely independent of the
register operation; the OEn transition does not affect the
clock and reset operations.
The 74HC/HCT173 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT173 are 4-bit parallel load registers with
clock enable control, 3-state buffered outputs (Q0 to Q3)
and master reset (MR).
When the two data enable inputs (E1 and E2) are LOW, the
data on the Dn inputs is loaded into the register
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
tPHL/ tPLH
PARAMETER
propagation delay
CONDITIONS
UNIT
HC
HCT
CL = 15 pF; VCC = 5 V
CP to Qn
MR to Qn
17
13
17
17
ns
ns
fmax
CI
maximum clock frequency
input capacitance
88
3.5
20
88
MHz
pF
3.5
20
CPD
power dissipation
notes 1 and 2
pF
capacitance per flip-flop
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
2
∑ (CL × VCC × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC −1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Quad D-type flip-flop; positive-edge trigger; 3-state
74HC/HCT173
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1, 2
OE1, OE2
Q0 to Q3
CP
output enable input (active LOW)
3-state flip-flop outputs
3, 4, 5, 6
7
clock input (LOW-to-HIGH, edge-triggered)
ground (0 V)
8
GND
9, 10
E1, E2
D0 to D3
MR
data enable inputs (active LOW)
data inputs
14, 13, 12, 11
15
16
asynchronous master reset (active HIGH)
positive supply voltage
VCC
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Quad D-type flip-flop; positive-edge trigger; 3-state
74HC/HCT173
Fig.4 Functional diagram.
FUNCTION TABLE
INPUTS
MR CP E1 E2 Dn
OUTPUTS
REGISTER OPERATING MODES
Qn (register)
reset (clear)
parallel load
H
X
X
X
X
L
L
L
↑
↑
l
l
l
l
l
h
L
H
L
L
X
X
h
X
X
h
X
X
qn
qn
hold (no change)
INPUTS
OUTPUTS
3-STATE BUFFER OPERATING MODES
Qn (register) OE1 OE2 Q0 Q1 Q2 Q3
L
H
L
L
L
L
L
H
L
H
L
H
L
H
read
X
X
H
X
X
H
Z
Z
Z
Z
Z
Z
Z
Z
disabled
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced input (or output)
one set-up time prior to the LOW-to-HIGH CP transition
X = don’t care
Z = high impedance OFF-state
↑ = LOW-to-HIGH CP transition
December 1990
4
Philips Semiconductors
Product specification
Quad D-type flip-flop; positive-edge trigger; 3-state
74HC/HCT173
Fig.5 Logic diagram.
December 1990
5
Philips Semiconductors
Product specification
Quad D-type flip-flop; positive-edge trigger; 3-state
74HC/HCT173
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
55
20
16
175
35
30
220
44
37
265
53
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.6
4.5
6.0
tPHL
propagation delay
MR to Qn
44
16
13
150
30
26
190
38
33
225
45
38
2.0 Fig.7
4.5
6.0
t
t
t
PZH/ tPZL 3-state output enable time
52
19
15
150
30
26
190
38
33
225
45
38
2.0 Fig.8
4.5
6.0
OEn to Qn
PHZ/ tPLZ 3-state output disable time
OEn to Qn
52
19
15
150
30
26
190
38
33
225
45
38
2.0 Fig.8
4.5
6.0
THL/ tTLH output transition time
14
5
4
60
12
10
75
15
13
90
18
15
2.0 Fig.6
4.5
6.0
tW
clock pulse width
HIGH or LOW
80
16
14
14
5
4
100
20
17
120
24
20
2.0 Fig.6
4.5
6.0
tW
master reset pulse
width; HIGH
80
16
14
14
5
4
100
20
17
120
24
20
2.0 Fig.7
4.5
6.0
trem
tsu
tsu
removal time
MR to CP
60
12
10
−8
−3
−2
75
15
13
90
18
15
2.0 Fig.7
4.5
6.0
set-up time
En to CP
100 33
125
25
21
150
30
26
2.0 Fig.9
4.5
6.0
20
17
12
10
set-up time
Dn to CP
60
12
10
17
6
5
75
15
13
90
18
15
2.0 Fig.9
4.5
6.0
December 1990
6
Philips Semiconductors
Product specification
Quad D-type flip-flop; positive-edge trigger; 3-state
74HC/HCT173
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
th
hold time
En to CP
0
0
0
−17
−6
−5
0
0
0
0
0
0
ns
ns
2.0 Fig.9
4.5
6.0
th
hold time
Dn to CP
1
1
1
−11
−4
−3
1
1
1
1
1
1
2.0 Fig.9
4.5
6.0
fmax
maximum clock pulse
frequency
6.0
30
35
26
80
95
4.8
24
28
4.0
20
24
MHz 2.0 Fig.6
4.5
6.0
December 1990
7
Philips Semiconductors
Product specification
Quad D-type flip-flop; positive-edge trigger; 3-state
74HC/HCT173
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
OE1, OE2
MR
E1, E2
Dn
0.50
0.60
0.40
0.25
1.00
CP
December 1990
8
Philips Semiconductors
Product specification
Quad D-type flip-flop; positive-edge trigger; 3-state
74HC/HCT173
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
20
20
20
19
5
40
37
35
30
12
50
46
44
38
15
60
56
53
45
19
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.6
4.5 Fig.7
4.5 Fig.8
4.5 Fig.8
4.5 Fig.6
4.5 Fig.6
4.5 Fig.7
4.5 Fig.7
4.5 Fig.9
4.5 Fig.9
4.5 Fig.9
4.5 Fig.9
tPHL
propagation delay
MR to Qn
t
PZH/ tPZL 3-state output enable time
OEn to Qn
tPHZ/ tPLZ 3-state output disable time
OEn to Qn
t
THL/ tTLH output transition time
tW
clock pulse width
HIGH or LOW
16
15
12
22
12
0
7
20
19
15
28
15
0
24
22
18
33
18
0
tW
master reset pulse
width; HIGH
6
trem
tsu
tsu
th
removal time
MR to CP
−2
13
7
set-up time
En to CP
set-up time
Dn to CP
hold time
En to CP
−6
−3
80
th
hold time
Dn to CP
0
0
0
fmax
maximum clock pulse
frequency
30
24
20
MHz 4.5 Fig.6
December 1990
9
Philips Semiconductors
Product specification
Quad D-type flip-flop; positive-edge trigger;
3-state
74HC/HCT173
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the clock (CP) to
output (Qn) propagation delays, the clock
pulse width, the output transition times and
the maximum clock pulse frequency.
Fig.7 Waveforms showing the master reset (MR)
pulse width, the master reset to output (Qn)
propagation delays and the master reset to
clock (CP) removal time.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the data set-up and hold
times from input (En, Dn) to clock (CP).
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
PACKAGE OUTLINES
Fig.8 Waveforms showing the 3-state enable and
disable times.
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
10
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•
The 74HC/HCT173 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC standard no. 7A.
Cross-reference
Packages
•
•
End of Life
information
Distributors Go
Here!
The 74HC/HCT173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs (Q to Q )
0
3
•
•
and master reset (MR).
When the two data enable inputs (E and E ) are LOW, the data on the Dn inputs is loaded into the register
1
2
Models
•
•
synchronously with the LOW-to-HIGH clock (CP) transition. When one or both E inputs are HIGH one set-up time
n
SoC solutions
prior to the LOW-to-HIGH clock transition, the register will retain the previous data. Data inputs and clock enable
inputs are fully edge-triggered and must be stable only one set-up time prior to the LOW-to-HIGH clock transition.
The master reset input (MR) is an active HIGH asynchronous input. When MR is HIGH, all four flip-flops are reset
(cleared) independently of any other input condition.
The 3-state output buffers are controlled by a 2-input NOR gate. When both output enable inputs (OE and OE ) are
1
2
LOW, the data in the register is presented to the Q outputs. When one or both OE inputs are HIGH, the outputs
n
n
are forced to a high impedance OFF-state. The 3-state output buffers are completely independent of the register
operation; the OE transition does not affect the clock and reset operations.
n
Features
●
●
●
●
●
●
Gated input enable for hold (do nothing) mode
Gated output enable control
Edge-triggered D-type register
Asynchronous master reset
Output capability: bus driver
I
category: MSI
CC
Datasheet
Type number Title
Publication release Datasheet status
date
Page
count
File
size
(kB)
Datasheet
74HC/HCT173 Quad D-type 12/1/1990
Product specification 10
65
Download
flip-flop;
positive-edge
trigger; 3-
state
Additional datasheet info
To complete the device datasheet with package and family information, also download the following PDF files. The
"Logic Package Information" document is required to determine in which package(s) this device is available.
Document
Description
1
2
3
HCT_FAMILY_SPECIFICATIONS HC/T Family Specifications, The IC06 74HC/HCT/HCMOS Logic
Family Specifications
HCT_PACKAGE_INFO
HC/T Package Info, The IC06 74HC/HCT/HCMOS Logic Package
Information
HCT_PACKAGE_OUTLINES
HC/T Package Outlines, The IC06 74HC/HCT/HCMOS Logic
Package Outlines
Parametrics
Type number Package
Description Propagation Voltage No. Power
Logic
Output
Delay(ns)
of Dissipation
Pins Considerations Levels
Switching Drive
Capability
Quad D-
Type Flip-
Flop;
Postive-
Edge
Low Power or
16 Battery
SOT109
74HC173D
5 Volts
+
15
CMOS
CMOS
CMOS
Low
(SO16)
Applications
Trigger; 3-
State
Quad D-
Type Flip-
Flop;
Postive-
Edge
Low Power or
16 Battery
SOT338-1
74HC173DB
5 Volts
+
15
15
Low
Low
(SSOP16)
Applications
Trigger; 3-
State
Quad D-
Type Flip-
Flop;
Postive-
Edge
Low Power or
16 Battery
Applications
SOT38-1
74HC173N
5 Volts
+
(DIP16)
Trigger; 3-
State
Quad D-
Type Flip-
Flop;
Postive-
Edge
Low Power or
16 Battery
SOT403-1
(TSSOP16)
5 Volts
+
74HC173PW
15
15
CMOS
Low
Low
Applications
Trigger; 3-
State
Quad D-
Type Flip-
Flop;
Postive-
Edge
Low Power or
16 Battery
SOT109
(SO16)
5 Volts
+
74HCT173D
TTL
Trigger;
TTL
Applications
Enabled (3-
State)
Quad D-
Type Flip-
Flop;
Postive-
Edge
Trigger;
TTL
Low Power or
16 Battery
SOT338-1
(SSOP16)
5 Volts
+
74HCT173DB
15
TTL
Low
Applications
Enabled (3-
State)
Quad D-
Type Flip-
Flop;
Postive-
Edge
Trigger;
TTL
Low Power or
16 Battery
Applications
SOT38-1
(DIP16)
5 Volts
+
74HCT173N
15
TTL
Low
Enabled (3-
State)
Products, packages, availability and ordering
Type number North
American
Ordering code Marking/Packing Package Device status Buy online
Discretes
(12NC)
packing info
type number
Standard Marking
9337 145 60652 * Bulk Pack,
CECC
SOT109
(SO16)
74HC173D
74HC173D
Full production
Standard Marking
74HC173D-T 9337 145 60653 * Reel Pack,
SMD, 13", CECC
SOT109
(SO16)
Full production
Full production
Full production
SOT338-1
(SSOP16)
Standard Marking
* Bulk Pack
74HC173DB 74HC173DB 9351 892 50112
Standard Marking
9351 892 50118 * Reel Pack,
SOT338-1
(SSOP16)
74HC173DB-
T
SMD, 13"
Standard Marking
9336 694 20652 * Bulk Pack,
CECC
SOT38-1
(DIP16)
74HC173N
74HC173N
Full production
SOT403-1
Standard Marking
* Bulk Pack
74HC173PW 74HC173PW 9351 895 50112
74HC173PW-
Full production
Full production
(TSSOP16)
Standard Marking
9351 895 50118 * Reel Pack,
SOT403-1
(TSSOP16)
T
SMD, 13"
Standard Marking
74HCT173D 74HCT173D 9337 150 40652 * Bulk Pack,
CECC
SOT109
(SO16)
Full production
Standard Marking
9337 150 40653 * Reel Pack,
SMD, 13", CECC
SOT109
(SO16)
74HCT173D-
T
Full production
Full production
Full production
SOT338-1
(SSOP16)
Standard Marking
* Bulk Pack
74HCT173DB 74HCT173DB 9351 897 10112
Standard Marking
9351 897 10118 * Reel Pack,
SOT338-1
(SSOP16)
74HCT173DB-
T
SMD, 13"
Standard Marking
74HCT173N 74HCT173N 9336 700 50652 * Bulk Pack,
CECC
SOT38-1
(DIP16)
Full production
Products in the above table are all in production. Some variants are discontinued; click here for information on these
variants.
Similar products
74HC/HCT173 links to the similar products page containing an overview of products that are similar in
function or related to the type number(s) as listed on this page. The similar products page includes products from the
same catalog tree(s), relevant selection guides and products from the same functional category.
Support & tools
HC/T Family Specifications, The IC06 74HC/HCT/HCMOS Logic Family Specifications(date 01-Mar-98)
HC/T User Guide(date 01-Nov-97)
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