933669560652 [NXP]
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| 型号： | 933669560652 |
| 厂家： | 
NXP |
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT259
8-bit addressable latch
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
8-bit addressable latch
74HC/HCT259
capable of storing single-line data in eight addressable
latches, and also 3-to-8 decoder and demultiplexer, with
active HIGH outputs (Q0 to Q7), functions are available.
FEATURES
• Combines demultiplexer and 8-bit latch
• Serial-to-parallel capability
• Output from each storage bit available
• Random (addressable) data entry
• Easily expandable
The “259” also incorporates an active LOW common reset
(MR) for resetting all latches, as well as, an active LOW
enable input (LE).
The “259” has four modes of operation as shown in the
mode select table. In the addressable latch mode, data on
the data line (D) is written into the addressed latch. The
addressed latch will follow the data input with all
non-addressed latches remaining in their previous states.
In the memory mode, all latches remain in their previous
states and are unaffected by the data or address inputs.
• Common reset input
• Useful as a 3-to-8 active HIGH decoder
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
In the 3-to-8 decoding or demultiplexing mode, the
addressed output follows the state of the D input with all
other outputs in the LOW state. In the reset mode all
outputs are LOW and unaffected by the address (A0 to A2)
and data (D) input. When operating the “259” as an
addressable latch, changing more than one bit of address
could impose a transient-wrong address. Therefore, this
should only be done while in the memory mode. The mode
select table summarizes the operations of the “259”.
The 74HC/HCT259 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT259 are high-speed 8-bit addressable
latches designed for general purpose storage applications
in digital systems. The “259” are multifunctional devices
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
CL = 15 pF; VCC = 5 V
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
D to Qn
18
17
15
3.5
19
20
20
20
3.5
19
ns
ns
ns
pF
pF
An, LE to Qn
MR to Qn
tPHL
CI
input capacitance
CPD
power dissipation capacitance per latch notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
December 1990
2
Philips Semiconductors
Product specification
8-bit addressable latch
74HC/HCT259
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
PIN DESCRIPTION
PIN NO.
SYMBOL
A0 to A2
Q0 to Q7
GND
D
NAME AND FUNCTION
1, 2, 3
address inputs
4, 5, 6, 7, 9 10, 11, 12
latch outputs
8
ground (0 V)
13
14
15
16
data input
LE
latch enable input (active LOW)
conditional reset input (active LOW)
positive supply voltage
MR
VCC
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
8-bit addressable latch
74HC/HCT259
Fig.4 Functional diagram.
MODE SELECT TABLE
LE
MR MODE
L
H
L
H
H
L
addressable latch
memory
active HIGH 8-channel demultiplexer
reset
H
L
December 1990
4
Philips Semiconductors
Product specification
8-bit addressable latch
74HC/HCT259
FUNCTION TABLE
OPERATING
INPUTS
A0
OUTPUTS
Q3 Q4
MODES
MR LE
D
A1
A2
Q0
Q1
Q2
Q5
Q6
Q7
master reset
L
H
X
X
X
X
L
L
L
Q=d
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
d
d
d
d
L
H
L
L
L
H
H
L
L
L
L
Q=d
L
L
Q=d
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
demultiplex
(active HIGH)
decoder
H
L
Q=d
L
L
L
L
L
L
L
L
d
d
d
d
L
H
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Q=d
L
Q=d
L
L
L
Q=d
L
L
L
L
(when D = H)
L
L
L
H
L
Q=d
store (do nothing)
addressable latch
H
H
X
X
X
X
q0
q1
q2
q2
q3
q4
q5
q6
q7
H
H
H
H
L
L
L
L
d
d
d
d
L
H
L
L
L
H
H
L
L
L
L
Q=d q1
q3
q3
q4
q4
q4
q5
q5
q5
q5
q6
q6
q6
q6
q7
q7
q7
q7
q0
q0
q0
Q=d q2
q1
q1
Q=d q3
q2
H
Q=d q4
H
H
H
H
L
L
L
L
d
d
d
d
L
H
L
L
L
H
H
H
H
H
H
q0
q0
q0
q0
q1
q1
q1
q1
q2
q2
q2
q2
q3
q3
q3
q3
Q=d q5
q6
q7
q7
q4
q4
q4
Q=d q6
q5
q5
Q=d q7
q6 Q=d
H
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition
q = lower case letters indicate the state of the referenced output established during the last cycle in which it was
addressed or cleared
December 1990
5
Philips Semiconductors
Product specification
8-bit addressable latch
74HC/HCT259
Fig.5 Logic diagram.
December 1990
6
Philips Semiconductors
Product specification
8-bit addressable latch
74HC/HCT259
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
D to Qn
58
21
17
185
37
31
230
46
39
280
56
48
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.7
4.5
6.0
t
t
PHL/ tPLH propagation delay
An to Qn
58
21
17
185
37
31
230
46
39
280
56
48
2.0 Fig.8
4.5
6.0
PHL/ tPLH propagation delay
LE to Qn
55
20
16
170
34
29
215
43
37
255
51
43
2.0 Fig.6
4.5
6.0
tPHL
propagation delay
MR to Qn
50
18
14
155
31
26
195
39
33
235
47
40
2.0 Fig.9
4.5
6.0
t
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
119
22
19
2.0 Figs 6 and 7
4.5
6.0
tW
tW
tsu
th
LE pulse width
HIGH or LOW
70
14
12
17
6
5
90
18
15
105
21
18
2.0 Fig.6
4.5
6.0
MR pulse width
LOW
70
14
12
17
6
5
90
18
15
105
21
18
2.0 Fig.9
4.5
6.0
set-up time
D, An to LE
80
16
14
19
7
6
100
20
17
120
24
20
2.0 Figs 10 and 11
4.5
6.0
hold time
D to LE
0
0
0
−19
−6
−5
0
0
0
0
0
0
2.0 Fig.10
4.5
6.0
th
hold time
An to LE
2
2
2
−11
−4
−3
2
2
2
2
2
2
2.0 Fig.11
4.5
6.0
December 1990
7
Philips Semiconductors
Product specification
8-bit addressable latch
74HC/HCT259
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
An
LE
D
1.50
1.50
1.20
0.75
MR
December 1990
8
Philips Semiconductors
Product specification
8-bit addressable latch
74HC/HCT259
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 TO +85 −40 TO +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
D to Qn
23
25
22
23
7
39
41
38
39
15
49
51
48
49
19
59
62
57
59
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.7
t
PHL/ tPLH propagation delay
An to Qn
4.5 Fig.8
t
PHL/ tPLH propagation delay
LE to Qn
4.5 Fig.6
tPHL
propagation delay
MR to Qn
4.5 Fig.9
t
THL/ tTLH output transition time
4.5 Figs 6 and 7
4.5 Fig.6
tW
tW
tsu
tsu
th
LE pulse width
LOW
19
18
17
17
0
11
10
10
10
−8
−4
24
23
21
21
0
29
27
26
26
0
MR pulse width
LOW
4.5 Fig.9
set-up time
D to LE
4.5 Fig.10
4.5 Fig.11
4.5 Fig.10
4.5 Fig.11
set-up time
An to LE
hold time
D to LE
th
hold time
An to LE
0
0
0
December 1990
9
Philips Semiconductors
Product specification
8-bit addressable latch
74HC/HCT259
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the enable input (LE) to output (Qn) propagation delays, the enable input pulse width
and the output transition times.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the data input (D) to output (Qn) propagation delays and the output transition times.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the address inputs (An) to outputs (Qn) propagation delays and the output transition
times.
December 1990
10
Philips Semiconductors
Product specification
8-bit addressable latch
74HC/HCT259
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the conditional reset input (MR) to output (Qn) propagation delays.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the data set-up and hold times for the D input to LE input.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing the address set-up and hold times for An inputs to LE input.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
11
it Q
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74HC/HCT259; 8-bit
addressable latch
download datasheet
Download datasheet
General description
Features
Datasheet
Applications
Support & tools
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Parametrics
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Function
General description
The 74HC/HCT259 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC standard no. 7A.
Catalog by
System
•
The 74HC/HCT259 are high-speed 8-bit addressable latches designed for general purpose storage applications in
digital systems. The '259' are multifunctional devices capable of storing single-line data in eight addressable latches,
Cross-reference
Packages
•
•
and also 3-to-8 decoder and demultiplexer, with active HIGH outputs (Q to Q ), functions are available.
0
7
End of Life
information
Distributors Go
Here!
•
•
The '259' also incorporates an active LOW common reset (MR) for resetting all latches, as well as, an active LOW
enable input (LE).
Models
•
•
The '259' has four modes of operation as shown in the mode select table. In the addressable latch mode, data on the
data line (D) is written into the addressed latch. The addressed latch will follow the data input with all non-addressed
latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are
unaffected by the data or address inputs.
SoC solutions
In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state of the D input with all other
outputs in the LOW state. In the reset mode all outputs are LOW and unaffected by the address (A to A ) and data
0
2
(D) input. When operating the '259' as an addressable latch, changing more than one bit of address could impose a
transient-wrong address. Therefore, this should only be done while in the memory mode. The mode select table
summarizes the operations of the '259'.
Features
●
●
●
●
●
●
●
●
●
Combines demultiplexer and 8-bit latch
Serial-to-parallel capability
Output from each storage bit available
Random (addressable) data entry
Easily expandable
Common reset input
Useful as a 3-to-8 active HIGH decoder
Output capability: standard
I
category: MSI
CC
Datasheet
Type number Title
Publication
release date
Datasheet status
Page
count
File
size
(kB)
Datasheet
74HC/HCT259 8-bit addressable 12/1/1990
latch
Product
specification
11
83
Download
Additional datasheet info
To complete the device datasheet with package and family information, also download the following PDF files. The
"Logic Package Information" document is required to determine in which package(s) this device is available.
Document
Description
1
2
3
HCT_FAMILY_SPECIFICATIONS HC/T Family Specifications, The IC06 74HC/HCT/HCMOS Logic
Family Specifications
HCT_PACKAGE_INFO
HC/T Package Info, The IC06 74HC/HCT/HCMOS Logic Package
Information
HCT_PACKAGE_OUTLINES
HC/T Package Outlines, The IC06 74HC/HCT/HCMOS Logic
Package Outlines
Parametrics
Type number Package
Description Propagation Voltage No. Power
Delay(ns) of Dissipation
Pins Considerations Levels
Low Power or
16 Battery
Logic
Switching Drive
Output
Capability
8-Bit
Addressable 15
Latch
SOT109
74HC259D
5 Volts
+
CMOS
CMOS
CMOS
CMOS
Low
(SO16)
Applications
8-Bit
Addressable 15
Latch
Low Power or
16 Battery
SOT338-1
74HC259DB
5 Volts
+
Low
Low
Low
(SSOP16)
Applications
8-Bit
Addressable 15
Latch
Low Power or
16 Battery
SOT38-1
74HC259N
5 Volts
+
(DIP16)
Applications
8-Bit
Addressable 15
Latch
Low Power or
16 Battery
SOT403-1
74HC259PW
5 Volts
+
(TSSOP16)
Applications
8-Bit
Addressable
Latch; TTL
Enabled
Low Power or
16 Battery
SOT109
74HCT259D
5 Volts
+
15
TTL
TTL
TTL
Low
Low
Low
(SO16)
Applications
8-Bit
Low Power or
16 Battery
SOT338-1
74HCT259DB
Addressable
15
5 Volts
+
Latch; TTL
(SSOP16)
Applications
Enabled
8-Bit
Low Power or
16 Battery
Applications
SOT38-1
74HCT259N
Addressable
15
5 Volts
+
Latch; TTL
(DIP16)
Enabled
8-Bit
Low Power or
16 Battery
Applications
SOT403-1
(TSSOP16)
Addressable
Latch; TTL
Enabled
5 Volts
+
74HCT259PW
15
TTL
Low
Products, packages, availability and ordering
Type number North
Ordering code Marking/Packing Package Device status Buy online
Discretes
American type (12NC)
number
packing info
Standard Marking
9337 146 50652 * Bulk Pack,
SOT109
(SO16)
74HC259D
74HC259D
Full production
CECC
Standard Marking
74HC259D-T 9337 146 50653 * Reel Pack,
SOT109
(SO16)
Full production
Full production
Full production
SMD, 13", CECC
SOT338-1
(SSOP16)
Standard Marking
* Bulk Pack
74HC259DB 74HC259DB 9351 874 10112
74HC259DB-
Standard Marking
9351 874 10118 * Reel Pack,
SOT338-1
(SSOP16)
T
SMD, 13"
Standard Marking
9336 695 60652 * Bulk Pack,
SOT38-1
(DIP16)
74HC259N
74HC259N
Full production
Full production
Full production
CECC
SOT403-1
Standard Marking
* Bulk Pack
74HC259PW 74HC259PW 9351 746 90112
74HC259PW-
(TSSOP16)
Standard Marking
9351 746 90118 * Reel Pack,
SOT403-1
(TSSOP16)
T
SMD, 13"
Standard Marking
74HCT259D 74HCT259D 9337 151 30652 * Bulk Pack,
CECC
SOT109
(SO16)
Full production
Standard Marking
9337 151 30653 * Reel Pack,
SMD, 13", CECC
SOT109
(SO16)
74HCT259D-
T
Full production
Full production
Full production
SOT338-1
(SSOP16)
Standard Marking
* Bulk Pack
74HCT259DB 74HCT259DB 9351 874 00112
Standard Marking
9351 874 00118 * Reel Pack,
SOT338-1
(SSOP16)
74HCT259DB-
T
SMD, 13"
Standard Marking
74HCT259N 74HCT259N 9336 701 90652 * Bulk Pack,
CECC
SOT38-1
(DIP16)
Full production
Full production
Full production
SOT403-1
Standard Marking
* Bulk Pack
74HCT259PW 74HCT259PW 9351 884 10112
(TSSOP16)
Standard Marking
9351 884 10118 * Reel Pack,
SOT403-1
74HCT259PW-
T
(TSSOP16)
SMD, 13"
Similar products
74HC/HCT259 links to the similar products page containing an overview of products that are similar in
function or related to the type number(s) as listed on this page. The similar products page includes products from the
same catalog tree(s), relevant selection guides and products from the same functional category.
Support & tools
HC/T Family Specifications, The IC06 74HC/HCT/HCMOS Logic Family Specifications(date 01-Mar-98)
HC/T User Guide(date 01-Nov-97)
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