933713850653 [NXP]

IC HCT SERIES, OCTAL 1-BIT DRIVER, INVERTED OUTPUT, PDSO20, PLASTIC, SO-20, Bus Driver/Transceiver;


型号：	933713850653
厂家：	NXP
描述：	IC HCT SERIES, OCTAL 1-BIT DRIVER, INVERTED OUTPUT, PDSO20, PLASTIC, SO-20, Bus Driver/Transceiver 驱动光电二极管输出元件逻辑集成电路
文件：	总7页 (文件大小：61K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT563

Octal D-type transparent latch;

3-state; inverting

December 1990

Product speciﬁcation

File under Integrated Circuits, IC06

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state;

inverting

74HC/HCT563

TTL (LSTTL). They are specified in

common to all latches.

FEATURES

compliance with JEDEC standard no.

7A.

When LE is HIGH, data at the D_n

inputs enter the latches. In this

condition the latches are transparent,

i.e. a latch output will change state

each time its corresponding D-input

changes.

• 3-state inverting outputs for bus

oriented applications

The 74HC/HCT563 are octal D-type

transparent latches featuring

separate D-type inputs for each latch

and inverting 3-state outputs for bus

oriented applications.

A latch enable (LE) input and an

output enable (OE) input are common

to all latches.

• Inputs and outputs on opposite

sides of package allowing easy

interface with microprocessor

• Common 3-state output enable

input

When LE is LOW the latches store the

information that was present at the

D-inputs a set-up time preceding the

HIGH-to-LOW transition of LE.

• Output capability: bus driver

• I_CCcategory: MSI

When OE is LOW, the contents of the

8 latches are available at the outputs.

When OE is HIGH, the outputs go to

the high impedance OFF-state.

Operation of the OE input does not

affect the state of the latches.

The “563” is functionally identical to

the “573”, but has inverted outputs.

GENERAL DESCRIPTION

The “563” consists of eight D-type

transparent latches with 3-state

inverting outputs. The LE and OE are

The 74HC/HCT563 are high-speed

Si-gate CMOS devices and are pin

compatible with low power Schottky

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C; t_r= t_f= 6 ns

TYPICAL

UNIT

SYMBOL

PARAMETER

CONDITIONS

HCT

t_PHL/t_PLH

C_I

propagation delay D_n, LE to Q_n

input capacitance

C_L= 15 pF; V_CC= 5 V

notes 1 and 2

3.5

C_PD

power dissipation capacitance per latch

Notes

1. C_PDis used to determine the dynamic power dissipation (P_Din µW):

P_D= C_PD× V_CC²× f_i+ ∑ (C_L× V_CC× f_o) where:

f_i= input frequency in MHz

f_o= output frequency in MHz

∑ (C_L× V_CC²× f_o) = sum of outputs

C_L= output load capacitance in pF

V_CC= supply voltage in V

2. For HC the condition is V_I= GND to V_CC

for HCT the condition is V_I= GND to V_CC− 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state;

inverting

74HC/HCT563

PIN DESCRIPTION

PIN NO.

SYMBOL

D₀to D₇

NAME AND FUNCTION

2, 3, 4, 5, 6, 7, 8, 9

data inputs

latch enable input (active HIGH)

3-state output enable input (active LOW)

ground (0 V)

GND

19, 18, 17, 16, 15, 14, 13, 12

Q₀to Q₇

V_CC

3-state latch outputs

positive supply voltage

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

December 1990

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state;

inverting

74HC/HCT563

FUNCTION TABLE

INPUTS

OUT-

PUTS

INTER-

NAL

OPERATING

MODES

LATCHES

Q₀to Q₇

OE LE D_n

enable and

read register

latch and read

latch register

and disable

outputs

Notes

1. H = HIGH voltage level

h = HIGH voltage level one set-up time prior to the

HIGH-to-LOW LE transition

L = LOW voltage level

l = LOW voltage level one set-up time prior to the

HIGH-to-LOW LE transition

Fig.4 Functional diagram.

Z = high impedance OFF-state

Fig.5 Logic diagram.

December 1990

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state;

inverting

74HC/HCT563

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: bus driver

I_CCcategory: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HC

SYMBOL PARAMETER

UNIT

V_CC

(V)

+25

−40 to +85 −40 to +125

WAVEFORMS

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

D_nto Q_n

145

180

220

2.0 Fig.6

4.5

6.0

_PHL/ t_PLHpropagation delay

LE to Q_n

145

180

220

2.0 Fig.7

4.5

6.0

_PZH/ t_PZL3-state output enable

150

190

225

2.0 Fig.8

4.5

6.0

time

OE to Q_n

_PHZ/ t_PLZ3-state output disable

150

190

225

2.0 Fig.8

4.5

6.0

time

OE to Q_n

_THL/ t_TLHoutput transition time

2.0 Fig.6

4.5

6.0

t_W

t_su

t_h

enable pulse width

HIGH

100

120

2.0 Fig.7

4.5

6.0

set-up time

D_nto LE

2.0 Fig.9

4.5

6.0

hold time

D_nto LE

−6

−2

2.0 Fig.9

4.5

6.0

December 1990

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state;

inverting

74HC/HCT563

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: bus driver

I_CCcategory: MSI

Note to HCT types

The value of additional quiescent supply current (∆I_CC) for a unit load of 1 is given in the family specifications.

To determine ∆I_CCper input, multiply this value by the unit load coefficient shown in the table below.

INPUT

UNIT LOAD COEFFICIENT

D_n

0.35

0.65

1.25

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HCT

SYMBOL PARAMETER

UNIT

V_CC

+25

−40 to +85 −40 to +125

WAVEFORMS

(V)

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

D_nto Q_n

4.5 Fig.6

4.5 Fig.7

4.5 Fig.8

4.5 Fig.6

4.5 Fig.7

4.5 Fig.9

t_PHL/ t_PLHpropagation delay

LE to Q_n

_PZH/ t_PZL3-state output enable

time OE to Q_n

t_PHZ/ t_PLZ3-state output disable

time OE to Q_n

t_THL/ t_TLHoutput transition time

t_W

t_su

t_h

enable pulse width

HIGH

set-up time

D_nto LE

hold time

D_nto LE

−1

December 1990

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state;

inverting

74HC/HCT563

AC WAVEFORMS

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.7 Waveforms showing the latch enable input

(LE) pulse width, the latch enable input to

output (Q_n) propagation delays and the

output transition times.

Fig.6 Waveforms showing the data input (D_n) to

output (Q_n) propagation delays and the

output transition times.

The shaded areas indicate when the input is permitted to

change for predictable output performance.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.9 Waveforms showing the data set-up and

hold times for D_ninput to LE input

PACKAGE OUTLINES

(1) HC : V_M= 50%; V_I= GND to V_CC

See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.8 Waveforms showing the 3-state enable and

disable times.

December 1990

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