933769260602 [NXP]
F/FAST SERIES, DUAL 6-INPUT AND-OR-INVERT GATE, PDIP14, 0.300 INCH, PLASTIC, SOT-27-1, MO-001AA, DIP-14;
| 型号： | 933769260602 |
| 厂家： | 
NXP |
| 描述： | F/FAST SERIES, DUAL 6-INPUT AND-OR-INVERT GATE, PDIP14, 0.300 INCH, PLASTIC, SOT-27-1, MO-001AA, DIP-14 输入元件 光电二极管 逻辑集成电路 |
| 文件： | 总8页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F51
Dual 2-wide 2-input, 2-wise 3-input
AND-OR-invert gate
Product specification
IC15 Data Handbook
1989 Mar 03
Philips
Semiconductors
Philips Semiconductors
Product specification
Dual 2-wide 2-input, 2-wide 3-input AND-OR-invert gate
74F51
PIN CONFIGURATION
TYPICAL
PROPAGATION
DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
TYPE
D0a
D1a
D1b
D1c
D1d
1
2
3
4
5
14
V
CC
74F51
3.0ns
3.5mA
13 D0c
12 D0b
11 D0f
10 D0e
ORDERING INFORMATION
COMMERCIAL RANGE
= 5V ±10%,
V
DESCRIPTION
PKG DWG #
CC
T
amb
= 0°C to +70°C
Q1
6
7
9
8
D0d
Q0
14-pin plastic DIP
14-pin plastic SO
N74F51N
SOT27-1
GND
N74F51D
SOT108-1
SF00085
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
20µA/0.6mA
Dna, Dnb, Dnc, Dnd, Dne, Dnf Data inputs
1.0/1.0
50/33
Q0, Q1
Data outputs
1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
9
&
&
1
1
12 13
9
10 11
2
3
4
5
10
11
8
13
12
1
D0a D0b D0c D0d D0e D0f D1a D1b D1c D1d
Q0
8
Q1
6
2
3
&
&
1
6
4
5
V
= Pin 14
CC
GND = Pin 7
SF00086
SF00087
LOGIC DIAGRAM
FUNCTION TABLE FOR 3-INPUT GATES
INPUTS
OUTPUT
1
D0a
H
D0b
H
D0c
H
D0d
X
D0e
X
D0f
X
Q0
L
D0a
12
D0b
13
D0c
X
X
X
H
H
H
L
8
Q0
All other combinations
H
9
D0d
NOTES:
10
D0e
H
L
X
= High voltage level
= Low voltage level
= Don’t care
11
D0f
2
D1a
3
FUNCTION TABLE FOR 2-INPUT GATES
D1b
6
Q1
4
INPUTS
OUTPUT
D1c
5
D1d
D1a
D1b
D1c
D1d
Q1
V
= Pin 14
H
X
H
X
X
H
X
H
L
L
CC
GND = Pin 7
SF00088
All other combinations
H
NOTES:
H
L
X
= High voltage level
= Low voltage level
= Don’t care
2
March 3, 1989
853–0054 95962
Philips Semiconductors
Product specification
Dual 2-wide 2-input, 2-wide 3-input AND-OR-invert gate
74F51
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
Supply voltage
Input voltage
Input current
CC
IN
V
V
I
mA
V
IN
V
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
–0.5 to V
40
OUT
OUT
CC
I
mA
°C
°C
T
amb
0 to +70
T
stg
–65 to +150
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
4.5
NOM
MAX
V
Supply voltage
5.0
5.5
V
V
CC
IH
IL
V
V
High-level input voltage
Low-level input voltage
Input clamp current
2.0
0.8
–18
–1
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
OH
OL
20
T
amb
Operating free-air temperature range
0
+70
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
= MIN, V = MAX
UNIT
2
MIN
2.5
TYP
MAX
V
V
V
V
V
±10%V
V
V
V
V
V
CC
IL
CC
V
OH
High-level output voltage
= MIN, I = MAX
±5%V
2.7
3.4
0.30
0.30
–0.73
IH
OH
CC
= MIN, V = MAX
±10%V
0.50
0.50
–1.2
CC
IL
CC
CC
V
V
Low-level output voltage
Input clamp voltage
OL
= MIN, I = MAX
±5%V
IH
OL
= MIN, I = I
IK
IK
CC
I
Input current at maximum input
voltage
I
I
V
CC
= MAX, V = 7.0V
100
µA
I
I
I
I
High-level input current
Low-level input current
V
V
V
= MAX, V = 2.7V
20
–0.6
–150
3.0
µA
mA
mA
mA
mA
IH
CC
CC
CC
I
= MAX, V = 0.5V
IL
I
3
Short-circuit output current
= MAX
–60
OS
I
V
= GND
= 4.5V
IN
1.8
5.5
CCH
IN
I
Supply current (total)
V
CC
= MAX
CC
I
V
7.5
CCL
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
3
March 3, 1989
Philips Semiconductors
Product specification
Dual 2-wide 2-input, 2-wide 3-input AND-OR-invert gate
74F51
AC ELECTRICAL CHARACTERISTICS
LIMITS
V
= +5.0V
= +25°C
V
= +5.0V ± 10%
= 0°C to +70°C
CC
CC
TEST
SYMBOL
PARAMETER
T
amb
T
amb
UNIT
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
Dna, Dnb, Dnc, Dnd, Dne, Dnf to Qn
2.0
1.0
3.5
2.5
5.5
4.0
1.5
1.0
6.5
4.5
PLH
PHL
Waveform 1
ns
AC WAVEFORMS
Dna, Dnb, Dnc, Dnd, Dne, Dnf
V
V
M
M
t
t
PHL
PLH
V
V
M
M
Qn
SF00089
Waveform 1. Propagation Delay for Inverting Outputs
NOTE:
For all waveforms, V = 1.5V.
M
TEST CIRCUIT AND WAVEFORM
t
w
AMP (V)
V
CC
90%
90%
NEGATIVE
V
V
M
M
PULSE
10%
10%
V
V
OUT
IN
0V
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
t
t )
T
L
t
t )
TLH ( r
THL ( f
AMP (V)
0V
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
R
L
C
L
R
T
=
=
=
Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
family
V
rep. rate
t
w
t
t
THL
amplitude
3.0V
M
TLH
Termination resistance should be equal to Z
pulse generators.
of
OUT
2.5ns 2.5ns
74F
1.5V
1MHz
500ns
SF00006
4
March 3, 1989
Philips Semiconductors
Product specification
Dual 2-wide 2-input, 2-wise 3-input AND-OR-invert gate
74F51
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
5
1989 Mar 03
Philips Semiconductors
Product specification
Dual 2-wide 2-input, 2-wise 3-input AND-OR-invert gate
74F51
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
6
1989 Mar 03
Philips Semiconductors
Product specification
Dual 2-wide 2-input, 2-wise 3-input AND-OR-invert gate
74F51
NOTES
7
1989 Mar 03
Philips Semiconductors
Product specification
Dual 2-wide 2-input, 2-wise 3-input AND-OR-invert gate
74F51
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-98
9397-750-05065
Document order number:
Philips
Semiconductors
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