933794980602 [NXP]
IC F/FAST SERIES, 8-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, PDIP20, 0.300 INCH, PLASTIC, SOT-146-1, DIP-20, Arithmetic Circuit;
| 型号： | 933794980602 |
| 厂家： | 
NXP |
| 描述： | IC F/FAST SERIES, 8-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, PDIP20, 0.300 INCH, PLASTIC, SOT-146-1, DIP-20, Arithmetic Circuit 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总14页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F524
8-bit register comparator (open-collector
+ 3-State)
Product specification
IC15 Data Handbook
1990 Aug 07
Philips
Semiconductors
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
FEATURES
PIN CONFIGURATION
• 8-Bit bidirectional register with bus-oriented input-output
S0
V
1
2
3
4
5
20
19
CC
• Independent serial input-output to register
I/O0
S1
• Register bus comparator with ‘equal to’, ‘greater than’ and
I/O1
I/O2
I/O3
18 SE
‘less than’ outputs
C/SI
17
16
• Cascadable in groups of 8-bits
C/SO
• Open collector comparator outputs for AND-wired expansion
• Two’s complement or magnitude compare
I/O4
I/O5
I/O6
I/O7
GND
6
7
15 EQ
14 GT
LT
M
8
13
12
11
9
DESCRIPTION
CP
10
The 74F524 is an 8-bit bidirectional register with parallel input and
output, plus serial input and output progressing from MSB to LSB.
All data inputs, serial and parallel, are loaded by the rising edge of
the clock. The device functions are controlled by two control lines
(S0, S1) to execute shift, load, hold and read out. An 8-bit
comparator examines the data stored in the registers and on the
data bus. Three true-High, open collector outputs representing
‘register equal to bus’, ‘register greater than bus’ and ‘register less
than bus’ are provided. These outputs can be disabled to the OFF
state by the use of Status Enable (SE). A mode control has also
been provided to allow Two’s Complement as well as magnitude
compare. Linking inputs are provided for expansion to longer words.
SF00970
TYPICAL SUPPLY CURRENT
(TOTAL)
TYPE
TYPICAL f
MAX
74F524
65MHz
110mA
ORDERING INFORMATION
COMMERCIAL
RANGE
= 5V ±10%,
DESCRIPTION
PKG DWG #
V
CC
T
amb
= 0°C to +70°C
20-pin plastic DIP
20-pin plastic SOL
N74F524N
SOT146-1
SOT163-1
N74F524D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
PINS
DESCRIPTION
I/On
S0, S1
C/SI
CP
Parallel data inputs
Mode select inputs
3.5/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
150/40
50/33
70µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
3.0mA/24mA
1.0mA/20mA
OC/20mA
Status priority or serial data input
Clock pulse input (active rising edge)
Status enable input (active Low)
Compare mode select input
SE
M
I/On
C/SO
LT
3-state parallel data outputs
Status priority or serial data output
Register less than bus output
Register equal to bus output
OC/33
OC/33
OC/33
EQ
OC/20mA
GT
Register greater than bus output
OC/20mA
NOTE:
One (1.0) FAST Unit Load (U.L.) is defined as 20µA in the High state and 0.6mA in the Low state.
OC=Open Collector
2
1990 Aug 07
853–0373 00135
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
LOGIC SYMBOL for 74F456
SELECT FUNCTION TABLE
S0
S1
OPERATION
12
18
L
L
HOLD–Retains data in shift register
L
H
L
READ–Read contents in register onto data bus
M
SE
17
1
C/SI
S0
C/SO
LT
16
13
14
15
H
SHIFT–Allows serial shifting on next rising clock
edge
S1
GT
19
11
H
H
LOAD–Load data on bus into register
CP
EQ
H = High voltage level
= Low voltage level
L
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
One port of an 8-bit comparator is attached to the data bus while the
other port is tied to the outputs of the internal register. Three
active-OFF Open Collector outputs indicate whether the contents
held in the shift register are ‘greater than’ (GT). ‘less than’ (LT), or
‘equal to’ (EQ) the data on the input bus. A High signal on the Status
Enable (SE) input disables these outputs to the OFF state. A mode
control (M) input allows selection between a straightforward
magnitude compare or a comparison between Two’s complement
numbers.
2
3
4
5
6
7
8
9
V
GND
=
=
Pin 20
Pin 10
CC
SF00971
LOGIC SYMBOL (IEEE/IEC) for 74F456
COMP
1
0=HOLD
1=READ
2=SHIFT
3=LOAD
0
1
NUMBER REPRESENTATION SELECT TABLE
0
3
M
19
M
OPERATION
11
12
C4/2/4
L
Magnitude compare
Two’s Complement compare
M5 MAGNITUDE
16
2D
M6 TWO’s COMPLEMENT
H
17
18
&
H = High voltage level
= Low voltage level
G7
L
13
14
15
2
3, 4D
1,5,6,7>I/O
1,5,6,7<I/O
For ‘greater than’ or ‘less than’ detection, the C/SI input must be
held High, as indicated in the Function Table. The internal logic is
arranged such that a Low signal on the C/SI input places the
‘greater than’ and ‘less than’ outputs in their off state. (Note that this
off state serves also as the active state when C/SI is High. It is
intended for use in expansion to word lengths greater than 8 bits
using multiple 74S524s as explained in the next 3 paragraphs.) The
C/SO output will be forced High if the ‘equal to’ status condition
exists; otherwise, C/SO will be held Low.
3
4
5
6
1,5,6,7=I/O
7
8
9
Word length expansion (in groups of 8 bits) can be achieved by
connecting the C/SO output of the more significant byte to the C/SI
input of the next less significant byte and also to its own SE input
(see Application Figure 1). The CS/I input of the most significant
device is held High while the SE input of the least significant device
is held Low. The corresponding status outputs are AND-wired
together. In the case of two’s complement number compare, only the
Mode input to the most significant device should be High. the Mode
inputs to all other cascaded devices are held Low.
SF00972
FUNCTIONAL DESCRIPTION
The 74F524 contains eight D-type flip-flops connected as a shift
register with provision for either parallel or serial loading. Parallel
data may be read from or loaded into the registers via the data bus
I/O0–I/O7. Serial data is loaded into the register from the C/SI input
and may be shifted through the register and out through the C/SO
output. Both parallel and serial data entry occurs on the rising edge
of the clock (CP). The operation of the shift register is controlled by
two signals, S0 and S1, according to the Select Function Table. The
3-State parallel output buffers are enabled only in the READ mode.
Suppose that an inequality condition is detected in the most
significant device. Assuming that the byte stored in the register is
greater than the byte on the data bus, then the EQ and LT outputs
will be pulled Low, whereas the GT output will float High. Also, the
3
1990 Aug 07
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
CS/O output of the most significant device will be forced Low,
disabling the subsequent devices but enabling its own status
outputs. The corrected status condition is thus indicated. The same
applies if the register byte is less than the data byte, only in this
case the EQ and GT outputs go Low, whereas the LT output floats
High.
device and disables its own status outputs. In this way, the status
output proximity is handed down to the next less significant device
which now effectively becomes the most significant byte. The worst
case propagation delay for a compare operation involving ‘n’
cascaded 74F524s will be when an equality condition is detected in
all but the least significant byte. In this case, the status priority has
to ripple all the way down the chain before the correct status output
is established. Typically, this will take 35+6(n–2) ns.
If an equality condition is detected in the most significant device, its
C/SO output is forced High. This enables the next less significant
APPLICATION
V
CC
GREATER THAN
EQUAL TO
LESS THAN
H = TWO’s COMPLEMENT
L
L
L = MAGNITUDE
M
GT
EQ
LT
M
GT
EQ
LT
M
GT
EQ
LT
SE
C/SO
SE
C/SO
SE
C/SO
H
C/SI
C/SI
C/SI
L
S0
S1
I/O
S0
S1
I/O
S0
S1
I/O
RD
WR
MSB
8
8
LSB
8
SF01012
Figure 1. Cascading 74F524s for Comparing Longer Words
FUNCTION TABLE
INPUTS
S1
OUTPUTS
OPERATING MODE
SE
H
H
H
H
H
H
H
L
C/SI
H
L
S0
L
Data comparison
EQ
H
H
H
H
H
H
H
L
GT
H
H
H
H
H
H
H
H
H
H
H
L
LT
H
H
H
H
H
H
H
H
H
H
L
C/SO
L
L
X
(1)
L
Hold
Shift
L
X
X
H
L
X
Q0
(1)
L
H
L
L
H
H
H
H
X
Read
L
X
H
L
H
X
(1)
L
Load
H
X
2
2
2
2
2
2
2
2
2
2
2
2
L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
OA–OH > I/O0–I/O7
OA–OH = I/O0–I/O7
OA–OH < I/O0–I/O7
OA–OH > I/O0–I/O7
OA–OH = I/O0–I/O7
OA–OH < I/O0–I/O7
L
Compare
(GT=CT=off)
L
L
H
L
L
L
L
L
L
H
H
H
L
L
Compare
(GT=CT=on)
L
H
L
L
H
L
L
L
H
(1) = High if I/On=Dn, otherwise Low
= Must meet setup and hold time requirements
H = High voltage level
2
L
X
= Low voltage level
= Don’t care
4
1990 Aug 07
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
LOGIC DIAGRAM
1
S0
19
S1
16
C/SO
18
SE
17
C/SI
15
EQ
Q
Q
CP
D
2
3
4
I/O0
I/O1
Q
Q
CP
D
Q
Q
CP
D
I/O2
I/O3
I/O4
I/O5
14
GT
Q
Q
CP
D
5
6
Q
Q
CP
D
Q
Q
CP
D
7
Q
Q
CP
D
8
9
I/O6
I/O7
13
LT
Q
Q
CP
D
11
12
CP
M
V
=
=
Pin 20
Pin 10
CC
GND
SF00973
5
1990 Aug 07
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
Supply voltage
Input voltage
Input current
CC
IN
V
V
I
mA
V
IN
V
OUT
Voltage applied to output in High output state
–0.5 to +V
CC
All except I/O
I/O only
40
48
mA
mA
°C
°C
I
Current applied to output in Low output state
OUT
T
Operating free-air temperature range
Storage temperature range
0 to +70
amb
T
–65 to +150
stg
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
4.5
NOM
MAX
V
Supply voltage
5.0
5.5
V
V
CC
IH
IL
V
V
High-level input voltage
Low-level input voltage
Input clamp current
High-level output voltage
2.0
0.8
–18
4.5
–3
V
I
mA
V
IK
V
OH
LT, EQ, GT only
Not LT, EQ, GT, C/SO
C/SO only
mA
mA
mA
mA
°C
I
High-level output current
OH
–1
All except I/O
I/O only
20
I
Low-level output current
OL
24
T
amb
Operating free-air temperature range
0
70
6
1990 Aug 07
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
NO TAG
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
2
MIN
TYP
MAX
250
LT, EQ, GT
only
V
V
= MIN, V = MAX,
CC
IH
IL
I
High-level output current
µA
OH
= MIN, V = MAX
OH
C/SO only
±10%V
±10%V
2.5
2.4
2.7
V
V
V
V
CC
CC
CC
V
V
V
= MIN,
= MAX,
= MIN
CC
IL
V
OH
High-level output voltage
I
=MAX
OH
I/On only
IH
±5%V
3.4
0.35
0.35
–0.73
V
V
V
= MIN,
= MAX,
= MIN
±10%V
±5%V
0.50
0.50
CC
IL
CC
V
V
Low-level output voltage
Input clamp voltage
I
OL
= MAX
OL
V
IH
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= MIN, I = I
IK
–1.2
1
V
IK
I
I/On
= MAX, V = 5.5V
mA
µA
µA
mA
I
Input current at maximum
input voltage
I
I
Except I/On
= MAX, V = 7.0V
100
20
I
I
I
High-level input current
Low-level input current
= MAX, V = 2.7V
I
IH
Except I/On
I/On only
= MAX, V = 0.5V
–0.6
IL
I
Off-state output current
High-level voltage applied
I
V
= MAX, V = 2.7V
70
µA
OZH
OZL
CC
CC
O
Off-state output current
Low-level voltage applied
I
V
= MAX, V = 0.5V
–0.6
mA
O
Short-circuit output
current
Except LT,
EQ, GT
I
I
V
V
= MAX
= MAX
–60
–150
150
mA
mA
OS
CC
3
Supply current (total)
110
CC
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
7
1990 Aug 07
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
AC ELECTRICAL CHARACTERISTICS
LIMITS
V
amb
= +5V
= +25°C
V
amb
= +5V ± 10%
= 0°C to +70°C
CC
CC
TEST
CONDITION
T
T
SYMBOL
PARAMETER
UNIT
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 4
Waveform 2
50
65
45
MHz
ns
MAX
t
t
Propagation delay
I/On to EQ
9.0
4.5
11.5
7.5
17.0
11.0
9.0
4.5
18.0
12.0
PLH
PHL
t
t
Propagation delay
I/On to GT
8.5
6.5
11.0
9.5
17.0
15.5
8.5
6.5
18.0
16.5
PLH
PHL
Waveform 2
Waveform 2
Waveform 2
Waveform 4
Waveform 4
Waveform 4
Waveform 4
Waveform 4
Waveform 1
Waveform 1
Waveform 2
Waveform 2
Waveform 2
Waveform 2
Waveform 2
Waveform 2
Waveform 2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
Propagation delay
I/On to LT
8.0
6.0
11.0
10.5
17.0
14.0
8.0
6.0
18.0
15.0
PLH
PHL
t
t
Propagation delay
I/On to C/SO
7.0
6.5
13.0
9.0
16.0
14.0
7.0
5.5
17.0
15.0
PLH
PHL
t
t
Propagation delay
CP to EQ
11.0
4.0
17.0
8.0
22.0
14.0
10.0
4.0
23.0
15.0
PLH
PHL
t
t
Propagation delay
CP to GT
11.0
10.0
16.0
16.5
20.0
21.0
10.0
10.0
21.0
22.0
PLH
PHL
t
t
Propagation delay
CP to LT
11.0
8.0
16.0
14.0
23.0
18.0
10.0
8.0
24.0
19.0
PHL
PLH
Propagation delay
CP to C/SO (Load)
t
10.0
16.0
20.0
10.0
21.0
PLH
t
t
Propagation delay
CP to C/SO (Serial shift)
5.0
4.5
10.0
9.0
13.0
11.5
5.0
4.5
14.0
12.5
PLH
PHL
t
t
Propagation delay
C/SI to GT
8.0
3.0
10.5
4.5
16.0
8.5
9.0
2.5
17.0
9.5
PLH
PHL
t
t
Propagation delay
C/SI to LT
8.0
3.0
10.5
6.0
17.0
8.5
8.0
2.5
18.0
9.5
PLH
PHL
t
t
Propagation delay
Sn to C/SO
6.5
5.5
8.0
10.0
14.5
17.0
6.5
5.5
15.5
18.0
PLH
PHL
t
t
Propagation delay
SE to EQ
3.5
2.5
7.0
4.5
10.5
8.0
3.5
2.5
11.5
9.0
PLH
PHL
t
t
Propagation delay
SE to GT
6.0
3.5
8.0
5.0
13.0
8.0
6.0
3.0
14.0
9.0
PLH
PHL
t
t
Propagation delay
SE to LT
5.0
3.5
8.0
5.5
12.0
8.0
5.0
3.0
13.0
9.0
PLH
PHL
t
t
Propagation delay
C/SI to C/SO
4.0
4.0
7.0
7.0
11.0
11.0
4.0
4.0
12.0
12.0
PLH
PHL
t
t
Propagation delay
M to GT
8.0
8.0
13.0
10.0
18.0
15.5
8.0
8.0
19.0
16.5
PLH
PHL
t
t
Propagation delay
M to LT
10.0
6.0
15.0
8.0
20.0
12.0
10.0
5.0
21.0
13.0
PLH
PHL
Waveform
NO TAG
Waveform
NO TAG
t
t
Output Enable time
Sn to I/On
4.5
5.5
7.0
9.0
13.0
15.0
4.5
5.5
14.0
16.0
PZH
PZL
ns
ns
Waveform
NO TAG
Waveform
NO TAG
t
t
Output Disable time
Sn to I/On
3.0
4.5
5.0
8.0
12.0
12.5
2.0
4.5
13.0
13.5
PHZ
PLZ
8
1990 Aug 07
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
AC SETUP REQUIREMENTS
LIMITS
T
amb
= +25°C
T
amb
= 0°C to +70°C
SYMBOL
PARAMETER
TEST
V
CC
= +5.0V
V
CC
= +5.0V ± 10%
UNIT
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t (H)
t (L)
s
Setup time, High or Low
I/On to CP
6.0
6.0
6.0
6.0
s
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 4
ns
ns
ns
ns
ns
ns
ns
t (H)
Hold time, High or Low
I/On to CP
0
0
0
0
h
t (L)
h
t (H)
Setup time, High or Low
S0, S1 to CP
13.5
10.0
15.0
10.0
s
t (L)
s
t (H)
Hold time, High or Low
S0, S1 to CP
0
0
0
0
h
t (L)
h
t (H)
Setup time, High or Low
C/SI to CP
7.0
7.0
7.0
7.0
s
t (L)
s
t (H)
Hold time, High or Low
C/SI to CP
0
0
0
0
h
t (L)
h
t (H)
CP pulse width,
High or Low
5.0
10.0
5.0
10.0
w
t (L)
w
AC WAVEFORMS
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
SE, C/SI, M
I/On, Sn
V
V
M
M
t
C/SI
V
V
M
t
M
t
t
PHL
PLH
PHL
PLH
EQ, C/SO
GT, LT
V
V
GT, LT
M
M
V
V
M
M
SF00974
SF00975
Waveform 1. Propagation Delay for Inverting Outputs
Waveform 2. Propagation Delay for Non-Inverting Outputs
1/f
MAX
V
V
M
CP
C/SI,
I/On,
Sn
V
V
V
V
M
M
M
M
M
t (L)
W
t (H)
W
t (L)
t (L)
h
t (H)
s
t (H)
h
s
t
t
PLH
PHL
CP
V
M
V
M
EQ, C/SO,
GT, LT
V
V
M
M
SF00976
SF00977
Waveform 3. Setup and Hold Times
Waveform 4. Propagation Delay, Clock to Output,
Clock Pulse Width, and Maximum Clock Frequency
9
1990 Aug 07
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
AC WAVEFORMS (Continued)
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
V
V
M
M
Sn
V
V
M
Sn
M
t
t
PLZ
V
-0.3V
0V
PZL
OH
t
t
PHZ
PZH
I/On
V
M
I/On
V
M
V
+0.3V
OL
SF00978
SF00979
Waveform 6. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
Waveform 5. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
TEST CIRCUIT AND WAVEFORMS
V
CC
t
w
AMP (V)
0V
7.0V
90%
90%
NEGATIVE
PULSE
V
V
M
R
L
M
V
V
OUT
IN
10%
10%
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
T
L
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
0V
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
and Open Collector Outputs
10%
10%
t
w
SWITCH POSITION
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ, PZL
Open Collector
All other
DEFINITIONS:
R
L
C
L
R
T
=
=
=
Load resistor;
INPUT PULSE REQUIREMENTS
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
pulse generators.
family
V
M
rep. rate
t
w
t
t
THL
amplitude
TLH
of
OUT
2.5ns
2.5ns
74F
3.0V
1.5V
1MHz
500ns
SF00980
10
1990 Aug 07
Philips Semiconductors
Product specification
8-bit register comparator (open-collector + 3-State)
74F524
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
11
1990 Aug 07
Philips Semiconductors
Product specification
8-bit register comparator (open-collector + 3-State)
74F524
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
12
1990 Aug 07
Philips Semiconductors
Product specification
8-bit register comparator (open-collector + 3-State)
74F524
NOTES
13
1990 Aug 07
Philips Semiconductors
Product specification
8-bit register comparator (open-collector + 3-State)
74F524
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-98
9397-750-05131
Document order number:
Philips
Semiconductors
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