933823910005 [NXP]

IC HC/UH SERIES, TRIPLE 3-INPUT OR GATE, UUC, CHIP ON WAFER, Gate;
933823910005
型号: 933823910005
厂家: NXP    NXP
描述:

IC HC/UH SERIES, TRIPLE 3-INPUT OR GATE, UUC, CHIP ON WAFER, Gate

栅 输入元件 逻辑集成电路
文件: 总5页 (文件大小:32K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
INTEGRATED CIRCUITS  
DATA SHEET  
For a complete data sheet, please also download:  
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications  
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information  
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines  
74HC/HCT4075  
Triple 3-input OR gate  
December 1990  
Product specification  
File under Integrated Circuits, IC06  
Philips Semiconductors  
Product specification  
Triple 3-input OR gate  
74HC/HCT4075  
FEATURES  
GENERAL DESCRIPTION  
Output capability: standard  
ICC category: SSI  
The 74HC/HCT4075 are high-speed Si-gate CMOS  
devices and are pin compatible with the “4075” of the  
“4000B” series. They are specified in compliance with  
JEDEC standard no. 7A.  
The 74HC/HCT4075 provide the 3-input OR function.  
QUICK REFERENCE DATA  
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns  
TYPICAL  
SYMBOL  
tPHL/ tPLH  
PARAMETER  
CONDITIONS  
UNIT  
ns  
HC  
HCT  
propagation delay nA, nB, nC to nY  
input capacitance  
CL = 15 pF; VCC = 5 V  
8
10  
CI  
3.5  
28  
3.5  
32  
pF  
pF  
CPD  
power dissipation capacitance per gate notes 1 and 2  
Notes  
1. CPD is used to determine the dynamic power dissipation (PD in µW):  
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:  
fi = input frequency in MHz  
fo = output frequency in MHz  
(CL × VCC2 × fo) = sum of outputs  
CL = output load capacitance in pF  
VCC = supply voltage in V  
2. For HC the condition is VI = GND to VCC  
For HCT the condition is VI = GND to VCC 1.5 V  
ORDERING INFORMATION  
See “74HC/HCT/HCU/HCMOS Logic Package Information”.  
December 1990  
2
Philips Semiconductors  
Product specification  
Triple 3-input OR gate  
74HC/HCT4075  
PIN DESCRIPTION  
PIN NO.  
3, 1, 11  
4, 2, 12  
5, 8, 13  
6, 9, 10  
7
SYMBOL  
1A to 3A  
1B to 3B  
1C to 3C  
1Y to 3Y  
GND  
NAME AND FUNCTION  
data inputs  
data inputs  
data inputs  
data outputs  
ground (0 V)  
14  
VCC  
positive supply voltage  
Fig.1 Pin configuration.  
Fig.2 Logic symbol.  
Fig.3 IEC logic symbol.  
FUNCTION TABLE  
INPUTS  
nB  
OUTPUT  
nY  
nA  
nC  
L
H
X
X
L
X
H
X
L
X
X
H
L
H
H
H
Notes  
1. H = HIGH voltage level  
L = LOW voltage level  
X = don’t care  
Fig.4 Functional diagram.  
Fig.5 Logic diagram (one gate).  
December 1990  
3
Philips Semiconductors  
Product specification  
Triple 3-input OR gate  
74HC/HCT4075  
DC CHARACTERISTICS FOR 74HC  
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.  
Output capability: standard  
ICC category: SSI  
AC CHARACTERISTICS FOR 74HC  
GND = 0 V; tr = tf = 6 ns; CL = 50 pF  
Tamb (°C)  
TEST CONDITIONS  
74HC  
SYMBOL PARAMETER  
UNIT  
WAVEFORMS  
VCC  
(V)  
+25  
40 to +85 40 to +125  
min. typ. max. min. max. min. max.  
tPHL/ tPLH propagation delay  
nA, nB, nC to nY  
28  
10  
8
100  
20  
17  
125  
25  
21  
150  
30  
26  
ns  
ns  
2.0 Fig.6  
4.5  
6.0  
t
THL/ tTLH output transition time  
19  
7
6
75  
15  
13  
95  
19  
16  
110  
22  
19  
2.0 Fig.6  
4.5  
6.0  
December 1990  
4
Philips Semiconductors  
Product specification  
Triple 3-input OR gate  
74HC/HCT4075  
DC CHARACTERISTICS FOR 74HCT  
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.  
Output capability: standard  
ICC category: SSI  
Note to HCT types  
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications.  
To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.  
INPUT  
UNIT LOAD COEFFICIENT  
nA, nB, nC  
1.50  
AC CHARACTERISTICS FOR 74HCT  
GND = 0 V; tr = tf = 6 ns; CL = 50 pF  
Tamb (°C)  
TEST CONDITIONS  
WAVEFORMS  
74HCT  
SYMBOL PARAMETER  
UNIT  
VCC  
+25  
40 to +85 40 to +125  
(V)  
min. typ. max. min. max. min. max.  
tPHL/ tPLH propagation delay  
nA, nB, nC to nY  
12  
24  
30  
36  
ns  
ns  
4.5 Fig.6  
4.5 Fig.6  
t
THL/ tTLH output transition time  
7
15  
19  
22  
AC WAVEFORMS  
(1) HC : VM = 50%; VI = GND to VCC  
.
HCT: VM = 1.3 V; VI = GND to 3 V.  
Fig.6 Waveforms showing the input (nA, nB, nC) to output (nY) propagation delays and the output transition times.  
PACKAGE OUTLINES  
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.  
December 1990  
5

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