933835630005 [NXP]

IC 64 X 9 OTHER FIFO, 520 ns, UUC, DIE, FIFO;


型号：	933835630005
厂家：	NXP
描述：	IC 64 X 9 OTHER FIFO, 520 ns, UUC, DIE, FIFO 先进先出芯片
文件：	总22页 (文件大小：166K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT7030

9-bit x 64-word FIFO register;

3-state

December 1990

Product speciﬁcation

File under Integrated Circuits, IC06

Philips Semiconductors

Product speciﬁcation

9-bit x 64-word FIFO register; 3-state

74HC/HCT7030

FEATURES

Data outputs (Q₀to Q₈)

• Synchronous or asynchronous operation

• 3-state outputs

As there is no weighting of the outputs, any output can be

assigned as the MSB. The size of the FIFO memory can

be reduced from the 9 × 64 configuration as described for

data inputs. In a reduced format, the unused data output

pins must be left open circuit.

• Master-reset input to clear control functions

• 33 MHz (typ.) shift-in, shift-out rates with or without flags

• Very low power consumption

Master-reset (MR)

• Cascadable to 25 MHz (typ.)

When MR is LOW, the control functions within the FIFO

are cleared, and data content is declared invalid. The

data-in-ready (DIR) flag is set HIGH and the

data-out-ready (DOR) flag is set LOW. The output stage

remains in the state of the last word that was shifted out,

or in the random state existing at power-up.

• Readily expandable in word and bit dimensions

• Pinning arranged for easy board layout: input pins

directly opposite output pins

• Output capability: standard

• I_CCcategory: LSI

Status flag outputs (DIR, DOR)

GENERAL DESCRIPTION

Indication of the status of the FIFO is given by two status

flags, data-in-ready (DIR) and data-out-ready (DOR):

The 74HC/HCT7030 are high-speed Si-gate CMOS

devices specified in compliance with JEDEC standard

no. 7A.

DIR = HIGH indicates the input stage is empty and

ready to accept valid data

The 74HC/HCT7030 is an expandable, First-In First-Out

(FIFO) memory organized as 64 words by 9 bits. A 33 MHz

data-rate makes it ideal for high-speed applications. Even

at high frequencies, the I_CCdynamic is very low

DIR = LOW indicates that the FIFO is full or that a

previous shift-in operation is not complete

(busy)

(f_max= 18 MHz; V_CC= 5 V produces a dynamic I_CCof

80 mA). If the device is not continuously operating at f_max

then I_CCwill decrease proportionally.

DOR = HIGH assures valid data is present at the

outputs Q₀to Q₈(does not indicate that new

data is awaiting transfer into the output stage)

With separate controls for shift-in (SI) and shift-out (SO),

reading and writing operations are completely

DOR = LOW indicates the output stage is busy or

there is no valid data

independent, allowing synchronous and asynchronous

data transfers. Additional controls include a master-reset

input (MR) and an output enable input (OE). Flags for

data-in-ready (DIR) and data-out-ready (DOR) indicate the

status of the device.

Shift-in control (SI)

Data is loaded into the input stage on a LOW-to-HIGH

transition of SI. A HIGH-to-LOW transition triggers an

automatic data transfer process (ripple through). If SI is

held HIGH during reset, data will be loaded at the rising

edge of the MR signal.

Devices can be interconnected easily to expand word and

bit dimensions. All output pins are directly opposite the

corresponding input pins thus simplifying board layout in

expanded applications.

Shift-out control (SO)

A LOW-to-HIGH transition of SO causes the DOR flags to

go LOW. A HIGH-to-LOW transition of SO causes

upstream data to move into the output stage, and empty

locations to move towards the input stage (bubble-up).

INPUTS AND OUTPUTS

Data inputs (D₀to D₈)

As there is no weighting of the inputs, any input can be

assigned as the MSB. The size of the FIFO memory can

be reduced from the 9 × 64 configuration, i.e. 8 × 64,

7 × 64, down to 1 × 64, by tying unused data input pins to

Output enable (OE)

The outputs Q₀to Q₈are enabled when OE = LOW. When

OE = HIGH the outputs are in the high impedance

OFF-state.

_CCor GND.

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit x 64-word FIFO register; 3-state

74HC/HCT7030

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C; t_r= t_f= 6 ns

TYPICAL

UNIT

SYMBOL

_PHL/t_PLH

PARAMETER

CONDITIONS

HCT

propagation delay

MR to DIR and DOR

SO to Q_n

C_L= 15 pF; V_CC= 5 V

f_max

maximum clock frequency

SI and SO

MHz

C_I

input capacitance

3.5

C_P

power dissipation capacitance per package notes 1 and 2

660

Notes

1. C_PDis used to determine the dynamic power dissipation (P_Din µW):

P_D= C_PD× V_CC²× f_i+ ∑ (C_L× V_CC²× f_o) where:

f_i= input frequency in MHz

f_o= output frequency in MHz

∑ (C_L× V_CC²× f_o) = sum of outputs

C_L= output load capacitance in pF

V_CC= supply voltage in V

2. For HC the condition is V_I= GND to V_CC

For HCT the condition is V_I= GND to V_CC− 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit x 64-word FIFO register; 3-state

74HC/HCT7030

PIN DESCRIPTION

PIN NO.

SYMBOL

GND

DIR

NAME AND FUNCTION

ground (0 V)

1, 2, 14

data-in-ready output

shift-in input (LOW-to-HIGH, edge-triggered)

parallel data inputs

5, 6, 7, 8, 9, 10, 11, 12, 13

D₀to D₈

output enable input (active LOW)

3-state parallel data outputs

24, 23, 22, 21, 20, 19, 18, 17, 16

Q₀to Q₈

DOR

data-out-ready output

shift-out input (HIGH-to-LOW, edge-triggered)

asynchronous master-reset input (active LOW)

positive supply voltage

V_CC

Note

1. Pin 14 must be connected to GND. Pins 1 and 2 can be left floating or connected to GND, however it is not allowed

to let current flow in either direction between pins 1, 2 and 14.

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit x 64-word FIFO register; 3-state

74HC/HCT7030

Fig.4 Functional diagram.

APPLICATIONS

• High-speed disc or tape controller

• Video timebase correction

• A/D output buffers

• Voice synthesis

• Input/output formatter for digital filters and FFTs

• Bit-rate smoothing

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit x 64-word FIFO register; 3-state

74HC/HCT7030

With the FIFO empty, the SO input can be held HIGH until

the SI control input is used. Following an SI pulse, data

moves through the FIFO to the output stage, resulting in

the DOR flag pulsing HIGH and a shift-out of data

occurring. The SO control must be made LOW before

additional data can be shifted out (see Fig.10).

FUNCTIONAL DESCRIPTION

Data input

Following power-up, the master-reset (MR) input is pulsed

LOW to clear the FIFO memory (see Fig.8). The

data-in-ready flag (DIR = HIGH) indicates that the FIFO

input stage is empty and ready to receive data. When DIR

is valid (HIGH), data present at D₀to D₈can be shifted-in

using the SI control input. With SI = HIGH, data is shifted

into the input stage and a busy indication is given by DIR

going LOW.

High-speed burst mode

If it is assumed that the shift-in/shift-out pulses are not

applied until the respective status flags are valid, it follows

that the shift-in/shift-out rates are determined by the status

flags. However, without the status flags a high-speed burst

mode can be implemented. In this mode, the

burst-in/burst-out rates are determined by the pulse widths

of the shift-in/shift-out inputs and burst rates of 35 MHz can

be obtained. Shift pulses can be applied without regard to

the status flags but shift-in pulses that would overflow the

storage capacity of the FIFO are not allowed (see Figs 11

and 12).

The data remains at the first location in the FIFO until SI is

set to LOW. With SI = LOW data moves through the FIFO

to the output stage, or to the last empty location. If the

FIFO is not full after the SI pulse, DIR again becomes valid

(HIGH) to indicate that space is available in the FIFO. The

DIR flag remains LOW if the FIFO is full (see Fig.6). The

SI pulse must be made LOW in order to complete the

shift-in process.

With the FIFO full, SI can be held HIGH until a shift-out

(SO) pulse occurs. Then, following a shift-out of data, an

empty location appears at the FIFO input and DIR goes

HIGH to allow the next data to be shifted-in. This remains

at the first FIFO location until SI again goes LOW (see

Fig.7).

Expanded format

With the addition of a logic gate, the FIFO is easily

expanded to increase word length (see Fig.17). The basic

operation and timing are identical to a single FIFO, with the

exception of an additional gate delay on the flag outputs. If

during application, the following occurs:

Data transfer

• SI is held HIGH when the FIFO is empty, some

additional logic is required to produce a composite DIR

pulse (see Figs 7 and 18).

After data has been transferred from the input stage of the

FIFO following SI = LOW, data moves through the FIFO

asynchronously and is stacked at the output end of the

FIFO as data moves through the device.

• SO is held HIGH when the FIFO is full, some additional

logic is required to produce a composite DOR pulse (see

Figs 10 and 18).

Due to the part-to-part spread of the ripple through time,

the flag signals of FIFO_Aand FIFO_Bwill not always

coincide and the AND-gate will not produce a composite

flag signal. The solution is given in Fig.18.

Data output

The data-out-ready flag (DOR = HIGH) indicates that

there is valid data at the output (Q₀to Q₈). The initial

master-reset at power-on (MR = LOW) sets DOR to LOW

(see Fig.8). After MR = HIGH, data shifted into the FIFO

moves through to the output stage causing DOR to go

HIGH. As the DOR flag goes HIGH, data can be

shifted-out using the SO control input. With SO = HIGH,

data in the output stage is shifted out and a busy indication

is given by DOR going LOW. When SO is made LOW,

data moves through the FIFO to fill the output stage and an

empty location appears at the input stage. When the

output stage is filled DOR goes HIGH, but if the last of the

valid data has been shifted out leaving the FIFO empty the

DOR flag remains LOW (see Fig.9). With the FIFO empty,

the last word that was shifted-out is latched at the output

Q₀to Q₈.

The “7030” is easily cascaded to increase the word

capacity and no external components are needed. In the

cascaded configuration, all necessary communications

and timing are performed by the FIFOs. The

intercommunication speed is determined by the minimum

flag pulse widths and the flag delays. The data rate of

cascaded devices is typically 25 MHz. Word-capacity can

be expanded to and beyond 128-words × 9-bits (see

Fig.19).

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit x 64-word FIFO register; 3-state

74HC/HCT7030

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit x 64-word FIFO register; 3-state

74HC/HCT7030

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standard

I_CCcategory: LSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HC

SYMBOL PARAMETER

UNIT

V_CC

+25

−40 to +85 −40 to +125

WAVEFORMS

(V)

min. typ. max. min. max. min. max.

t_PHL/ t_PLHpropagation delay

MR to DIR, DOR

210

265

315

µs

2.0

4.5

6.0

Fig.8

_PHL/ t_PLHpropagation delay

SI to DIR

235

295

355

2.0

4.5

6.0

Fig.6

_PHL/ t_PLHpropagation delay

SO to DOR

102 315

395

475

2.0

4.5

6.0

Fig.9

_PHL/ t_PLHpropagation delay

DOR to Q_n

2.0

4.5

6.0

Fig.10

Fig.14

Fig.10

Fig.7

_PHL/ t_PLHpropagation delay

SO to Q_n

113 345

430

520

104

2.0

4.5

6.0

t_PLH

propagation delay/

ripple through delay

SI to DOR

2.5

0.9

0.7

8.0

1.6

1.3

2.0

1.6

2.4

1.9

2.0

4.5

6.0

t_PLH

propagation delay/

bubble-up delay

SO to DIR

3.3

1.2

1.0

10.0

2.0

1.6

2.5

2.0

3.0

2.4

2.0

4.5

6.0

_PZH/ t_PZL3-state output enable

175

220

265

2.0

4.5

6.0

Fig.16

Fig.14

Fig.6

OE to Q_n

_PHZ/ t_PLZ3-state output disable

OE to Q_n

150

190

225

2.0

4.5

6.0

t_THL/ t_TLHoutput transition time

110

2.0

4.5

6.0

t_W

SI pulse width

HIGH or LOW

2.0

4.5

6.0

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit x 64-word FIFO register; 3-state

74HC/HCT7030

T_amb(°C)

TEST CONDITIONS

74HC

SYMBOL PARAMETER

UNIT

V_CC

+25

−40 to +85 −40 to +125

WAVEFORMS

(V)

min. typ. max. min. max. min. max.

t_W

SO pulse width

HIGH or LOW

100 33

125

150

2.0

4.5

6.0

Fig.9

t_W

DIR pulse width

HIGH

145

180

220

2.0

4.5

6.0

Fig.7

t_W

DOR pulse width

HIGH

145

180

220

2.0

4.5

6.0

Fig.10

t_W

MR pulse width

LOW

105

2.0

4.5

6.0

Fig.8

t_rem

removal time

MR to SI

100

120

2.0

4.5

6.0

Fig.15

t_su

set-up time

D_nto SI

−35 −36

−45

−9

−8

−55

−11

−9

2.0

4.5

6.0

Fig.13

−7

−6

−13

−10

t_h

hold time

D_nto SI

135 44

170

205

2.0

4.5

6.0

Fig.13

f_max

maximum clock pulse

frequency

9.9

2.8

2.4

MHz 2.0

4.5

Figs 11 and 12

Figs 6 and 9

SI, SO burst mode

6.0

maximum clock pulse

frequency

9.9

2.8

2.4

MHz 2.0

4.5

SI, SO using ﬂags

6.0

maximum clock pulse

frequency

7.6

2.2

1.8

9.2

MHz 2.0

4.5

SI, SO cascaded

6.0

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit x 64-word FIFO register; 3-state

74HC/HCT7030

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standard

I_CCcategory: LSI

Note to HCT types

The value of additional quiescent supply current (∆I_CC) for a unit load of 1 is given in the family specifications.

To determine ∆I_CCper input, multiply this value by the unit load coefficient shown in the table below.

INPUT

UNIT LOAD COEFFICIENT

D_n

1.00

1.50

0.75

1.50

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HCT

SYMBOL PARAMETER

UNIT

V_CC

+25

−40 to +85 −40 to +125

WAVEFORMS

(V)

min. typ. max. min. max. min. max.

_PHL/ t_PLHpropagation delay

MR to DIR, DOR

30 51

29 49

39 67

46 78

2.0

µs

4.5

Fig.8

_PHL/ t_PLHpropagation delay

SI to DIR

Fig.6

t_PHL/ t_PLHpropagation delay

SO to DOR

101

117

Fig.9

_PHL/ t_PLHpropagation delay

SO to Q_n

Fig.14

Fig.10

_PHL/ t_PLHpropagation delay

DOR to Q_n

t_PLH

propagation delay/ripple

through delay

0.9 1.6

1.2 2.0

2.4

SI to DOR

t_PLH

propagation delay/

bubble-up delay

SO to DIR

2.5

3.0

µs

4.5

Fig.7

t_PZH/ t_PZL3-state output enable

OE to Q_n

20 35

19 35

4.5

Fig.16

Fig.14

_PHZ/ t_PLZ3-state output disable

OE to Q_n

t_THL/ t_TLHoutput transition time

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit x 64-word FIFO register; 3-state

74HC/HCT7030

T_amb(°C)

TEST CONDITIONS

74HCT

SYMBOL PARAMETER

UNIT

V_CC

(V)

+25

−40 to +85 −40 to +125

WAVEFORMS

min. typ. max. min. max. min. max.

t_W

SI pulse width

HIGH or LOW

4.5

Fig.6

t_W

SO pulse width

HIGH or LOW

Fig.9

t_W

DIR pulse width

HIGH

22 37

20 35

Fig.7

t_W

DOR pulse width

HIGH

Fig.10

Fig.8

t_W

MR pulse width

LOW

−5

−4

t_rem

t_su

t_h

removal time

MR to SI

Fig.15

Fig.13

Figs 11 and 12

set-up time

D_nto SI

−16

hold time

D_nto SI

f_max

maximum clock pulse

frequency

MHz 4.5

SI, SO burst mode

f_max

maximum clock pulse

frequency

Figs 6 and 9

SI, SO using ﬂags

f_max

maximum clock pulse

frequency

8.6

SI, SO cascaded

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit x 64-word FIFO register; 3-state

74HC/HCT7030

AC WAVEFORMS

Shifting in sequence FIFO empty to FIFO full

Notes to Fig.6

1. DIR initially HIGH; FIFO is

prepared for valid data.

2. SI set HIGH; data loaded into

input stage.

3. DIR drops LOW, input stage

“busy”.

4. SI set LOW; data from first

location “ripple through”.

5. DIR goes HIGH, status flag

indicates FIFO prepared for

additional data.

6. Repeat process to load 2nd word

through to 64th word into FIFO.

7. DIR remains LOW; with attempt

to shift into full FIFO, no data

transfer occurs.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.6 Waveforms showing the SI input to DIR output propagation

delay. The SI pulse width and SI maximum pulse frequency.

With FIFO full; SI held HIGH in anticipation of empty location

Notes to Fig.7

1. FIFO is initially full, shift-in is held

HIGH.

2. SO pulse; data in the output

stage is unloaded, “bubble-up

process of empty locations

begins”.

3. DIR HIGH; when empty location

reached input stage, flag

indicates FIFO is prepared for

data input.

4. DIR returns to LOW; FIFO is full

again.

5. SI brought LOW; necessary to

complete shift-in process, DIR

remains LOW, because FIFO is

full.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.7 Waveforms showing bubble-up delay, SO input to DIR output

and DIR output pulse width.

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit x 64-word FIFO register; 3-state

74HC/HCT7030

Master reset applied with FIFO full

Notes to Fig.8

1. DIR LOW, output ready HIGH;

assume FIFO is full.

2. MR pulse LOW; clears FIFO.

3. DIR goes HIGH; flag indicates

input prepared for valid data.

4. DOR drops LOW; flag indicates

FIFO empty.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.8 Waveforms showing the MR input to DIR, DOR output

propagation delays and the MR pulse width.

Shifting out sequence; FIFO full to FIFO empty

Notes to Fig.9

1. DOR HIGH; no data transfer in

progress, valid data is present at

output stage.

2. SO set HIGH; results in DOR

going LOW.

3. DOR drops LOW; output stage

“busy”.

4. SO is set LOW; data in the input

stage is unloaded, and new data

replaces it as empty location

“bubbles-up” to input stage.

5. DOR goes HIGH; transfer

process completed, valid data

present at output after the

specified propagation delay.

(1) HC : V_M= 50%; V_I= GND to V_CC

6. Repeat process to unload the 3rd

through to the 64th word from

FIFO.

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.9 Waveforms showing the SO input to DIR output propagation

delay. The SO pulse width and SO maximum pulse frequency.

7. DOR remains LOW; FIFO is

empty.

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit x 64-word FIFO register; 3-state

74HC/HCT7030

With FIFO empty; SO is held HIGH in anticipation

Notes to Fig.10

1. FIFO is initially empty, SO is held

HIGH.

2. SI pulse; loads data into FIFO

and initiates ripple through

process.

3. DOR flag signals the arrival of

valid data at the output stage.

4. Output transition; data arrives at

output stage after the specified

propagation delay between the

rising edge of the DOR pulse to

the Q_noutput.

5. DOR goes LOW; FIFO is empty

again.

6. SO set LOW; necessary to

complete shift-out process. DOR

remains LOW, because FIFO is

empty.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.10 Waveforms showing ripple through delay SI input to DOR output,

DOR output pulse width and propagation delay from the DOR

pulse to the Q_noutput.

Shift-in operation; high-speed burst mode

In the high-speed mode, the burst-in rate is determined by the minimum shift-in HIGH and shift-in LOW

specifications. The DIR status flag is a don’t care condition, and a shift-in pulse can be applied regardless of

the flag. A SI pulse which would overflow the storage capacity of the FIFO is ignored.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.11 Waveforms showing SI minimum pulse width and SI maximum pulse frequency, in high-speed shift-in

burst mode.

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit x 64-word FIFO register; 3-state

74HC/HCT7030

Shift-out operation; high-speed burst mode

In the high-speed mode, the burst-out rate is determined by the minimum shift-out HIGH and shift-out LOW

specifications. The DOR flag is a don’t care condition and a SO pulse can be applied without regard to the flag.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.12 Waveforms showing SO minimum pulse width and maximum pulse frequency, in high-speed shift-out

burst mode.

The shaded areas indicate when the input is permitted to change for predictable output performance.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.13 Waveforms showing hold and set-up times for D_ninput to SI input.

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit x 64-word FIFO register; 3-state

74HC/HCT7030

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.15 Waveforms showing the

MR input to SI input removal

time.

Fig.14 Waveforms showing SO input to Q_noutput

propagation delays and output transition time.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.16 Waveforms showing the 3-state enable and disable times for input OE.

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit x 64-word FIFO register; 3-state

74HC/HCT7030

APPLICATION INFORMATION

The PC74HC/HCT7030 is easily expanded to increase word length. Composite

DIR and DOR flags are formed with the addition of an AND gate. The basic

operation and timing are identical to a single FIFO, with the exception of an added

gate delay on the flags.

Fig.17 Expanded FIFO for increased word length; 64 words × 18 bits.

This circuit is only required if the SI input is constantly held HIGH, when the FIFO

is empty and the automatic shift-in cycles are started or if SO output is constantly

held HIGH, when the FIFO is full and the automatic shift-out cycles are started

(see Figs 7 and 10).

Fig.18 Expanded FIFO for increased word length.

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit x 64-word FIFO register; 3-state

74HC/HCT7030

Expanded format

Fig.19 shows two cascaded FIFOs providing a capacity of 128 words × 9 bits.

Fig.20 shows the signals on the nodes of both FIFOs after the application of a SI pulse, when both FIFOs are initially

empty. After a rippled through delay, data arrives at the output of FIFO_A. Due to SO_Abeing HIGH, a DOR pulse is

generated. The requirements of SI_Band D_nBare satisfied by the DOR_Apulse width and the timing between the rising

edge of DOR_Aand Q_nA. After a second ripple through delay, data arrives at the output of FIFO_B.

Fig.21 shows the signals on the nodes of both FIFOs after the application of a SO_Bpulse, when both FIFOs are initially

full. After a bubble-up delay a DIR_Bpulse is generated, which acts as a SO_Apulse for FIFO_A. One word is transferred

from the output of FIFO_Ato the input of FIFO_B. The requirements of the SO_Apulse for FIFO_Ais satisfied by the pulse

width of DOR_B. After a second bubble-up delay an empty space arrives at D_nA, at which time DIR_Agoes HIGH.

Fig.22 shows the waveforms at all external nodes of both FIFOs during a complete shift-in and shift-out sequence.

The PC74HC/HCT7030 is easily cascaded to increase word capacity without any

external circuitry. In cascaded format, all necessary communications are handled

by the FIFOs. Figs 17 to 19 demonstrate the intercommunication timing between

FIFO_Aand FIFO_B. Fig.22 gives an overview of pulses and timing of two cascaded

FIFOs, when shifted full and shifted empty again.

Fig.19 Cascading for increased word capacity; 128 words × 9 bits.

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit x 64-word FIFO register; 3-state

74HC/HCT7030

Notes to Fig.20

1. FIFO_Aand FIFO_Binitially empty,

SO_Aheld HIGH in anticipation of

data.

2. Load one word into FIFO_A; SI

pulse applied, results in DIR

pulse.

3. Data out _A/data in _Btransition;

valid data arrives at FIFO_Aoutput

stage after a specified delay of

the DOR flag, meeting data input

set-up requirements of FIFO_B.

4. DOR_Aand SI_Bpulse HIGH;

(ripple through delay after

SI_ALOW) data is unloaded from

FIFO_Aas a result of the data

output ready pulse, data is shifted

into FIFO_B.

5. DIR_Band SO_Ago LOW; flag

indicates input stage of FIFO_Bis

busy, shift-out of FIFO_Ais

complete.

6. DIR_Band SO_Ago HIGH

automatically; the input stage of

FIFO_Bis again able to receive

data, SO is held HIGH in

anticipation of additional data.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

7. DOR_BgoesHIGH;(ripplethrough

delay after SI_BLOW) valid data is

present one propagation delay

later at the FIFO_Boutput stage.

Fig.20 FIFO to FIFO communication; input timing under empty condition.

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit x 64-word FIFO register; 3-state

74HC/HCT7030

Notes to Fig.21

1. FIFO_Aand FIFO_Binitially full,

SI_Bheld HIGH in anticipation of

shifting in new data as empty

location bubbles-up.

2. Unload one word from FIFO_B;

SO pulse applied, results in DOR

pulse.

3. DIR_Band SO_Apulse HIGH;

(bubble-up delay after SO_BLOW)

data is loaded into FIFO_Bas a

result of the DIR pulse, data is

shifted out of FIFO_A.

4. DOR_Aand SI_Bgo LOW; flag

indicates the output stage of

FIFO_Ais busy, shift-in to FIFO_Bis

complete.

5. DOR_Aand SI_Bgo HIGH; flag

indicates valid data is again

available at FIFO_Aoutput stage,

SI_Bis held HIGH, awaiting

bubble-up of empty location.

6. DIR_Agoes HIGH; (bubble-up

delay after SO_ALOW) an empty

location is present at input stage

of FIFO_A.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.21 FIFO to FIFO communication; output timing under full condition.

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit x 64-word FIFO register; 3-state

74HC/HCT7030

Sequence 1 (Both FIFOs empty, starting shift-in process):

After a MR pulse has been applied FIFO_Aand FIFO_Bare empty. The DOR flags of FIFO_Aand FIFO_Bgo

LOW due to no valid data being present at the outputs. The DIR flags are set HIGH due to the FIFOs being

ready to accept data. SO_Bis held HIGH and two SI_Apulses are applied (1). These pulses allow two data

words to ripple through to the output stage of FIFO_Aand to the input stage of FIFO_B(2). When data arrives

at the output of FIFO_B, a DOR_Bpulse is generated (3). When SO_Bgoes LOW, the first bit is shifted out and

a second bit ripples through to the output after which DOR_Bgoes HIGH (4).

Sequence 2 (FIFO_Bruns full):

After the MR pulse, a series of 64 SI pulses are applied. When 64 words are shifted in, DIR_Bremains LOW

due to FIFO_Bbeing full (5). DOR_Agoes LOW due to FIFO_Abeing empty.

Sequence 3 (FIFO_Aruns full):

When 65 words are shifted in, DOR_Aremains HIGH due to valid data remaining at the output of FIFO_A.

Q_nAremains HIGH, being the polarity of the 65th data word (6). After the 128th SI pulse, DIR remains LOW

and both FIFOs are full (7). Additional pulses have no effect.

Sequence 4 (Both FIFOs full, starting shift-out process):

SI_Ais held HIGH and two SO_Bpulses are applied (8). These pulses shift out two words and thus allow two

empty locations to bubble-up to the input stage of FIFO_B, and proceed to FIFO_A(9). When the first empty

location arrives at the input of FIFO_A, a DIR_Apulse is generated (10) and a new word is shifted into FIFO_A.

SI_Ais made LOW and now the second empty location reaches the input stage of FIFO_A, after which

DIR_Aremains HIGH (11).

Sequence 5 (FIFO_Aruns empty):

At the start of sequence 5 FIFO_Acontains 63 valid words due to two words being shifted out and one word

being shifted in in sequence 4. An additional series of SO_Bpulses are applied. After 63 SO_Bpulses, all

words from FIFO_Aare shifted into FIFO_B. DOR_Aremains LOW (12).

Sequence 6 (FIFO_Bruns empty):

After the next SO_Bpulse, DIR_Bremains HIGH due to the input stage of FIFO_Bbeing empty (13). After

another 63 SO_Bpulses, DOR_Bremains LOW due to both FIFOs being empty (14). Additional SO_Bpulses

have no effect. The last word remains available at the output Q_n.

Fig.22 Waveforms showing the functionality and intercommunication between two FIFOs (refer to Fig.19).

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit x 64-word FIFO register; 3-state

74HC/HCT7030

PACKAGE OUTLINES

See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

December 1990

933835630005 [NXP]

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