934020680127 [NXP]

IC BUF OR INV BASED PRPHL DRVR, Peripheral Driver;


型号：	934020680127
厂家：	NXP
描述：	IC BUF OR INV BASED PRPHL DRVR, Peripheral Driver 驱动接口集成电路
文件：	总11页 (文件大小：122K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level TOPFET

BUK100-50GL

DESCRIPTION

QUICK REFERENCE DATA

Monolithic temperature and

SYMBOL

PARAMETER

MAX.

UNIT

overload protected logic level power

MOSFET in a 3 pin plastic

V_DS

I_D

Continuous drain source voltage

Continuous drain current

13.5

150

125

˚C

mΩ

envelope, intended as a general

purpose switch for automotive

systems and other applications.

P_D

T_j

Total power dissipation

Continuous junction temperature

Drain-source on-state resistance

R_DS(ON)

APPLICATIONS

V_IS= 5 V

General controller for driving

lamps

motors

solenoids

heaters

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Vertical power DMOS output

stage

Low on-state resistance

Overload protection against

over temperature

Overload protection against

short circuit load

Latched overload protection

reset by input

DRAIN

O/V

CLAMP

POWER

INPUT

MOSFET

5 V logic compatible input level

Control of power MOSFET

and supply of overload

protection circuits

RIG

LOGIC AND

derived from input

PROTECTION

Low operating input current

ESD protection on input pin

Overvoltage clamping for turn

off of inductive loads

SOURCE

Fig.1. Elements of the TOPFET.

PINNING - TO220AB

PIN CONFIGURATION

SYMBOL

DESCRIPTION

tab

TOPFET

input

drain

source

tab drain

1 2 3

November 1996

Rev 1.300

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level TOPFET

BUK100-50GL

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DSS

Continuous off-state drain source

V_IS= 0 V

voltage¹

V_IS

I_D

I_DRM

P_D

T_stg

T_j

Continuous input voltage

Continuous drain current

Repetitive peak on-state drain current

Total power dissipation

Storage temperature

T_mb≤25 ˚C; V_IS= 5 V

T_mb≤100 ˚C; V_IS= 5 V

T_mb≤ 25 ˚C; V_IS= 5 V

T_mb≤ 25 ˚C

13.5

8.5

150

˚C

-55

Continuous junction temperature²

normal operation

T_sold

Lead temperature

during soldering

250

˚C

OVERLOAD PROTECTION LIMITING VALUES

With the protection supply provided via the input pin, TOPFET can protect itself from two types of overload.

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_ISP

Protection supply voltage³

for valid protection

Over temperature protection

V_DDP(T)

Protected drain source supply voltage V_IS= 5 V

Short circuit load protection

V_DDP(P)

P_DSM

Protected drain source supply voltage⁴V_IS= 5 V

0.6

Instantaneous overload dissipation

T_mb= 25 ˚C

OVERVOLTAGE CLAMPING LIMITING VALUES

At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

I_DROM

E_DSM

Repetitive peak clamping current

Non-repetitive clamping energy

V_IS= 0 V

200

_mb≤ 25 ˚C; I_DM= 15 A;

_DD≤ 20 V; inductive load

_mb≤ 95 ˚C; I_DM= 4 A;

_DD≤ 20 V; f = 250 Hz

E_DRM

Repetitive clamping energy

ESD LIMITING VALUE

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_C

Electrostatic discharge capacitor

voltage

Human body model;

C = 250 pF; R = 1.5 kΩ

1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.

2 A higher T_jis allowed as an overload condition but at the threshold T_j(TO)the over temperature trip operates to protect the switch.

3 The input voltage for which the overload protection circuits are functional.

4 The device is able to self-protect against a short circuit load providing the drain-source supply voltage does not exceed V_DDP(P)maximum.

For further information, refer to OVERLOAD PROTECTION CHARACTERISTICS.

November 1996

Rev 1.300

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level TOPFET

BUK100-50GL

THERMAL CHARACTERISTICS

SYMBOL PARAMETER

Thermal resistance

CONDITIONS

MIN. TYP. MAX. UNIT

R_{th j-mb}

R_{th j-a}

Junction to mounting base

Junction to ambient

2.5

3.1

K/W

in free air

STATIC CHARACTERISTICS

T_mb= 25 ˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

V_(CL)DSS

Drain-source clamping voltage V_IS= 0 V; I_D= 10 mA

Drain-source clamping voltage V_IS= 0 V; I_DM= 1 A; t_p≤ 300 µs;

δ ≤ 0.01

I_DSS

R_DS(ON)

Zero input voltage drain current V_DS= 12 V; V_IS= 0 V

Zero input voltage drain current V_DS= 50 V; V_IS= 0 V

Zero input voltage drain current V_DS= 40 V; V_IS= 0 V; T_j= 125 ˚C

0.5

100

125

µA

Drain-source on-state

resistance

V_IS= 5 V; I_DM= 7.5 A; t_p≤ 300 µs;

δ ≤ 0.01

mΩ

OVERLOAD PROTECTION CHARACTERISTICS

TOPFET switches off when one of the overload thresholds is reached. It remains latched off until reset by the input.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Short circuit load protection¹T_mb= 25 ˚C; L ≤ 10 µH

E_DS(TO)

t_{d sc}

Overload threshold energy

Response time

V_DD= 13 V; V_IS= 5 V

0.2

0.8

Over temperature protection

T_j(TO)

Threshold junction temperature V_IS= 5 V; from I_D≥ 1 A²

150

˚C

INPUT CHARACTERISTICS

T_mb= 25 ˚C unless otherwise specified. The supply for the logic and overload protection is taken from the input.

SYMBOL PARAMETER

V_IS(TO)Input threshold voltage

I_IS

CONDITIONS

MIN. TYP. MAX. UNIT

V_DS= 5 V; I_D= 1 mA

V_IS= 5 V; normal operation

1.0

1.5

0.2

2.6

2.0

0.35

3.5

Input supply current

V_ISR

Protection reset voltage³

2.0

V_ISR

Protection reset voltage

T_j= 150 ˚C

1.0

I_ISL

V_(BR)IS

R_IG

Input supply current

Input clamp voltage

Input series resistance

V_IS= 5 V; protection latched

I_I= 10 mA

to gate of power MOSFET

0.5

1.2

2.0

kΩ

1 The short circuit load protection is able to save the device providing the instantaneous on-state dissipation is less than the limiting value for

P_DSM, which is always the case when V_DSis less than V_DSPmaximum. Refer to OVERLOAD PROTECTION LIMITING VALUES.

2 The over temperature protection feature requires a minimum on-state drain source voltage for correct operation. The specified minimum I_D

ensures this condition.

3 The input voltage below which the overload protection circuits will be reset.

November 1996

Rev 1.300

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level TOPFET

BUK100-50GL

TRANSFER CHARACTERISTICS

T_mb= 25 ˚C

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

g_fs

Forward transconductance

V_DS= 10 V; I_DM= 7.5 A t_p≤ 300 µs;

δ ≤ 0.01

I_D(SC)

Drain current¹

V_DS= 13 V; V_IS= 5 V

SWITCHING CHARACTERISTICS

T_mb= 25 ˚C. R_I= 50 Ω . Refer to waveform figures and test circuits.

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

t_{d on}

t_r

t_{d off}

t_f

t_{d on}

t_r

t_{d off}

t_f

Turn-on delay time

Rise time

V_DD= 13 V; V_IS= 5 V

resistive load R_L= 4 Ω

V_DD= 13 V; V_IS= 0 V

resistive load R_L= 4 Ω

V_DD= 13 V; V_IS= 5 V

inductive load I_DM= 3 A

V_DD= 13 V; V_IS= 0 V

inductive load I_DM= 3 A

1.5

µs

Turn-off delay time

Fall time

4.5

1.5

Turn-on delay time

Rise time

Turn-off delay time

Fall time

0.5

REVERSE DIODE LIMITING VALUE

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

13.5

UNIT

I_S

Continuous forward current

T_mb≤ 25 ˚C; V_IS= 0 V

REVERSE DIODE CHARACTERISTICS

T_mb= 25 ˚C

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

V_SDS

t_rr

Forward voltage

I_S= 15 A; V_IS= 0 V; t_p= 300 µs

not applicable²

1.0

1.5

Reverse recovery time

ENVELOPE CHARACTERISTICS

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

L_d

L_s

Internal drain inductance

Internal source inductance

Measured from contact screw on

tab to centre of die

Measured from drain lead 6 mm

from package to centre of die

Measured from source lead 6 mm

from package to source bond pad

3.5

4.5

7.5

1 During overload before short circuit load protection operates.

2 The reverse diode of this type is not intended for applications requiring fast reverse recovery.

November 1996

Rev 1.300

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level TOPFET

BUK100-50GL

Normalised Power Derating

Zth / (K/W)

BUK100-50GL

PD%

120

110

100

D =

0.5

0.2

0.1

0.05

0.1

0.02

D =

0.01

Tmb /

100

120

140

1E-07

1E-05

1E-03

t / s

1E-01

1E+01

Fig.2. Normalised limiting power dissipation.

P_D% = 100 P_D/P_D(25 ˚C) = f(T_mb)

Fig.5. Transient thermal impedance.

Z_{th j-mb}= f(t); parameter D = t_p/T

Normalised Current Derating

ID%

ID / A

BUK100-50GL

VIS / V =

120

110

100

5.5

4.5

3.5

2.5

Tmb /

100

120

140

VDS / V

Fig.3. Normalised continuous drain current.

I_D% = 100 I_D/I_D(25 ˚C) = f(T_mb); conditions: V_IS= 5 V

Fig.6. Typical output characteristics, T_j= 25 ˚C.

ID = f(V_DS); parameter V_IS; t_p= 250 µs & t_p< t_{d sc}

ID & IDM / A

BUK100-50GL

ID / A

BUK100-50GL

100

VIS / V =

tp =

10 us

5.5

RDS(ON) = VDS/ID

100 us

1 ms

4.5

10 ms

100 ms

3.5

Overload protection characteristics not shown

10 100

0.1

VDS / V

Fig.4. Safe operating area. T_mb= 25 ˚C

I_D& I_DM= f(V_DS); I_DMsingle pulse; parameter t_p

Fig.7. Typical on-state characteristics, T_j= 25 ˚C.

ID = f(V_DS); parameter V_IS; t_p= 250 µs

November 1996

Rev 1.300

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level TOPFET

BUK100-50GL

RDS(ON) / Ohm

0.20

BUK100-50GL

Normalised RDS(ON) = f(Tj)

VIS / V =

3.5

4.5

5.5

1.5

1.0

0.5

0.15

0.10

0.05

-60 -40 -20

20 40 60 80 100 120 140

ID / A

Tj /

Fig.8. Typical on-state resistance, T_j= 25 ˚C.

Fig.11. Normalised drain-source on-state resistance.

a = R_DS(ON)/R_DS(ON)25 ˚C = f(T_j); I_D= 7.5 A; V_IS= 5 V

R_DS(ON)= f(I_D); parameter V_IS; t_p= 250 µs

ID / A

BUK100-50GL

td sc / ms

BUK100-50GL

100

PDSM

0.1

0.01

0.1

VIS / V

PDS / kW

Fig.9. Typical transfer characteristics, T_j= 25 ˚C.

Fig.12. Typical overload protection characteristics.

I_D= f(V_IS) ; conditions: V_DS= 10 V; t_p= 250 µs

t_{d sc}= f(P_DS); conditions: V_IS≥ 4 V; T_j= 25 ˚C.

gfs / S

PDSM%

120

BUK100-50GL

100

-60

-40

-20

100 120 140

Tmb / C

ID / A

Fig.10. Typical transconductance, T_j= 25 ˚C.

g_fs= f(I_D); conditions: V_DS= 10 V; t_p= 250 µs

Fig.13. Normalised limiting overload dissipation.

P_DSM% =100 P_DSM/P_DSM(25 ˚C) = f(T_mb)

November 1996

Rev 1.300

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level TOPFET

BUK100-50GL

IIS / uA

BUK100-50GL

Energy & Time

500

400

300

200

100

Time / ms

0.5

25 C

Tj(TO)

Energy / J

150 C

-60

-20

100

140

180

220

Tmb / C

VIS / V

Fig.14. Typical overload protection characteristics.

Conditions: V_DD= 13 V; V_IS= 5 V; SC load = 30 mΩ

Fig.17. Typical DC input characteristics.

I_IS= f(V_IS); normal operation, parameter: T_j

ID / A

BUK100-50GL

IISL / mA

BUK100-50GL

PROTECTION LATCHED

typ.

RESET

NORMAL

VDS / V

VIS / V

Fig.15. Typical clamping characteristics, 25 ˚C.

Fig.18. Typical DC input characteristics, T_j= 25 ˚C.

I_D= f(V_DS); conditions: V_IS= 0 V; t_p≤ 50 µs

I_ISL= f(V_IS); overload protection operated

I_D= 0 A

VIS(TO) / V

IS / A

BUK100-50GL

max.

typ.

min.

-60 -40 -20

Tj /

80 100 120 140

0.2

0.4

0.6

0.8

1.2

1.4

VSD / V

Fig.16. Input threshold voltage.

V_IS(TO)= f(T_j); conditions: I_D= 1 mA; V_DS= 5 V

Fig.19. Typical reverse diode current, T_j= 25 ˚C.

I_S= f(V_SDS); conditions: V_IS= 0 V; t_p= 250 µs

November 1996

Rev 1.300

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level TOPFET

BUK100-50GL

VDD

VDD = VCL

: adjust for correct ID

TOPFET

D.U.T.

VIS

ID measure

0R1

Fig.20. Test circuit for resistive load switching times.

Fig.23. Test circuit for inductive load switching times.

RESISTIVE TURN-ON

VDS / V

BUK100-50GL

INDUCTIVE TURN-ON

VDS / V

BUK100-50GL

td on

VIS / V

ID / A

VIS / V

ID / A

90%

10%

time / us

Fig.21. Typical switching waveforms, resistive load.

Fig.24. Typical switching waveforms, inductive load.

_DD= 13 V; I_D= 3 A; R_I= 50 Ω, T_j= 25 ˚C.

V_DD= 13 V; R_L= 4 Ω; R_I= 50 Ω, T_j= 25 ˚C.

RESISTIVE TURN-OFF

td off

BUK100-50GL

VDS / V

INDUCTIVE TURN-OFF

BUK100-50GL

VDS / V

td off

VIS / V

90%

VIS / V

90%

ID / A

90%

ID / A

10%

time / us

Fig.22. Typical switching waveforms, resistive load.

Fig.25. Typical switching waveforms, inductive load.

V_DD= 13 V; R_L= 4 Ω; R_I= 50 Ω, T_j= 25 ˚C.

V_DD= 13 V; I_D= 3 A; R_I= 50 Ω, T_j= 25 ˚C.

November 1996

Rev 1.300

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level TOPFET

BUK100-50GL

EDSM%

120

Iiso normalised to 25 C

110

100

1.5

0.5

Tmb / C

100

120

140

-60

-20

Tj / C

100

140

180

Fig.26. Normalised limiting clamping energy.

E_DSM% = f(T_mb); conditions: I_D= 15 A; V_IS= 5 V

Fig.29. Normalised input current (normal operation).

I_IS/I_IS25 ˚C = f(T_j); V_IS= 5 V

V(CL)DSS

VDS

Iisl normalised to 25 C

VDD

1.5

VDS

VIS

TOPFET

-ID/100

D.U.T.

Schottky

R 01

shunt

RIS

0.5

-60

-20

Tj / C

100

140

180

Fig.27. Clamping energy test circuit, R_IS= 50 Ω.

Fig.30. Normalised input current (protection latched).

I_ISL/I_ISL25 ˚C = f(T_j); V_IS= 5 V

E_DSM= 0.5 LI_D²V_(CL)DSS/(V_(CL)DSS− V_DD

)

Idss

1 mA

100 uA

10 uA

1 uA

typ.

100 nA

Tj / C

100

120

140

Fig.28. Typical off-state leakage current.

_DSS= f(T_j); Conditions: V_DS= 40 V; I_IS= 0 V.

November 1996

Rev 1.300

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level TOPFET

BUK100-50GL

MECHANICAL DATA

Dimensions in mm

Net Mass: 2 g

4,5

max

10,3

max

1,3

3,7

2,8

5,9

min

15,8

max

3,0 max

not tinned

3,0

13,5

min

1,3

1 2 3

max

(2x)

0,9 max (3x)

0,6

2,4

2,54 2,54

Fig.31. TO220AB; pin 2 connected to mounting base.

Notes

1. Refer to mounting instructions for TO220 envelopes.

2. Epoxy meets UL94 V0 at 1/8".

November 1996

Rev 1.300

Philips Semiconductors

Product specification

PowerMOS transistor

Logic level TOPFET

BUK100-50GL

DEFINITIONS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and

operation of the device at these or at any other conditions above those given in the Characteristics sections of

this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Philips Electronics N.V. 1996

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the

The information presented in this document does not form part of any quotation or contract, it is believed to be

accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under patent or other

industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these

products can be reasonably expected to result in personal injury. Philips customers using or selling these products

for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting

from such improper use or sale.

November 1996

Rev 1.300

934020680127 [NXP]

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