934055781127 [NXP]

TRANSISTOR 50 A, 200 V, 0.04 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-247, PLASTIC PACKAGE-3, FET General Purpose Power;


型号：	934055781127
厂家：	NXP
描述：	TRANSISTOR 50 A, 200 V, 0.04 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-247, PLASTIC PACKAGE-3, FET General Purpose Power 局域网开关脉冲晶体管
文件：	总7页 (文件大小：86K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Philips Semiconductors

Product specification

N-channel TrenchMOS transistor

PSMN040-200W

FEATURES

SYMBOL

QUICK REFERENCE DATA

• ’Trench’ technology

• Very low on-state resistance

• Fast switching

V_DSS= 200 V

I_D= 50 A

• Low thermal resistance

R_DS(ON)≤ 40 mΩ

GENERAL DESCRIPTION

PINNING

SOT429 (TO247)

SiliconMAXproductsusethelatest

Philips Trench technology to

achieve the lowest possible

on-state resistance in each

package at each voltage rating.

DESCRIPTION

gate

drain

Applications:-

• d.c. to d.c. converters

• switched mode power supplies

source

drain

tab

The PSMN040-200W is supplied in

the SOT429 (TO247) conventional

leaded package.

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DSS

V_DGR

V_GS

I_D

Drain-source voltage

Drain-gate voltage

Gate-source voltage

Continuous drain current

T_j= 25 ˚C to 175˚C

T_j= 25 ˚C to 175˚C; R_GS= 20 kΩ

200

± 20

˚C

T_mb= 25 ˚C

T_mb= 100 ˚C

T_mb= 25 ˚C

I_DM

P_D

T_j, T_stg

Pulsed drain current

Total power dissipation

Operating junction and

storage temperature

200

300

175

- 55

AVALANCHE ENERGY LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

E_ASNon-repetitive avalanche

CONDITIONS

MIN.

MAX.

UNIT

Unclamped inductive load, I_AS= 50 A;

t_p= 100 µs; T_jprior to avalanche = 25˚C;

661

energy

V_DD≤ 25 V; R_GS= 50 Ω; V_GS= 10 V; refer

to fig:15

I_AS

Non-repetitive avalanche

current

August 1999

Rev 1.000

Philips Semiconductors

Product specification

N-channel TrenchMOS transistor

PSMN040-200W

THERMAL RESISTANCES

SYMBOL PARAMETER

R_{th j-mb}Thermal resistance junction

CONDITIONS

TYP.

MAX.

UNIT

0.5

K/W

to mounting base

Thermal resistance junction in free air

to ambient

R_{th j-a}

K/W

ELECTRICAL CHARACTERISTICS

T_j= 25˚C unless otherwise specified

SYMBOL PARAMETER

V_(BR)DSSDrain-source breakdown

CONDITIONS

MIN. TYP. MAX. UNIT

V_GS= 0 V; I_D= 0.25 mA;

200

voltage

T_j= -55˚C

178

V_GS(TO)

Gate threshold voltage

V_DS= V_GS; I_D= 1 mA

2.0

1.0

3.0

0.05

4.0

116

100

500

mΩ

µA

T_j= 175˚C

T_j= -55˚C

R_DS(ON)

Drain-source on-state

resistance

Gate source leakage current V_GS= ±10 V; V_DS= 0 V

Zero gate voltage drain

current

V_GS= 10 V; I_D= 25 A

T_j= 175˚C

I_GSS

I_DSS

V_DS= 200 V; V_GS= 0 V;

T_j= 175˚C

Q_g(tot)

Q_gs

Q_gd

Total gate charge

Gate-source charge

Gate-drain (Miller) charge

I_D= 50 A; V_DD= 160 V; V_GS= 10 V

183

t_{d on}

t_r

t_{d off}

t_f

Turn-on delay time

Turn-on rise time

Turn-off delay time

Turn-off fall time

V_DD= 100 V; R_D= 3.9 Ω;

V_GS= 10 V; R_G= 5.6 Ω

Resistive load

230

L_d

L_s

Internal drain inductance

Internal source inductance

Measured from tab to centre of die

Measured from drain lead to centre of die

Measured from source lead to source

bond pad

3.5

4.5

7.5

C_iss

C_oss

C_rss

Input capacitance

Output capacitance

Feedback capacitance

V_GS= 0 V; V_DS= 25 V; f = 1 MHz

9530

732

380

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

T_j= 25˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

I_S

Continuous source current

(body diode)

Pulsed source current (body

diode)

Diode forward voltage

200

1.2

I_SM

V_SD

I_F= 25 A; V_GS= 0 V

0.85

t_rr

Q_rr

Reverse recovery time

Reverse recovery charge

I_F= 20 A; -dI_F/dt = 100 A/µs;

V_GS= 0 V; V_R= 30 V

160

1.4

µC

August 1999

Rev 1.000

Philips Semiconductors

Product specification

N-channel TrenchMOS transistor

PSMN040-200W

Transient thermal impedance, Zth j-mb (K/W)

Normalised Power Derating, PD (%)

100

0.1

D = 0.5

0.2

0.1

0.05

0.02

D = tp/T

0.01

single pulse

1E-05

0.001

1E-06

1E-04

1E-03

1E-02

1E-01

1E+00

100

125

150

175

Pulse width, tp (s)

Mounting Base temperature, Tmb (C)

Fig.1. Normalised power dissipation.

PD% = 100 P_D/P_{D 25 ˚C}= f(T_mb)

Fig.4. Transient thermal impedance.

Z_{th j-mb}= f(t); parameter D = t_p/T

Drain Current, ID (A)

Tj = 25 C

Normalised Current Derating, ID (%)

VGS = 10V

8 V

6 V

100

5 V

4.8 V

4.6 V

4.4 V

4.2 V

100

125

150

175

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

Mounting Base temperature, Tmb (C)

Drain-Source Voltage, VDS (V)

Fig.2. Normalised continuous drain current.

Fig.5. Typical output characteristics, T_j= 25 ˚C.

I_D= f(V_DS)

ID% = 100 I_D/I_{D 25 ˚C}= f(T_mb); V_GS≥ 10 V

Peak Pulsed Drain Current, IDM (A)

1000

Drain-Source On Resistance, RDS(on) (Ohms)

0.2

4.6 V

4.4 V

4.2 V

Tj = 25 C

0.18

0.16

0.14

0.12

0.1

RDS(on) = VDS/ ID

tp = 10 us

100

4.8 V

100 us

1 ms

0.08

0.06

0.04

0.02

5 V

D.C.

10 ms

100 ms

VGS = 10V

100

1000

Drain-Source Voltage, VDS (V)

Drain Current, ID (A)

Fig.3. Safe operating area

I_D& I_DM= f(V_DS); I_DMsingle pulse; parameter t_p

Fig.6. Typical on-state resistance, T_j= 25 ˚C.

R_DS(ON)= f(I_D)

August 1999

Rev 1.000

Philips Semiconductors

Product specification

N-channel TrenchMOS transistor

PSMN040-200W

Threshold Voltage, VGS(TO) (V)

Drain current, ID (A)

4.5

VDS > ID X RDS(ON)

maximum

typical

3.5

2.5

175 C

minimum

1.5

Tj = 25 C

0.5

-60 -40 -20

20 40 60 80 100 120 140 160 180

Junction Temperature, Tj (C)

Gate-source voltage, VGS (V)

Fig.7. Typical transfer characteristics.

I_D= f(V_GS)

Fig.10. Gate threshold voltage.

V_GS(TO)= f(T_j); conditions: I_D= 1 mA; V_DS= V_GS

Transconductance, gfs (S)

VDS > ID X RDS(ON)

Tj = 25 C

Drain current, ID (A)

100

1.0E-01

1.0E-02

1.0E-03

1.0E-04

1.0E-05

1.0E-06

175 C

minimum

typical

maximum

0.5

1.5

2.5

3.5

4.5

10 15 20 25 30 35 40 45 50 55 60

Drain current, ID (A)

Gate-source voltage, VGS (V)

Fig.8. Typical transconductance, T_j= 25 ˚C.

g_fs= f(I_D)

Fig.11. Sub-threshold drain current.

I_D= f(V_GS); conditions: T_j= 25 ˚C

Capacitances, Ciss, Coss, Crss (nF)

Normalised On-state Resistance

100

2.9

2.7

2.5

2.3

2.1

1.9

1.7

1.5

1.3

1.1

0.9

0.7

0.5

Ciss

Coss

Crss

0.1

-60 -40 -20

20 40 60 80 100 120 140 160 180

0.1

100

Junction temperature, Tj (C)

Drain-Source Voltage, VDS (V)

Fig.9. Normalised drain-source on-state resistance.

R_DS(ON)/R_{DS(ON)25 ˚C}= f(T_j)

Fig.12. Typical capacitances, C_iss, C_oss, C_rss.

C = f(V_DS); conditions: V_GS= 0 V; f = 1 MHz

August 1999

Rev 1.000

Philips Semiconductors

Product specification

N-channel TrenchMOS transistor

PSMN040-200W

Gate-source voltage, VGS (V)

Maximum Avalanche Current, I_AS(A)

100

ID = 50 A

Tj = 25 C

VDD = 40 V

25 C

VDD = 160 V

Tj prior to avalanche = 150 C

100 120 140 160 180 200

0.001

0.01

0.1

Avalanche time, t_AV(ms)

Gate charge, QG (nC)

Fig.13. Typical turn-on gate-charge characteristics.

V_GS= f(Q_G)

Fig.15. Maximum permissible non-repetitive

avalanche current (I_AS) versus avalanche time (t_AV);

unclamped inductive load

Source-Drain Diode Current, IF (A)

VGS = 0 V

175 C

Tj = 25 C

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Source-Drain Voltage, VSDS (V)

1.1 1.2

Fig.14. Typical reverse diode current.

I_F= f(V_SDS); conditions: V_GS= 0 V; parameter T_j

August 1999

Rev 1.000

Philips Semiconductors

Product specification

N-channel TrenchMOS transistor

PSMN040-200W

MECHANICAL DATA

Plastic single-ended through-hole package; heatsink mounted; 1 mounting hole; 3-lead TO-247

SOT429

(1)

20 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

UNIT

1.9

1.7

1.2

0.9

3.7

3.3

2.6

2.4

7.5

7.1

15.7

15.3

6°

4°

17°

13°

5.3

4.7

2.2

1.8

3.2

2.8

0.9

0.6

4.0

3.6

3.5

3.3

5.45

5.3

0.4

Note

1. Tinning of terminals are uncontrolled within zone L

REFERENCES

EUROPEAN

PROJECTION

OUTLINE

VERSION

ISSUE DATE

IEC

JEDEC

EIAJ

98-04-07

99-08-04

SOT429

TO-247

Fig.16. SOT429; pin 2 connected to mounting base

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent

damage to MOS gate oxide.

2. Refer to mounting instructions for SOT429 envelope.

3. Epoxy meets UL94 V0 at 1/8".

August 1999

Rev 1.000

Philips Semiconductors

Product specification

N-channel TrenchMOS transistor

PSMN040-200W

DEFINITIONS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and

operation of the device at these or at any other conditions above those given in the Characteristics sections of

this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Philips Electronics N.V. 1999

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the

The information presented in this document does not form part of any quotation or contract, it is believed to be

accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under patent or other

industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these

products can be reasonably expected to result in personal injury. Philips customers using or selling these products

for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting

from such improper use or sale.

August 1999

Rev 1.000

934055781127 [NXP]

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